Common instruction mnemonics for microprocessors

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COMMON INSTRUCTION MNEMONICS FOR MICROPROCESSORS

J.D. Nicoud

Mini and Microcomputer Laboratory

Swiss Federal I n s t i t u t e of Technology

Lausanne, Switzerland

Abstract

New, more consistent mnemonics are proposed for mi-

croprocessors. Explicit mnemonics and simple addres-

sing rules make it much easier to read assembly pro-

grams. All the data transfer instructions have the

general form "LOAD destination, source". Arithmetic

instructions are "OP destination, source" (destina-

tion get destination OP source) and jump instruc-

tions "JUMP, test destination" or "CALL, test desti-

nation". Up to now, reference cards have been prepa-

red for the Intel 8080 and Motorola 6800; they are

oconvenient to use and allow occasional hand-assem-

bling. Cross-assemblers on PDP-11 and NOVA minicom-

puters are available.

I. In t roduct ion

Microprocessors are becoming a common tool for the electronics engineer: more than lO different one- chip microprocessors wi l l be available by the end of 1975, each one requiring different hardware and software. The choice problem wi l l not be easy; hardware cr i ter ia such as cost, speed and system comple- x i ty are fairy easy to size-up; scanning the instruction set gives a rough idea of the possibi l i t ies of the microprocessor. But in order to really compare two microprocessors, i t is necessary to design a complete system with both machine, and write precise benchmarks, which may lead to various hardware/software trade-offs depending on the processor. This is d i f f i cu l t to do ef f ic ient ly now because of the rather considerable work implied in getting familiar with any of the new microprocessors: documentation is scarce, application notes nonexistent or incomple- te, and mnemonics are very confusing. Hence most of the users l imi t themselves to only one microprocessor and are just waiting for the promised software support and the announced new chips.

I t is possible that in a few years a limited number of microprocessors wi l l have won the race, but until then i t wi l l be very d i f f i cu l t to find one's way in the microprocessor jungle, as far as efficiency and optimization are concerned. Hardware and software standards are needed, and this paper proposes to standardize the basic description of the instruction set, in terms of the assembly language mnemonics.

Two in i t i a l motivations have triggered a search for more consistent mnemonics. The f i r s t one has been that the Intel 8080 mnemonics are very bad: many users (at least four to my knowledge) have modi- fied these 8080 mnemonics on different ways when writing their own cross-assemblers. A lot of time is necessary to get familiar with these mnemonics, primarily because of the poor documentation and the lack of a quick reference card. The other mo- tivation has been that various processors, for instance the Intel 8080, Motorola 6800, RCA COSMAC, Signetics 2650, Fairchild F8, etc. are designed for the same category of applications. Benchmarks for these processors should be written in a minimum amount of time by the same engineers concentrating on the part icularit ies of the processors and not on t r i v ia l notation problems. This requires that the same mnemonics are used for the same func- tions.

I t is evident that the use of standardized mnemonics is only a part of the need. Common high level languages are also required, leaving the user with the l iberty of choosing the best language for his application.

2. General cha rac te r i s t i c s of mnemo-nics

A microprocessor is characterized by i ts register organization and i ts instruction set, plus many part iculari t ies. Most of the notations can be standardized and the following notations seem to be very convenient for the most recent 8-bit microprocessors.

Registers are named by simple letters A(accumu- lator), B, C, .. . or by let ter R and a subscript i f there are more than few registers. Register pairs are designated by two letters AB, CD, SP (stack pointer), IX (index register) or by let ter P and a subscript.

Addressing schemes are named:

- Absolute i f fu l l address is a part of the instruc tion (ex: LOAD A, ADR)

- Indexed i f address is relocated by an index register, with a possible displacement (ex: LOAD A,(IX)+DISP)

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- Relative i f the instruction gives the difference between the address desired and the present program counter value (ex: LOAD A,.+lO)

- Deferred i f the memory location reached f i r s t contains the desired address(ex: LOAD A,~INDAD) Immediate i f instruction contains the data i t se l f (ex: LOAD A,# DATA).

Usually, the programmer w i l l not expl ic i te ly use relative addressing: the assembler i t se l f w i l l de- cide which is the best way to reach the wanted location. This may cause some problems because of the usual limited range for relative addressing.

As usual , a sometimes confusing ident i f icat ion is made between a register or memory location and i ts contents. Parentheses denote that the contents of a register are used as an address to point to a memory location (or i ts contents). Symbol of indi- rection ~ has basically the same meaning as parentheses and is dif ferent because i t can be combined with them. ?(IX) means deferred indexed addressing.

The instruction set may be divided in four categories: a) Data transfers between registers and memory b) Arithmetic c) Jump d) Misceleanous.

a) The mnen~onic "LOAD" is mainly used in the f i r s t category, followed by destination and source registers or memory locations: LOAD d,s. This unique notation has been preferred to the very often used "MOVE" for various reasons. The f i r s t one is that the "destination gets source" notation is widely used in mathematics and high level programming languages. The other is that in arithmetic operations also, the order destination-source is more natural.

The store instruction is not used: no major d i f - ference exists between registers, memories, and for some processors, peripherals; the old load/ store concept is of a limited interest with the new multiregister architectures.

Exchange (EX) of registers, PUSH and POP on stack instructions are in the same category.

Figure l gives a few examples of data transfer mnemo-nics for the Intel 8080 and allow comparison with the original 8080 mnemonics.

b) Arithmetic instructions have the general struc- ture "OP d,s", which means "destination device (register or location) gets the result of the operation between d and s". Almost every processor has the two-operand instructions ADD, ADDC (add with carry), SUB~ SUBC, AND, OR XOR, COMP (compare) and the one-operand instructions INC, DEC, CPL (Is-complement), NEG (negate, 2s-complement), RR (rotate r ight) , RRC (rotate r ight with carry), RL (rotate l e f t ) , RLC, CL (clear) SET, TEST (update flags). The operand can be are- gister or a memory location, or a single b i t of a status register; in that case, the b i t - l e t te r is concatenated to the mnemonic to avoid confu- sion (ex: CPL A: complement register A, CPLC: complement b i t C).

Jump instructions can be classified in three major categories: - Jump unconditionally and branch on condition - Call subroutine with or without condition - Return from subroutine with or without condi-

tion.

Various notations for the corresponding mnemonics have been experimented. For instance, a jump to label ADDR i f previous result is positive can be written

JP ADDR ( In te l ) ; BPL ADDR (Motorola); JPL ADDR; JUMP ADDR,PL; BRAN ADDR,PL; JMPPL ADDR; JUMP/PL ADDR; JUMP,PL ADDR; etc.

Experienced programmers have an immediate pre- ference, depending on the machine they are used to program. Novices prefer the most exp l ic i t instructions, and since mnemo-nics are mainly inten- ted for engineers without programming sk i l l s , the notation JUMP,PL ADDR has been chosen.An other ad. vantage is that overall l e g i b i l i t y of the program is improved because the 7-1etter mnemo-nics of these important instructions make them appear clearly in a l i s t ing ( f ig. 2). The objection that these mnemo-nics are longer to type and to print is val id, but the increase in time is negligible, specially i f compared to the time usually lost because of misunderstanding or confusing mnemonics.

For instance, i t may seem that JPL is as clear and shorter than JUMP,PL.But the use of JPL implies the use of CPL in.place of CALL,PL, which in turn obliges the use of a less evident mnemonic for complement instruction. The use of jump

;E~ I_E OF INSTRUCTIONS: SEE INTEL BOOKLE[ "FR17~i CFIJ TO SF.#:TWAG~E", PAGE 17

; M i ~ N I C S IN TEL L O ~ I A , B ;MOV A,B LOAD A,#23. ;MVI A,23 LOAD A,4098. ;LDA 4098. LOAD A, KkL) ;NOV A,M LOAD A,(I-~t) ;Ll)~e~( B LOAD HL,4098.;LXIH 4098. LOA~[m A, (HL) ;NOV A,M POP AI-" ; POF' A EX (SF') ,HL ;X'THL JLW'IF' (I-IL; ; F'CFL

;LOAD A WITH REGISTER B ;LOAD A WITH DATA IM~I)IATE 23 DECIMAL ;LOAD A WITH CDN[£NT OF MEMORY LOCATIO~I 4098 ~LOAIJ A USIN~ PAIR HI_ AS AI)I~ES~ ;LOAD A USING FAIR BC AS ADDRESS ;LOAD A... ;..USING LOC 4098 [ECIMAL ;LOAD A AND FLAGS FROM STACK ; E X C ~ T(]F' OF" STACK WITH HL ;LOAD PC WITH HI_ (JLIHP TO LOC AI)Br~ES~:~EII BY Hi.)

Fig. l.

Comparison between

mnemo-nics and Intel

mnemonics for some

data transfer

instructions.

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.TITLE RPR68 JQBN 20.1.75/6.2.75

;CALL R£AI': ; REAP AND ECHO CH~<ACTER FROM KB WITH []L4RACTER READ IN A ; REMOVE PARITY BIT ~ CHANGE L ~ CASE

;CALL PRINT: ; PRINT CHARACTER IN A ;IX] NOT CHANGE B, IX

SKB= 40210 KB = 40010 STT= 40310 TT = 40010

.LOC 37700

REAII: TEST SKB ;TEST KEYBORD FLAG JL~,SC R'EAD ;TEST AGAIN IF BUFFER MOT FULL LOAD A,K~ ;READ KEYBOARD AND A ,#177 ;STRIP PARITY BIT COil' A,#140 ;TEST BIT FOR LOWER CASE JU~',CS F~INT ;JUMP IF ASCII COIE LO~-R THAN 140 SUB A,#40 ;CHA~. LO~ER TO UFI:~ZR CASE

PRINT: TEST STT ;TEST F'RINTER FLAG 3UtIP,SC PRINT ;TEST AGAIN IF NOT READY LOAD TT,A ;PRINT RET

.£N~

Fig. 2. Sample source program for the Motorola 6800.

i ns t ruc t i on , which looks d i f f e r e n t from other ins t ruc t ions , has appeared to be very convenient.

The mnemonic JUMP has been chosen for a branch ins t ruc t ion for two reasons: the same mnemonic CALL is used for "ca l l always" and "ca l l condi- t i o n a l " , hence i t is not consistent to have two d i f f e r e n t mnemonics for "jump ~lways)" and "branch (on cond i t ions) " ; jump is preferable to branch because i t does not have to be abbreviated confusions and typing errors w i l l be less f re - quent.

Hence, the mnemo-nics for the jump ins t ruc t ions have one of the fo l lowing forms:

JUMP ADDR Jump uncondi t iona l ly to ADDR JUMP,XX ADDR Jump i f tes t XX true to ADDR CALL ADDR Call rout ine ADDR CALL,XX ADDR Call i f tes t XX true rout ine ADDR RET Return from subroutine RET,XX Return i f tes t XX true.

Various addressing schemes can be used, depending on the processor. Mnemo-nics for tests are preferably two - le t te rs , usual ly g iv ing a c lear enough abbreviat ion ("VC" overf low b i t c leared, "GE" ~reater or equal, etc.#. These tests depend usual ly only on The values of the f lag reg is ters which are not loaded at every ins t ruc t ion . I t is imPortant to think in terms of these f l ags , which are often used for non-ar i thmetic opera- t ions: "SC" (sign b i t c lear) is often used for test ing i f a peripheraT is ready and is equiva- lent to "PL" (plus (pos i t i ve ) r e s u l t ) , which can a l t e r n a t i v e l y be used, and is preferable only i f the tes t concerns a signed number.

I t is necessary to be careful with the mnemonics of the ar i thmet ic tests fo l lowing a compare or subtract ins t ruc t ion : "LT" ( less than) applies to two signed numbers in 2s-complementary form (7 b i ts plus s ign) , "CS" (~arry ~et) m~ans also lower than, but for two 8 - b i t pos i t i ve integers.

d) Misceleaneous instructions include mainly INP (input), OUT (output), ION (interrupt on), IOF (interrupt of f) , TRAP (software interrupt), NOP (no op, idle), WAIT (halt, wait for interrupt).

Input and output instructions are in fact data transfer instructions, and they wil l appear as LOAD instructions in many microprocessors.Howe- ver, i f the I/O transfer concerns only one accu- mulator, input and output instructions are convenient.

In each group other more special ins t ruc t ions ex i s t , depending on the processor. The notat ion for these addi t ional mnemo-nics is e i the r inspired from the mnemo-nics used for s im i l a r ins t ruc t ions or is iden- t i ca l to the or ig ina l manufacturer's mnemonics.

Numerical values for addresses, ins t ruc t ions and data can be wr i t ten e i ther in octal or in hexadecimal. I f no habi t p re -ex is ts , octal should be prefer - red for several reasons: ins t ruc t ion coding (hand- assembling) is more easy (see example in -~ 4); confusions between numbers and labels are avoided i f numbers do not include l e t t e r s ; octal numbers are also more easy to read and to type on a keyboard. The only drawback is the sometimes necessary conver- sion in two bytes, very easy to learn (see the acompanying In te l mnemonic reference card).

3. So f twa re suppo r t f o r mnemo-nics

Changing the manufacturer's notations implies to wr i te a new assembler, which may seem a considerable waste of time. However, software support pro- vided by the microprocessor manufacturers is up to now very weak, not cheaply appl icable, and very often not adapted to user's need. I f the user wants to change from one processor to another , not only the mnemonics change, but also the assembler, ed i to r and debugger ru les, and a new microcomputer may have to be bought. Some standardizat ion is necessary at a l l these leve ls .

010763 JUMF',SC REflD 010703 362 010704 200 010705 02i 010706 INF' KB 01070,9 333 010707 010 010710 RND R,#177 0 i 0 ? 1 0 3 4 6 Q16711 177 010712 COMP ~ , # i 4 0 010712 376 010713 140 010714 JUMP, C5 PRINT 010714 332 010715 321 010716 021 01071? SUB R,#40 010717 326 ~ t 0 7 2 ~ 040

;READ CHARRC.T£;~

;REt'lOYE F'FIRI7'~' BIT

.; TEST IF LOWE£ CASE

;CHRNGE LGHEF: ;0 UF'

010721 PRINT: PUSH AF ~SRVE CHRRhCTER 010721 365 010722 F'RZNI: INP STT ;TEST £F R£RDY 01~722 333

Fig. 3. Sample of program for the Intel 8080, assem-

bled with the PDPI1 (compare with fig. 2).

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The Mini and Microcomputer Laboratory of the Inst i- tute of Technology of Lausanne is working in that direction. The mnemo-nics have been used for several months and they have proved to be very easy to learn and convenient to use. Up to now, Intel 8080 and Motorola 6800 instruction sets have been con- verted in mnemo-nics and cross-assemblers have been written for both, using both the macroassembler of the RT-II (or DOS) on a PDP l l /40 and the macroassembler on a Nova. Figure 3 gives an example of an assembly l is t ing typed by the cross-assembler running on PDP I I . Later this year, resident assemblers wi l l also run on the microprocessor i t se l f . Similar work wi l l be done for the RCA COSMAC, Signetics PIP, Intel 4040, etc., as soon as these processors wi l l be available to us.

The use of the macroassembler of a minicomputer allows to write rather easily a cross-assembler for a microprocessor. Few of the symbols chosen for the mnemo-nics may seem d i f f i cu l t to be recognized by a given macroassembler. I t is however always possible, by using a more complex analysis of the instruction: the convenience of al l the users of the assembler is more important than some saving of time of the programmer writing once the assembler.

4. In te l 8080 and Motorola 6800 mnemo-nics

The ins t ruc t i on reference card fo r In te l 8080 ( f i g . 4 ) and Motorola 6800 ( f i g . 6 ) microprocessors are prima- r i l y machine i ns t ruc t i on reference cards. They con- ta in a l l the necessary informat ion about the processor, to the programmer's point of view, with of course a lot of evident definitions and conventions not expl ic i tely mentioned. Register organization, with symbols used for registers, register pairs and status bits are the f i r s t things to get familiar with. Instructions themselves are easy to understand. For the detailed effect of some instructions (e.g. test, sh i f t ) , i t may be necessary to check the manufacturer's complete description.

the two devices. The conventions for the stack, restart and interrupt procedures are also summarized in order to quickly remove al l the hesitations which may suddenly appear, especially i f one has formerly studied many processors.

When debugging a program, changes or replacements of instructions can often be made directly in the memory, reducing the number of consecutive assemblings, and saving time. Instruction l i s t in numerical order ( f ig .5 and 7 ) is very useful when checking memory contents.

Examples of figure 8 show more samples of programs, written for the Motorola and the Intel 8080. The ease of reading an assembly program written with mnemo-nics is evident and allows the programmer to use more significant comments and make the program more easy to understand.

5. Conclusion

Multiplication of equipments and users implies some standardization. This has (more or less) been done for integrated circuits, peripherals and high level languages. I t has s t i l l to be done for assembly languages. Even i f i t may take some time before the manufacturers commit themselves to any standard, i t wi l l happen because the users wi l l have to get familiar with various microprocessors and they need to have their work done simpler, faster and more ef f ic ient ly.

The attempt presented in this paper has widely bene- f i ted from the work done by Rick Merril l from Digital Equipment (Maynard, Mass.) and Mike Lind- heim~r from Analog Devices (Westwood, Mass.). The author is also very grateful to G~rard Gris and Ren6 Sommer from the Swiss Institute of Technology (Lausanne) for their expert work in writing the software support for the mnemo-nics.

Hand assembling and disassembling is very easy, espe- ;~HO~STHE UIFFE~HC~S ~T~-~NI~4~T~A~:.M4~NI~ c ia l ly in octal. For instance: S.'~,L(~ ~,,ST~C~

INTEL 8080

LOAD A,(HL) = 100+70+6 = 176 One byte i ns t r : Load A with content of location addressed by HL

MOTOROLA 6800

LOAD A,(IX)+8 = 206+0+40=246 Two-byte i ns t r : Load A with the content of location addressed

by IX (indexed by IX without displacement)

INTEL 8080

SUB A,#31 = 220+106 = 326 Two-byte i ns t r : Subtract to A number 31

ION LOAJ) IX,¢TAI~_E LO(4J R, (IX) JUttP, EO F'F~J LOAb A, (IX)*1 COf~ A,#'A JUt~ M; F~2 C~. R INC IX,SP LO#4# tIX)-2,B AD[W~ A, ¢10<) JLk~, H I F~G3 ~JB A,B

;,~ F,<R~A/~ FOR INTEL ; ~ TFE IIIFF£R~NC~S I'cETWEEN

SAI~/'L£ : LO~ HE,#~ LO¢~ A, (HI-) RLC A JLW'F', HE FTCOG 1

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MOTOROLA 6800

SUB B,#31 = 200+I00+0 = 300 Subtract to B number 31.

Two byte instr:

The sequence for the low order and high order byte of a 16-bit word stored in the memory appears clearly on the programming sheet: i t is different for

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Fig. 8. Sample of

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).(H

L)

=W

AIT

~e

H

--4

H

~1

L

5 L

LO

AD

.d=

#n

Lo

ad d

im

med

iate

with

n (

8-bi

ts)

-~-

(HE)

6

(HL)

"~

A

7 A

m

LOA

D==

p=em

Lo

ad r

egis

ter p

act p

im

med

iate

with

m (

16-b

its)

N

BC

211

DE

P

"~-

HL

5 {-

3-7

--q

LO

AD

~ S

P~H

L Lo

ad s

tack

poi

nter

with

HL

pair

I ~

~ 5

..

..

..

..

..

..

(L

OA

D P

C. H

L =

JM

P (H

L)

: se

e be

low

13

~ L

OA

D.A

=m

Lo

ad a

ccum

ulat

or

with

mem

ory

loca

tion

m

13

~ LO

AD

= m

=A

Lo

ad l

ocat

ion

m w

ith a

ccum

ulat

or c

onte

nt

(sto

re a

ccum

ulat

or

in m

emor

y)

7 ~

LOA

D=

A~

(q)

Load

acc

umul

ator

w

ith c

onte

nt o

f lo

ca-

tion

addr

esse

d by

con

tent

of

pair

q [~

(in

dexe

d to

q w

ithou

t di

sp, .

....

t)

q

~

7 ~

LOA

D~

(q)~

A

Load

wor

d ad

dres

sed

by t

heco

nten

t of

q

to a

ccum

ulat

or

(sto

re a

cc i

ndex

ed)

16

J9

52

I

LO

AD

.HL

=m

Lo

ad H

L pa

ir w

ith t

he c

onte

nt o

f m

emor

y lo

catio

ns m

+ 1

and

m

16

~ L

OA

D.m

=H

L

Load

mem

ory

~oca

tiont

m +

1 a

nd r4

w

ith H

L {s

tore

HL)

4 ~

EX

=D

E=

HL

Exc

hang

e D

E a

nd H

L

1B

~ E

X=(

SP

),=H

L E

xcha

nge

loca

tion

addr

esse

d by

SP

(top

of

=tR

Ck)

wit

hH

L

Sav

e re

gist

er p

air

on t

he s

tack

=

....

,,

13e5

- I

pus.

o.'

(~ad

,oca

tions

SP-I.

SP-~

,:-

.~;--

-~

....

.._

,, __

~- ~

: w

lth

p'a

nd

sub

2

toS

P)

l~--

}-m

~

p,

29

DE

Res

tore

regi

ster

pai

r fr

om t

he

~-

t~

4~

6~

AFHL

10

I~

l~l'

J

PO

P=p

' st

ack

(load

p'w

=th

loca

tions

F-

J

"+"

SP

+ 1

, SP

and

add

2 t

o S

P)

~'~

CA

LL

=I~

m

Cal

l if

test

t t

rue

subr

outin

e ~

zc

z=o~

.,¢~,

z=o~

at

add

ress

m

__

N~

~.~

¢A

~,~

" (P

C o

n st

ack

: (S

P--

1)

te

~ ~¢

A-*I'Z

=°b"

={Z'~

)

(SP

- 2)

~ P

C, S

P '*

- SP

- 2)

2e

cc

f*

>,,

, ~.

,>01

10

JUM

P~

t.m

Ju

mp

if t

true

~*

<~.~

A *>

0~

to lo

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"~

m

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=m

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T~

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etur

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t tr

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s~

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(s =

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11

(Add

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fro

m s

tack

:

7¢

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i~,~

u~ °

PC

~ (

SP

) (S

P +

1)

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P ~

SP

+ 2

) ",,

w, c

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u~

rc--

---3

;1

7 ~

CA

LL=

m

Jum

p to

sub

rout

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(PC

on

stac

k)

10

~ JU

MP

~m

Jum

p ~'1

._.~

~9(I

29

2¢

-

10

RE

T

Ret

urn

from

sub

rout

ine

(Add

resa

fro

m s

tJck

) I

3~

3~

5 1

35

1

t JU

MP

=(H

L)

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p to

loca

tion

addr

esse

d bV

HL

5(I

i i

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79

7(I

J;~

13

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RS

T=I

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64

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94

3 IN

X S

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XB

91

3 D

CX

D

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3 O

CX

SP

1~73

O

AO

B

I)lt

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O

(~31

O

AO

H

(~51

O

AO

SP

@

71

AD

D r

20S

A

DD

M

206

AD

I

AO

C r

2iS

A

OC

M

216

AC

I 31

6 S

UB

r 22

S S

UB

M

226

SU

I 32

6 se

n r

23S

~l

~lB

M

2363

36

AN

A r

24S

AN

A M

24

6 A

NI

346

XR

Ar

25S

SR

AM

2r

~6

XR

I 35

6

OR

Ar

2~

D

RA

M

266

OR

I 36

6

CM

P 27

S

CM

P M

27

6 C

PI

376

CM

A

~57

RLC

~

7

RA

L

027

RR

C

¢17

RA

R

~137

DA

A

g47

CM

C

¢77

STC

~

7

IN

333

OU

T

323

El

373

DI

363

HLT

16

6

NO

P

~e

l

MN

EMO

NIC

S

Incr

emen

t O

f loc

atio

n d

el

B

m

INC

~d

reQ

iste

r (S

. Z.

X,

P c

an c

hecR

e)

te

C

DE

C=d

D

ecre

men

t d

d ~

" E

(S

, Z,

X,

P ca

n ch

ange

) 4e

H

I~"

L IN

C=

p In

crem

ent

pair

p ;

6e

(HL)

(S

, Z,

X.

P, C

do

not

chan

ge)

; 71

1 A

I

[~

D

EC

, p

Dec

rem

ent

pair

p (S

. Z.

X.

P. C

do

not c

hang

e)

8(:

OE

P HL

A

DD

AH

L~o

Add

to

HL

the

pa

irp

SP

(S

. Z,

X.

P

do n

ot c

hang

e)

4 7 ~

AD

D=

A~

r A

dd t

o A

ccum

ulat

or r

egis

ter,

loca

tion

Or n

umb~

=

(S, Z

. X

. P

. C c

on c

hang

e)

AD

DC

. A~

I A

dd w

ith ¢

w'rv

7

i i

(S. Z

, X

, P

. C c

an c

heng

e)

; 8

,,4.

~ 1

c '

4 ~

--~

I

SU

BA

Aa$

S

ubtra

ct

2"

O

4 L.

....

J

(S, Z

, X

. P

. C c

an c

hang

e)

3 E

4 ~

SU

BC

.A,#

S

ubtra

ct w

ith c

arry

$

~ H

7

I -

IL

..

..

J (S

.Z.X

,P,

C c

an c

hang

e)

~ L

AND.A

. And

,H

LI

7 (C

= 0

, S, Z

. P ca

n ch

enge

) 7

A

J 25

0+J

XO

R=

A65

E

xclu

sive

0 R

7

L. ..

..

J (C

= (

~. S

. Z.

p ca

n ch

lmge

) ,m

OR

.A..

OR

I~m

.~".

.)

7 ¢.

....

j

(C =

(D

. S, Z

, p

can

chan

ge)

COM

Ps A

~a

Com

pare

(A -s

) 7

L f

(Z=

I i

f A

=s

,C

= 1

if A

<s

,S.

X.

Pca

n ch

ange

)

4 ~

CP

LAA

C

ompl

emem

th

e ac

c.

4 ~

RL

=A

R

otat

e le

ft a

cc (

with

out

carr

y) (

C m

AT

)

4 [T

~]

RLC

AA

R

otat

e le

ft ac

c. w

ith c

arry

(C

= A

T)

4 ~

RR

=A

R

otet

e rig

ht e

cc.

(with

out

cacr

y) (

C =

AID

)

h 4

[T

~

RR

CA

A

Rot

ate

right

Icc

. w

ith

carr

y (C

= A

I)

4 ~

D/U

IL

Dec

imel

adj

t.~t

i¢¢.

(S, Z

. X

. P

. C c

an c

hang

e)

4 ~

OP

LC

Com

plem

ent

the

cirr

y (C

= (

~)

4 ~

SE

TC

Set

c, e

rry

(C=

1)

10

~ IN

P~R

I n

l:lU

t to

acc.

f fo

re p

ii'iph

ecel

n

10

~'

~

OU

TA

n O

utpu

t tO

per

iphe

sel n

4 ~

ION

In

tcvr

upt

on

4 ~

IOF

In

te'ru

pt o

ff

(71

~ W

AJT

W

ait f

or in

terT

Opt

(ha

lt)

4 ~

NO

P

NO

ope

ratio

n

Can

be

repr

oduc

ed w

ith a

, Jtho

riz~u

on o

f LC

D E

PFL

. Bel

lw~v

e 16.

CH

100

7 Ll~

wnn

e

I o~

I

MINI

SHISS FEDERAL INSTITUTE OF TFO-INOI.O6Y

12 13 14 15 1B 17

3O 31 32 33 34 35 36 37

3B

3A 3B 3C 3D

MICROCOHPb'TF.R LAIk"NRATORY

22 23 24 25 26 27

(LCD EPFL)

¢ " 0 )NOP 1 i IZ l LOAD BC,~m

ILOAD (BCI,A 3 ~ : INC BC

¢ INC B { DEC B n ', LOAD B,~n e IRL A

ADD HL,BC }, LOAD A,(BC) I~ !iDEC BC u iINC C

DEC C LOAD C,,~n

w RR A

p o LOAD DE,~

LOAD (DE),A u INC DE

INC D X. DEC D

i LOAD D,~n = RLC A

,/~ADD HL,DE + ', LOAD A, (DE) ÷ DEC DE + INC E - DEC E £ LOAD E~n

RRC A

iLOAD HL,Om i LOAD m,HL

~ NC HL INC H DEC H

& LOAD H,=~n ' DAA

( ADD HL,HL LOAD HL,m DEC HL INC L DEC L LOAD L,#n CPL A

LOAD SP,#m 2 2 LOAD m,A 3 3 INC SP 4 4 IRC (HL) 5 5 DEC (HL) 6 6 LOAD (HL),~n 7 7 SETC

1 9 ADD HL,SP 2 z LOAD A,m 3 ~ DEC SP 4 < INC A II

DEC A i 5 ; LOAD A,#n

7 ? CPLC ,

~[uemo-nio

INTEL

41 i lOlA LOAD B,C l 42 102 B LOAD B,D 43 103 c LOAD B,E 44 104 D LOAD B,H 45 1p5 E LOAD. B,L 46 47

48 49 4A 4B 4C 4D 4E 4F

50 51

] 0 6 l

Ip7

llO 111 l l2 If3 l l4 I15 If6 I17

120 121 122

!.123 1124

125 126

i t

172 73

174 75 176 177

F LOAD B,(HL) G LOAD B,A

H LOAD C,B I LOAD C,C J LOAD C,D K LOAD C,E L LOAD C,H

LOAD C,L N LOAD C,(HL)I 0 LOAD C,A

P LOAD D,B 0 LOAD D,C R LOAD D,D S LOAD D,E T LOAD D,H U LOAD D,L v LOAD D,(HL) W LOAD D,A

x LOAD E,B Y LOAD E,C Z LOAD E,D [ LOAD E,E \ )LOAD E,H ] LOAD E,L

LOAD E,(HL) LOAD E,A

i LOAD tI,B LOAD H,C LOAD H,D

c LOAD H,E d LOAD H,H e LOAD H,L • f LOAD H,(HL)

LOAD H,A

LOAD L,B LOADL,C LOAD L,D

k LOAD L,E Z LOAD L,H m LOAD L,L n LOAD L,(HL) o LOAD L,A

p LOAD (HL),B' q LOAD (HL),C r LOAD (HL),D

LOAD (HL),E LOAD (HL),H LOAD (HL),L WAIT LOAD (HL),A

LOAD A,B LOAD A,C

z LOAD A,D { LOAD A,E I LOAD A,H } LOAD A,L

LOAD A,(HL) I LOAD A,A

MCM6571 Character ~enerator

- 2 7 -

8 0 8 0 M N E M O - N I C S

e l | ?O1 ~ ADD A,C y ADD

ADD ¢ . ADD

ADD fi ADD o !ADD

'~ i ADOC F: 'iAOO C X )ADDC

ADDC v ADDC

ADDC 216 -~ ADDC 217 W ADDC

220 ~ SUB 221 ~ SUI3 222 -r SUB 223 u SUB 224 ~ SUB 225 ~ SUB 226 ~ SUB 227 ~ SUB

2361 ~ SUBC 231 ~ SUBC 232 " SUBC 233 SUBC 234 ; SUBC 235 t~ SUBC 236 E SUBC 237 ~- SUBC

240 i :AND 241 ~ l AND 242 "~ :AND 243 :~ AND 244 AND 245 ~ AND 246 & AND 247 ' AND

250 ( XOR 251 :): XOR 252 ~r XOR 253 XOR 254 , XOR 255 ~ XOR 256 ~ XOR 257 XOR

260 g. OR z6~ ~I: i OR 262 .~ fOR 263 _3 i OR 264 4 i OR 265 ~)OR 266 ~ OR 267 Z OR

270 ~ COMP 27] .~ COMP 272 -'. i COMP 273 ~ COMP 274[ ~ COMP 275 i - COMP 276j > I COMP 277 ~ COMP

A,D ; A,E ) A,H A,L A,(HL)I A,A

A,B A,C A,D A,E A,H A,L i A,(HL). A,A

A,B A,C A,D A,E A,H ) A,L I A,(HL)I A,A

A,B A,C A,D A,E A,H A,L A,(HL: A,A

A,B A,C A,D A,E A,H A,L A,(HL) A,A

A,B ..A,C A,D A,E A,H A,L A,(HL) A,A



6¢ 61

~ 8

6

Octal

7A 7B

t 17c

7E : F

B2i202 83)203 841204 85:205 86 206 87 207

e8 210 89 211 8A 212 BB 213 ac 214 SO 215 BE

A7 A8 A9

AC AD AE AF

BO B1 B2 R3 B4 BS B6 B7

B9

BC

RE

, , I J)O ( ,

i cl 301 ~ I c2 302 1i i c3 303 d i

l C4 304 Q~ ! c5 305 ~ I

c6 306 P:! C7 307 r.)

C9 311 :Z ) CA 312 J() CB 313 ~ i cc 314 co 315 CE 316 CF 317.

DO 320 D1 321 02 D3

I

i

f

356 ~ 357

36~L ~ 361 362 363 364 EI 365 366 367

370 371

373 ~I 374 375 376 377

H e x a d e c i m a l

RET,NE POP BC JUMP,NE m JUMP m CALL,NE m PUSH BC ADD A,,n RST 0

RET,EQ RET JUMP,EQ m

CALL,EQ m i CALL in

I~ AODC A,,~n U RST 1@

RET,CC POP DE

.~ JUMP,CC m OUT n CALL,CC m

U PUSH DE )~. SUB A,+n k~ RST 20

RET,CS

JUMP,CS m ;INP n

IS CALL,CS m

SUBC A,*n . ! RST 30

i~ m (sP) ,HL

g HL f~ A,4n °: ,, ) RET,PE (HL)

l JUMP,PE m

,t m

XOR A,+-n RST 5¢ RET,PL POP AF JUMP,PL m IOF CALL,PL m PUSH AF OR A,..~n RST 60

RET,MI LOAD ST,HL JUMP,MI m ION CALL,MI m

CONP A,+n RST 7e

e

17.2.75

Fig. 5. Intel 8080 mnemo-nic instruction list.

- 28 -

MINI AND MICROCOMPUTER LABORATORY SWISS FEDERAL INSTITUTE OF TECHNOLOGY OF LAUSANNE (LCD EPFL)

F=q

U)*AdO~ 2 ~DAA~e~ LD~AIX~ ~DAeI=P

~oXl,l 316

STAA~m S~AAIe, ST~X~

S~S~m

TAB

[BA

rAP

FPA

n~

026

021

~ 6

~7

z~

su~.m

~c.m

ORBm

¢.P~m

c*x.,

ABA 033

SBA 020

CBA 021

OAA 031

INX ~10

DEX 011

INS 061

DES 064

CLRA 117 CLR8 137 CLR(E 177 CLR(I: t57

COMA 103

NEGA 1~

DECA 112

INCA t14 I

ROLA I11

nORA 106 I

ASL ne I

" 107 ASR

kSn 104

TST 115

I February t975

MPU Cycles (~' I ~zsfcycle) $

Hexa Octal

~ LOAD~d~s L - - - J L _ - - J L - - - J L _ - - J

[ • ' 7 • ~ LOAID~d~; L - - - J L___ -I L _ _ _ J L - - - J

MOTOROLA MPU 6800B M I C R O P R O C E S S O R I N S T R U C T I O N S R E F E R E N C E C A R D ( M N E M O - N I C S )

........ t ...... . . . . . . . . . . tab or m 16-bit number

Low byte I LSB[ comma)

! Deviations with 6800A

~E~[ ]~ li~

(sz. v = ~, L[4-E [ ] ' x ~ :?,.~: .....

..i,.,0,.~,l L g IGI~ ,×~

withs 16 bits ~ ]-SX (sz, v = 0) ~,*teod,,0~ [[~] [ ] , x

~ . . . . . . [[~]i ~;] sP indexed F~JRA

PSRB

II~ 6 Ill ~'~'~ I ~OAOo.oA Load BwithA {SZ.V =0) ~ LOAO~A~8 Load A with B (S,Z, V = 0)

[ ~ ] ~ LOAD~F~A Load status reg F with A

I ] ' ~ 1 " 0 ~ LOADaAaF Load A with status reg F

~ ~ ADD~d~s Add d with $, result in d (XSZVC . . . . hange ) d ~II ~] [ ] A

s.0 . . . . ( . . , (SZVC) o '

' '1 #ml lX SP) ~ su.:o,,o, sub.~tw.b ..... (SZVC)

ANDodo* And (SZ, V = ~) $ 8 b~is {d,r~t I

{SZ, V = (~) (e~lended)

~ ~ OR~d~s' O, (SZ, V = 0 ) ~ t - ~ [ ] . . . . . . . . , ~ d ~

2 Q~ 5* Bit test (d and s) (SZ. V = 0)

~ ~ COMP~IX~x Compare Index reg wrth S (IX s) (16 bits} (SZVC)

~ ADD~A~B A d d A a n d B ( A ~ A + B ) (XSZVC)

II~ellle~l,u,oA~ su~ ..... A a o d ~ A ~ A - ~ , ~ Z V C ~

~ DAA Decimal adjust ACC A (SZVC)

II ~ e I] I ~ ~ ~ I , .co,x , . . . . . . . . ,o0~:~ reg ~ ,

II e~ I 1 1 ~ ~ I DE~o,x o . . . . . . . index ,eg (Z) '

[I 3~ I I N 6 " 1 'NC~SP I . . . . . . . . . . Stack p . . . . . .

II 3 4 l] l e 6 4 1 o~c . sP o . . . . . . . Stack p . . . . . .

114 F'I] l i i 7"J C, Ro~ C,e.rd(S=e.Z = f . V = e . C = ~ ) L : z z d ~ : : : d

II 4 3"111 i ~ ] ' 1 c , , , , ~omp, . . . . . . . 1 i, ~Tj L~J A L___J L__- J . . . . . . . . . . (SZ.V = @.C = ~) ~]~O~J ~ B

L - - - - - J L - - - - - - J (SZ.C = I i f d = ~ ~ I mar~lule

V = 1 dd = 2~(~} (extendedl 114 A'[I I~ ~ 2"1 o z c ~ ~ . . . . . . . . 'T~ ~ ........ ~ _ _ _ J L-----~

If 4 cfll I l l 4"1 ,NC~# , . . . . . . . . . ~ -_-_-~ E - : Z J (SZ, V = l d d = 177.)

[I 4 9"1] I ~ 1 1"1 RLC.d R . . . . . ,el, with . . . . . . . . . . . . . . . (s~c. v : s + c~ ~ P

I146"11 f i ~ 6 : / R R ¢ ~ , . . . . . . . . g . . . . . h . . . . . t : : : d r_: : : . {szc. v =s + o ~ ~1

I148f l l I ' ! ~'1 ~ o " Arithmeticshdl left [ ~ - ~ - ~ - O ~ - - : ~ ~ - - Z : ~ (SZC. v = S + C)

[I I][ ~~.1 q ~ 4 7* 1 ASR~d Arithmetic shift right L - - _ _ ~ L_----~ (SZC. V = S + C}

(SZ, C = g , V = S + C]

I 114 D ' I I / ' ]'~)+"=J TEST." Test d (load S and Z . . . . d,ng I ~ - - - d t - - - - ~ . . . . . . tod) (sz, c = (~. v = @)

I nt~'rupt : IDF General save on stack. load of interrupt address

065

0e~

~66 ~B7

PU LA PULB

SEC 0t5

:LC 014

~EV 013

~LV 012

BCC 044

3CS 045

~LS 043

~HI 042

~NE 046

BEQ 047

BPL 052

BMI 053

BGT ~56

BGE 054

BLE 057

8LT 055

BVC 05~

Bvs 051

BRA ~4~

BSR 2~5

JMP(EI 176 JMP(I) 156

JSR(EI 275 JSRN) 255

RTS e71

RTI 073

SWI 077

WAI 076

CLI 016

SEI 017

NOP 6'~2

REGISTER O R G A N I Z A T I O N i i , l l X , l , S l z , v , c t I

I I .........

a~,~,haw Jr,v

Top memory asslgnmenI

r-- F - I- . . . . . . ~ F , ~ , ~ 177770 L B ~ AL, B INTERRUPT

k- - { - - -A ....

171777

HIxa Oc~l

~ DEC~SP~IX

~ INCaIX~SP

Load SP with IX and decrement

Load IX with SP and increment

[ ~ [ ' 0 " ~ PUSHed Pushd . . . . . . k ~ - - - / . . . .

[ T 3 " ~ ~ 6 " - ~ POP~d Pupal on stack ~ - - sPd B

[ ~ SETC Set carry bit (C = I) !

[ ] ~ ' ] ] ~ CLRC Clear carry bit (C = ~}

~ SETV Set overflow b,t {V = I)

[ ] ' ~ - [ ] ~ CLRV CI . . . . . . . f low bit (V = 0)

~ ~ JDMPACC~.+." Jump if carry clear (C = 0) (jump if greater or equal *}

~ ~ 'DMP.CS..+n' Jump ff carry set (C = 1)

~ ~ JUMP. LS..+tr Jump if I . . . . . . . . . . * ( C + Z = , )

~ ~ JUMP~HI. +n Jump if higher (C + Z = @)

~ ~ JUMP~NE~.+n' Jump if not equal . . . . (Z = @) JUMP~ZC~ +n' Ilump if zero bil clear)

~ ~ JUMP^EO~ .+n' Jump if equal (Z = 1) . ' ,sa 2 . . . . . . . . . . . . JUMP^ZS ~.+n' (jump if zero bit set) d~pl~emenl ( 176to ~201)

g 2 A ~ 2 ~ JUMP.Pt.,+n, Jump if plus (S = , ) . . . . . . . . . . . . JUMP~SC~.+tr (jump if sign bit clear)

~ ~ JUMP~MI^.+n' Jump if . . . . . (S=11 JUMP~,SS~.+n" (jump if sign bit set)

JUMP~G Ta .+n' Jump if greater • * ~he, COMP or SUE{ ,nslru{ hun (Z + (S + V) = (~) * * 2scomplement

U bliS nun,~rs i 7 b,ts + Sl#,/) ~ ~ JUMP,GE ..+n' Jump ,f greater or abe, CC)MP or SUB ............

equal *" (S + V = (~)

Jumpd, . . . . . . equal**(Z + (S + V) = 1)

~ ~ JUMP~ LTr '+n' Jump d I ze fo " (S + V = . . . . . hart ')

~ JUMP.VC .+n ' Jcr,:r p(,v f o:e(~;Iow

,UMP vs .umpdoorfow set (V = I)

I ~ ~ JUJPn.+n' Jurnp relative (displa(enlerll n bytes)

~ ~ CALLA.,n' C b r o u t i n e ( p c . . . . . on sta{k)

/ . (e.t eacled)

~ ~ CALLt,/ Call subroutine i ~ [ ] ...... (PC on stack) ,ndexed

~ nET Return from subroutine (PC from stack)

~ RTI Return from interrupl (F, 8, A. IX. PC from stack)

[ [ ~ ~ TRAP Sol . . . . . . . . . . . . pt (trap, (PC, I X. A, B, F on sti~ck, l = l )

I ] '~ E ~ ~ WAIT Walt for i . . . . . . pt (halt) (no DMA, registers already on stack)

~ - ] ] ~ ION I . . . . . . pt ON (I = 0)

~ NOP No operation

Can be reproduced with authonzat,on of LCO EPF L, Bellerive I6. CH 1007 Lau~nne

Fig. 6. Motorola 6800 mnemo-nic reference card.

MINI AND MICROCOMPUTER LABORATORY

SWISS FEDERAL INSTITUTE OF TECHNOLOGY

0 I 2 3 4 5 6 7

I0 11 12 13 14 15 16 17

20 21 22 23 24 25 26 27

30 31 32 33 34 35 36 37

4O 41 42 43 44 45 46 47

50 51 52 53 54 55 56 57

60 61 62 63 64 65 66 67

70 71 72 73 74 75 76 77

Oc ta l

(LCD EPFI.)

B y NOP

£

n LOAD F,A e LOAD A,F

I INC IX K DEC IX

CLRV p SETV v CLRX

SETC 0 IOF

ION

p SUB A,B o COMP A,B T

U

¢ X

LOAD B,A w LOAD A,B

~ AA

÷ ADD A,B

÷

JUMP .+n'

" JUMP,HI .+n' JUMP,LS .+n'

$ JUMP,CC .+n % JUMP,CS .+n

JUMP,NE .+n JUMP,EQ .+n

JUMP,VC .+n JUMP,VS .+n JUMP,PL .+n JUMP,MI .+n JUMP,GE .+n JUMP,LZ .+n JUMP,GT .+n JUMP,LE .÷n'

INC IX,SP INC SP POP A POP B DEC SP DEC SP,IX PUSH A PUSH B

RET

RTI

WAIT TRAP

~nemo-nlc

IO ;1 12 t3 14 ~5 ~,6 ~7

18 ~.9 ~A IB

~D ~E ~F

50 51 52 53 54 55 56 57

58 59 5A 5B 5C 5D 5E 5F

GO 61 62 63 64 65 66 67

68 69 6A 65 6C 6D 6E ,SF

70 71 72 73 74 75 76 77

78 79 7A 76 7C 70 7E 7F

EG A

PL A SR A

RC A .SR A

,SL A :LC A ~EC A

NC A EST A

:LR A

IEG B

',PL B .SR B

~RC B ~SR B

kSL B {LC B )EC B

[NC B FEST B

"LR B

~EG (IX)+n

:PL (IX)+n .SR (IX)+n

~RC (IX)+n ~SR (IX)+n

%SL (IX)+n ~LC (IX)+n )EC (IX)+n

[NC (IX)+n rEST (IX)+n

;LR (IX)+n

IEG m

tPL m LSR m

RRC m ASR m

~SL m RLC m DEC m

INC m TEST m

CLR m

MCM 6571 Character generator

- 2 9 -

MOTOROLA 6800 r, INEMO-N I CS

~O I 200 ~i I 201 ~2 1 202 63 I 203 ~4 t 204 65 I 205 66 I 206 ~7 I 207

B8 1 210 691211 BA I 212 8B I 213 Bc I 214 BD 1 215 BE I 216 8F 1 217

901220 91 t221 921222 931223 941224 951225 951226 971227

981230 99 J 231 9A I 232 98 1 233 9c I 234 9D1235 9E1236 9F1237

A01240 A I1241 AZl 242 A3! 243 A4! 244 A51245 A6 246 A7 247

A8 250 A9 251 AA 252 AB 253 AC 254 AD 255 AE 256 AF 257

BO 26C 61 261 B2 262 63 263 64 264 65 265 86 266 B7 26;

68 27C 69 271 BA 27~ BB 273 BC 274 BD 275 BE 27E BF 27)

SUB A,~n COMP A,+n SUBC A,-~n

AND A,#n BIT A,.in LOAD A,~.n

XOR AJn ADDC A,~-n OR A,~n ADD A,~n COMP IX,Im CALL .+n' LOAD SP,Im

SUB A,n COMP A,n SUBC A,n

AND A,n BIT A,n LOAD A,n LOAD n,A

XOR A,n ADDC A,n OR A,n ADD A,n COMP IX,n

LOAD SP,n LOAD n,SP

SUB A,(IX)+n COMP A,(IX)+n SUBC A,(IX)+n

AND A,(IX)+n BIT A,(IX)+n LOAD A,(IX)+n LOAD (IX)+n,A

XOR A,(IX)+n ADDC A,(IX)+n OR A,(IX)+n ADD A,(IX)+n COMP IX,(IX)+n

LOAD SP,(IX)+n LOAD (IX)+n,SP

SUB A,m COMP A,m SUBC A,m

AND A,m BIT A,m LOAD A,m LOAD m,A

XOR A,m ADDC A,m OR A,m ADD A,m COMP IX,m

LOAD SP,m LOAD m,SO

CO CI c2 c3 c4 c5 c6 c7

ca c9 CA CB CC CO CE CF

DO DS D2 D3 D4 D5 D6 D7

D8 D9 DA DB OC DD DE DF

EO El E2 E3 E4 E5 E6 E7

E8 E9 EA EB EC ED EE EF

FO F1 F2 F3 F4 F5 F6 F7

F8 F9 FA FB FC FD FE FF

t Hexadecimal

SUB B,,#n COMP B,~n SUBC B,|n

AND B,~n BIT B,~n LOAD B,,n

XOR B,~n ADDC B,~n OR B ,~ n ADD B,~n

LOAD IXdm

SUB B,n COMP B,n SUBC B,n

AND B,n BIT B,n LOAD B,n LOAD n,B

XOR B,n ADDC B,n OR B,n ADD B,n

LOAD IX,n LOAD n,IX

SUB B,(IX)+n COMP B,(IX)+n SUBC B,(IX)+n

AND B,(IX)+n BIT B,(IX)+n LOAD B,(IX)+n LOAD (IX)+n,B

XOR B,(IX)+n ADDC B,(IX)+n OR B,(]X)+n ADD B,(IX)+n

LOAD IX,(IX)+n LOAD (IX)+n,IX

SUB B,m COMP B,m SUBC B,m

AND B,m BIT B,m LOAD B,m LOAD m,B

XOR B,m ADDC B,m OR B,m ADD B,m

LOAD IX,m LOAD m,IX

1 7 . 2 . 7 5

Fig. 7. Motorola 68oo mnemo-nic instruction list.

Documents

Common instruction mnemonics for microprocessors