Computer Architecture: IntroAnatomy of a CPU

J. Schmalzel

S. Mandayam

Hierarchical View of EP and Digital Systems

CPU MEM

I/O

GatesBoolean Algebra

Design Techniques

MSI Functions

State Machines

Interface Method

Computer Architecture

Operating System

HLLs

BlockDiagram

Concept of CPU as Two Paths

Data Path Where data elements flow from/to Where operations are performed

Control Path The source of data path control

Simple Model Data Path (7-18)

Dbus

n-bit bus

Signal

Dbus

DoutAout

FS

Status

DA

AA

RW

Const

MB

MD

Register

File

Function

Unit

MuxB

MuxD

Din

BA

Instruction Word

DA AA BA MB FS MD RW

3 3 3 1 1 15

Iword, cont.

RW to write back result

AA, BA, DA: 3-bit selection field to select 1-of-8 registers

MB to select source operand for B path

FS to select operation

MD to select source for register file load

RF

FU

Function Select Codes00000 F=A00001 F=A+100010 F=A+B00011 F=A+B+100100 F=A+ ~B00101 F= A+ ~B + 100110 F=A-100111 F=A01000 F=A & B01010 F=A | B01100 F=AB01110 F= ~A10000 F=B10100 F= sr B11000 F= sl B

FU (ALU) Design Approaches

Complex combinatorial structureMultiplexed discrete logical and arithmetic

unitsHDL model

Consider Implementation

Use organization of FS codes to partition system (use FS4 and FS3): 00- Arithmetic 01- Logical 10, 11- Shift, Miscellaneous

Questions, Comments, Discussion