Computer Organization-Basic Processing Unit

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Text of Computer Organization-Basic Processing Unit

  • Basic Processing Unit

  • Overview Instruction Set Processor (ISP) Central Processing Unit (CPU) A typical computing task consists of a series

    of steps specified by a sequence of machine of steps specified by a sequence of machine instructions that constitute a program.

    An instruction is executed by carrying out a sequence of more rudimentary operations.

  • Some Fundamental Concepts

  • Fundamental Concepts Processor fetches one instruction at a time and

    perform the operation specified. Instructions are fetched from successive memory

    locations until a branch or a jump instruction is encountered.

    Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).

    Instruction Register (IR)

  • Executing an Instruction Fetch the contents of the memory location pointed

    to by the PC. The contents of this location are loaded into the IR (fetch phase).

    IR [[PC]] Assuming that the memory is byte addressable,

    increment the contents of the PC by 4 (fetch phase).PC [PC] + 4

    Carry out the actions specified by the instruction in the IR (execution phase).

  • Processor Organization

    linesData

    Addresslines

    busMemory

    PC

    MAR

    MDR

    bus

    IR

    Control signals

    Instructiondecoder and

    Internal processor

    control logic

    MDR HAS TWO INPUTS

    AND TWO OUTPUTS

    Carry-in

    ALU

    Y

    Z

    Add

    XOR

    Sub

    TEMP

    R0

    controlALU

    lines

    R n 1-( )A B

    MUXSelect

    Constant 4

    Datapath

    Fig 1 Single-bus organization of the datapath inside a processor

  • Executing an Instruction Transfer a word of data from one processor

    register to another or to the ALU. Perform an arithmetic or a logic operation

    and store the result in a processor register.and store the result in a processor register. Fetch the contents of a given memory

    location and load them into a processor register.

    Store a word of data from a processor register into a given memory location.

  • Register Transfers

    Y in

    Y

    R i in

    R i

    R i out

    b usInternal processor

    Constant 4

    BA

    Z

    ALU

    Z in

    Z out

    Constant 4

    MUX

    Fig 2 Input and output gating for the registers shown in Fig1.

    Select

  • All operations and data transfers are controlled by the processor clock.Bus

    Register Transfers

    Figure 7.3. Input and output gating for one register bit.

    D Q

    Q

    Clock

    1

    0

    Riout

    Ri in

    Fig 3. Input and output gating for one register bit.

  • Performing an Arithmetic or Logic Operation The ALU is a combinational circuit that has no

    internal storage. ALU gets the two operands from MUX and bus.

    The result is temporarily stored in register Z. What is the sequence of operations to add the

    contents of register R1 to those of R2 and store the result in R3?

    1. R1out, Yin2. R2out, SelectY, Add, Zin3. Zout, R3in

  • Fetching a Word from Memory Address into MAR; issue Read operation; data into MDR.

    Memory-busdata lines

    Internal processorbusMDRoutMDRoutE

    MDR

    Figure 7.4. Connection and control signals for register MDR.

    MDRinMDRinE

    Fig 4 Connection and control signals for register MDR.

  • Fetching a Word from Memory The response time of each memory access varies

    (cache miss, memory-mapped I/O,). To accommodate this, the processor waits until it

    receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC).MFC).

    Move (R1), R2 MAR [R1] Start a Read operation on the memory bus Wait for the MFC response from the memory Load MDR from the memory bus R2 [MDR]

  • Timing1 2

    Clock

    Address

    Read

    Step 3

    MARinAssume MARis always availableon the address linesof the memory bus.

    MAR [R1]

    Start a Read operation on the memory bus

    Figure 7.5. Timing of a memory Read operation.

    MR

    Data

    MFC

    MDRinE

    MDRout

    R2 [MDR]

    Wait for the MFC response from the memory

    Load MDR from the memory bus

    Fig 5 Timing of a Memory Read operation

  • Execution of a Complete Instruction Add (R3), R1 Fetch the instruction Fetch the first operand (the contents of the

    memory location pointed to by R3)memory location pointed to by R3) Perform the addition Load the result into R1

  • Y in

    Y

    R i in

    R i

    R i out

    b usInternal processor

    Constant 4

    Architecture

    BA

    Z

    ALU

    Z in

    Z out

    Constant 4

    MUX

    Fig 2 Input and output gating for the registers in Figure1.

    Select

  • Execution of a Complete Instruction

    linesData

    Addresslines

    busMemory

    PC

    MAR

    MDR

    Y

    bus

    IR

    Control signals

    Instructiondecoder and

    Internal processor

    control logicAdd (R3), R1

    Step Action

    1 PCout , MARin , Read,Select4,Add, Zin2 Zout , PCin , Yin , WMFC

    Carry-in

    ALU

    Y

    Z

    Add

    XOR

    Sub

    TEMP

    R0

    controlALU

    lines

    R n 1-( )A B

    MUXSelect

    Constant 4

    Fig 6 Control Sequencer execution of the instruction Add (R3),R1.

    Fig 1 Single-bus organization of the datapath inside a processor

    3 MDRout , IRin4 R3out , MARin , Read5 R1out , Yin , WMFC6 MDRout , SelectY,Add, Zin7 Zout , R1in , End

  • Execution of Branch Instructions A branch instruction replaces the contents of

    PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.in the branch instruction.

    The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.

    Conditional branch

  • Execution of Branch Instructions

    Step Action

    1 PCout , MAR in , Read, Select4,Add, Z in2 Zout, PCin , Yin, WMF C3 MDRout , IR in4 Offset-field-of-IRout, Add, Z in5 Zout, PCin , End

    Fig 7. Control sequence for an unconditional branch instruction.

  • Multiple-Bus OrganizationBus A Bus B Bus C

    PC

    Re gisterfile

    Constant 4

    ALU

    A

    B

    R

    M

    U

    X

    Incrementer

    Register file

    Memory b usdata lines

    Figure 7.8. Three-b us or g anization of the datapath.

    Instructiondecoder

    MDR

    B

    Addresslines

    MAR

    IR

    Fig 8 Three-bus organization of the datapath

    Memory bus datalines

  • Multiple-Bus Organization Add R4, R5, R6

    Step Action

    1 PC , R=B, MAR , Read, IncPC1 PCout, R=B, MAR in , Read, IncPC2 WMFC3 MDRoutB, R=B, IR in4 R4outA, R5outB, SelectA, Add, R6in , End

    Fig 9. Control sequence for the instruction Add R4,R5,R6,for the three-bus organization in Fig 8.

  • Quiz What is the control

    sequence for execution of the instruction

    linesData

    Addresslines

    busMemory

    PC

    MAR

    MDR

    Y

    bus

    IR

    Control signals

    Instructiondecoder and

    Internal processor

    control logic

    Add R1, R2including the instruction fetch phase? (Assume single bus architecture)

    Carry-in

    ALU

    Y

    Z

    Add

    XOR

    Sub

    TEMP

    R0

    controlALU

    lines

    R n 1-( )A B

    MUXSelect

    Constant 4

    Fig 1 Single-bus organization of the datapath inside a processor

  • Hardwired Control

  • Overview To execute instructions, the processor must

    have some means of generating the control signals needed in the proper sequence.

    Two categories: hardwired control and Two categories: hardwired control and microprogrammed control

    Hardwired system can operate at high speed; but with little flexibility.

  • Control Unit OrganizationCLKClock Control step

    Decoder/

    counter

    inputsExternal

    Figure 7.10. Control unit organization.

    IRencoderDecoder/

    Control signals

    codesCondition

  • Detailed Block DescriptionResetCLKClock

    counter

    Step decoder

    Control step

    T1 T2 Tn

    Externalinputs

    Figure 7.11. Separation of the decoding and encoding functions.

    Encoder

    Control signals

    Run End

    Conditioncodes

    decoderInstruction

    IR

    INS1INS2

    INSm

  • Generating Zin Zin = T1 + T6 ADD + T4 BR +

    AddBranch

    T4 T6

    Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.

    T1

  • Generating End End = T7 ADD + T5 BR + (T5 N + T4 N) BRN +

    T7

    Add BranchBranch

  • A Complete ProcessorInstruction

    unitInteger

    unitFloating-point

    unit

    Instructioncache

    Datacache

    Bus interface

    Mainmemory

    Input/Output

    System bus

    Processor

    Figure 7.14. Block diagram of a complete processor.

  • Microprogrammed Control

  • Overview Control signals are generated by a program similar to machine

    language programs. Control Word (CW); microroutine; microinstruction

    P

    C

    i

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    P

    C

    o

    u

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    R

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    n

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    D

    R

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    n

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    i

    n

    S

    e

    l

    e

    c

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    d

    Z

    i

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    Z

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    R

    1

    o

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    i

    n

    R

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    u

    t

    W

    M

    F

    C

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    n

    dMicro -instruction

    P

    C

    P

    C

    M

    A

    R

    R

    e

    a

    d

    M

    D

    R

    I

    R

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    c

    t

    A

    d

    d

    Z R

    1

    R

    1

    R

    3

    W

    M

    F

    C

    0100000

    0000001

    1000000

    1001000

    1001000

    0010010

    0010000

    0100100

    1000000

    1000010

    1000010

    0100001

    0000100

    0000001

    0001000

    0100100

    1234567

    Figure 7.15 An example of microinstructions for Figure 7.6.

  • Overview

    Step Action

    1 PCout , MAR in , Read, Select4,Add, Zin2 Zout , PCin , Yin , WMF C3 MDR out , IR in3 MDR out , IR in4 R3out , MAR in , Read5 R1out , Yin , WMF C6 MDR out , SelectY, Add, Zin7 Zout , R1in , End

    Figure 7.6. Control sequencefor execution of the instruction Add (R3),R1.

  • Overview Control store

    generator

    StartingaddressIR One function

    cannot be carriedout by this simpleorganization.

    Figure 7.16. Basic organization of a microprogrammed control unit.

    storeControl CW

    Clock PC

    organization.

  • Overview The previous organization cannot handle the situation when the control

    unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action.

    Use conditional branch microinstruction.

    AddressMicroinstruction

    0 PCout , MAR in , Read,Select4,Add, Zin1 Zout , PCin , Yin , WMFC2 MDRout , IRin3 Branch to startingaddressof appropriatemicroroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    25 If N=0, then branch to microinstruction026 Offset-field-of-IRout , SelectY, Add, Zin27 Zout , PCin , End

    Figure 7.17. Microroutine for the instruction Branch

  • Overview

    generator

    Starting andbranch address Conditioncodes

    inputsExternal

    IR

    Figure 7.18. Organization of the control unit to allowconditional branching in the microprogram.

    Controlstore

    Clock

    CW

    PC

  • Microinstructions A straightforward way to structure

    microinstructions is to assign one bit position to each control signal.

    However, this is very inefficient. However, this is very inefficient. The length can be reduced: most signals are

    not needed simultaneously, and many signals are mutually exclusive.

    All mutually exclusive signals are placed in the same group in binary coding.

  • Partial Format for the Microinstructions

    F2 (3 bits)000: No transfer001: PCin010: IRin011: Zin100: R0in101: R1in

    F1 F2 F3 F4 F5

    F1 (4 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)0000: No transfer0001: PCout0010: MDRout0011: Zout0100: R0out0101: R1out

    000: No transfer001: MARin010: MDRin011: TEMPin100: Yin

    0000: Add0001: Sub

    1111: XOR

    00: No action01: Read10: Write

    Microinstruction

    101: R1in110: R2in111: R3in

    0101: R1out0110: R2out0111: R3out1010: TEMPout1011: Offsetout

    16 ALUfunctions

    F6 F7 F8

    F6 (1 bit) F7 (1 bit) F8 (1 bit)0: SelectY1: Select4

    0: No action1: WMFC

    0: Continue1: End

    Figure 7.19. An example of a partial format for field-encoded microinstructions.

    What is the price paid for this scheme?

  • Further Improvement Enumerate the patterns of required signals in

    all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code.signals can then be assigned a distinct code.

    Vertical organization(No encoding of control signals in control memory)

    Horizontal organization(Reducing control fields in memory storage by use of MUXs in the output word form control memory)

  • Microprogram Sequencing If all microprograms require only straightforward

    sequential execution of microinstructions except for branches, letting a PC governs the sequencing would be efficient.

    However, two disadvantages: However, two disadvantages: Having a separate microroutine for each machine instruction results

    in a large total number of microinstructions and a large control store. Longer execution time because it takes more time to carry out the

    required branches. Example: Add src, Rdst Four addressing modes: register, autoincrement,

    autodecrement, and indexed (with indirect forms).

  • - Bit-ORing- Wide-Branch Addressing- WMFC

  • OP code 0 1 0 Rsrc Rdst

    Mode

    Contents of IR

    034781011

    Address Microinstruction(octal)

    000 PCout, MARin, Read, Select4, Add, Zin001 Zout, PCin, Yin, WMFC002 MDRout, IRin003 Branch {PC 101 (from Instruction decoder);

    PC [IR ]; PC [IR10] [IR9] [IR8]}

    Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.Note:Microinstruction at location 170 is not executed for this addressing mode.

    PC5,4 [IR10,9]; PC3 121 Rsrcout, MARin, Read, Select4, Add, Zin122 Zout, Rsrcin123170 MDRout, MARin, Read, WMFC171 MDRout, Yin172 Rdstout, SelectY, Add, Zin173 Zout, Rdstin, End

    [IR10] [IR9] [IR8]}

    Branch {PC 170;PC0 [IR8]}, WMFC

  • Microinstructions with Next-Address Field The microprogram we discussed requires several

    branch microinstructions, which perform no useful operation in the datapath.

    A powerful alternative approach is to include an address field as a part of every microinstruction to indicate the location of the next microinstruction to indicate the location of the next microinstruction to be fetched.

    Pros: separate branch microinstructions are virtually eliminated; few limitations in assigning addresses to microinstructions.

    Cons: additional bits for the address field (around 1/6)

  • Microinstructions with Next-Address Field

    Conditioncodes

    IR

    Decoding circuits

    InputsExternal

    Figure 7.22. Microinstruction-sequencing organization.

    Control store

    Next address

    Microinstruction decoder

    Control signals

    AR

    I R

  • F1 (3 bits)

    000: No transfer001: PCout010: MDRout011: Zout100: Rsrcout101: Rdstout110: TEMPout

    F0 F1 F2 F3

    F0 (8 bits) F2 (3 bits) F3 (3 bits)

    000: No transfer001: PCin010: IRin011: Zin100: Rsrcin

    000: No transfer001: MARin

    F4 F5 F6 F7

    Microinstruction

    Address of nextmicroinstruction

    101: Rdstin

    010: MDRin011: TEMPin100: Yin

    F5 (2 bits)F4 (4 bits) F6 (1 bit)0000: Add0001: Sub

    0: SelectY1: Select4

    00: No action01: Read

    1111: XOR10: Write

    F8 F9 F10

    F8 (1 bit)

    F7 (1 bit)

    F9 (1 bit) F10 (1 bit)

    0: No action1: WMFC

    0: No action1: ORindsrc

    0: No action1: ORmode

    0: NextAdrs1: InstDec

    Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

  • Implementation of the Microroutine

    F9

    0

    00

    0

    F10

    0

    00

    00

    00

    0

    F8F7F6F5F4

    000 0 0 0 0 0

    1

    0

    0

    0

    10000

    00001100000

    100

    0

    0

    01

    0 0

    00

    00 01

    110

    10010

    F2

    1

    110 0 0 0 0 0

    1

    12

    0

    21

    000

    addressOctal

    111 00000

    1 000000010000000

    F0 F1

    0

    0 0 10 0

    001

    110100

    0

    10

    1

    F3

    011000 0 0 0 0 00 00 00000 0 0 0 0 030 0 00 0 0

    (See Figure 7.23 for encoded signals.)Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

    1

    01

    111100111110

    001

    001

    121 0

    000

    000

    00

    00

    00

    00

    00 0

    0000

    0 00101

    11037

    700000000

    0 1111110

    000

    1707 0

    0

    00

    00

    00

    00

    0

    0

    0

    00

    0

    100

    0

    00

    0

    00

    0

    00

    0 1

    1

    0

    00 0

    10 10000 0

    0

    00 0

    0

    00000

    000

    001110

    11

    221

    011110

    111 00121 111 00000

    010010

    0 11001

    0

    0

    1

    1

    next-microinstruction address field.

  • Decoder

    Decoder

    circuitsDecoding

    Condition

    External

    codes

    inputs

    Rsrc RdstIR

    InstDecout

    ORmodeORindsrc

    R15in R15out R0in R0out

    decoderMicroinstruction

    Control store

    Next address F1 F2

    Other control signals

    F10F9F8

    Rdstout

    Rdstin

    Rsrcout

    Rsrcin

    AR

    Figure 7.25. Some details of the control-signal-generating circuitry.

  • bit-ORing

  • Micro-Programmed Control

    Emulation A micro-program determines the machine

    instructions of a computer Suppose we have two computers M1 and M2 with

    different instruction sets

    47

    different instruction sets

    By adapting the micro-program of M1, we can emulate M2

  • Micro-Programmed Control

    Organization Micro-program is often placed in ROM on CPU chip Some machines had writable control store, i.e. user

    could change instruction set

    48