Computer Organization: Basic Processor Structure · Computer Organization: Basic Processor Structure James Gil de Lamadrid April 17, 2018 Computer Organization: Basic Processor Structure

Computer Organization: Basic ProcessorStructure

James Gil de Lamadrid

April 17, 2018

Computer Organization: Basic Processor Structure

Chapter 1: Overview

I Computer Science students start by learning a high-levellanguage. We study what is below the high-level code theywrite.

I We break our study into two areas:I Computer Organization - the study of the implementation of

the computer.I Computer Architecture - the study of he interface to the

computer.


High-Level Laguages

I Programming languages are classified by level.

I Low level languages are closer to the hardware.

I High level languages manipulate more abstract datastructures.

Examples

I Haskell - a functional language.I C++ - an object-oriented language.


Machine Language

I Machine language is numeric.

I A machine instruction is a collection of fields, or numbers therepresent the information given in the instruction.

I Instruction format: op-code, destination, source, constant

I Machine instructions operate on registers


Machine Language (cont.)

Examples

Source code:x = 5 + y * 3;

Machine code:1, 1, 2, 3

14, 1, 1, 5

Meaning: (Registers R1, and R2 are used to represent the variablesx , and y , respectively.)

R1 = R2 * 3

R1 = R1 + 5


Assembly Language

I Assembly language is a symbol version of machine language.

I Numbers forming parts of the machine instruction, are givensymbolic names.

I The programmer is relieved of remembering the meanings ofnumbers.

Examples

Assembly code:mult R1, R2, #3

add R1, R1, #5


Compilers & Assembly Language

I High-level source code must be translated into machine code,to able to execute on hardware.

I Translation is done in several stages. In the first stage. Sourcecode is often translated into Assembly code.

I The translation Process

1. Parse - the source code is translated into an abstractrepresentation, often an abstract syntax tree (AST).

2. Generate Code - the AST is traversed, and as it is, code foreach node assembly code for each node is written.


Compilers & Assembly Language (cont.)

Examples

Example AST

=

x +

5 *

y3


Assemblers & Object Code

I The assembler translates assembly code to object code

I Object code is incomplete machine code.

I The assembler has trouble completing the machine codebecause of external references.

I A module containing a reference to a definition from anothermodule has an external reference.


External References

Module Q contains:extern int x;

x = 5;

Module Driver contains:int x;

In assembly language, this would be

I Q:store x, #5

I Driver (Allocate a word in memory for the variable x .):x: .word


External References (cont.)

I Translating the store into machine language might yield thefollowing (We assume the op-code for store is 19, and x hasbeen allocated memory location 50.):

19, 50, 5

I But, the assembler only analyses one module at a time, andand cannot determine what memory location has beenallocated to x .

I Instead the assembler produces the following object codeinstruction, with a blank left for the address of x , when it iseventually calculated.

19, x?, 5


Compiler vrs. Assembler

I The compiler parsing activity is complex.

I The code generation is complex, often producing severalassembly instructions for each high-level statement.

I Assembler translation is little more than looking up symbols ina symbol table.

I The numeric field values are assembled into a full instruction.


The Linker & Executable Code

I The input to the linker is a set of object code files.

I The output is a single executable code file.I Linker tasks:

I Resolve external references.I Library search.I Relocation of object code modules.


The Linker & Executable Code (cont.)

I Resolving External references:The linker sees both the module Q, and Driver. It cancalculate the address of x in Driver, and fill in the blank in theQ module.

I Library searches:The linker pulls in modules from the library, and adds them tothe executable code, in order to resolve some externalreferences.

I Relocation:Modules are assigned an order in memory. The addresses inthe module must be adjusted to reflect the modules position.


Library Search Example

Examples

(A0 is the argument register, used to pass an argument to afunction, and RV is the return value register, used to pass a valueback from a function.)

Source code:z = sqrt(y);

Assembly code:load A0, y

call sqrt

store z, RV


Relocation Example

I Module Driver has addresses 0 - 2,999.

I Module Q has addresses 0 - 1,999.

I Module q is placed after Mudule Driver. The base address ofmodule Q is now 3,000.

I All addresses from Module Q must be modified by adding3,000 to them.


The Loader

I The loader:I Relocates the executable code.I Initializes registers.

I The loader loads an executable program into its own sectionof memory called its workspace.

I Several programs (processes) can be active simultaneously.

I The processor executes small pieces of each process (calledquanta) in rapid succession, making it appear that allprocesses in memory are running simultaneously.

I Depending on the location of the program workspace,addresses in the executable code will need to be altered yetagain.

I Several registers, with special uses must be initialized beforethe program is started.


Initializing the PC Register

The Program Counter (PC) is a register that contains the memoryaddress of the next instruction to be executed. It must be updatedeach time an instruction is executed. Initially, it must be set topoint to the base address of the program workspace.

PC2350

2000workspace

Current Instruction2349

Memory


Translation Summary


The Processor

I Levels of abstraction for HardwareI The register transfer level (RTL), or behavioral level.I The gate level, or structural level.

I Processor BehaviorThe processor repeatedly executes the machine cycle, thatreads a single instruction from memory, and executes it.

I Steps in the machine cycle.

1. Fetch an instruction from memory.2. Decode the instruction. (Split the instruction into fields.)3. Execute the instruction.


Processor Structure

I The processor contains registers for storage. Collectively theyare referred to as the register file.

I An arithmetic logic unit (ALU) performs operation of datastored in registers.

I The way the devices in the processor are connected is calledthe data-path.

I The circuit that controls the data-path, and all devices is thecontrol unit.


The Data-Path

Examples (Simple 2-register data-path.)

R1 R1 + R2R2 0

Corresponding circuit:

R1

R2

+

0

Operations performed:

1. Add the contents of R1, and R2, and put the result in registerR1.

2. Set register R2 to zero.

Input the registers is calculated by circuitry called a computationalunit.


Control Circuitry

Examples (Simple 2-input control.)

S1 : R1 R1 + R2S2 : R2 0

Corresponding circuit:

R1

R2

+

0

S1

S2

LD

LD

Registers are opened for input when the load (LD) line is triggeredby the control inputs.These descriptions are register transfer level (RTL). RTL shows acollection of connected devices.


Digital Circuitry

I Below the RTL level is the digital circuit level, or gate level.

I Gate level circuits are composed of gates.

I Digital circuits represent Boolean values as voltages (maybe0V for false, and 5V for true).

I Gates compute Boolean functions, from input signals.

Examples (AND gate: computes z = a b.)

ab z


Combining Gates into Larger Functions

Examples (Circuit that computes z = a b c)

a

b

c z

(Uses an OR gate, a NOT gate, or inverter.)


Chapter 2: Number, and Logic Systems

Topics covered:

I Computer systems use the base two (binary) number system.

I This system is cumbersome for people. A system that is lessfor people, but still easily translatable to binary is hexadecimal.

I The circuitry in computer systems is based on Booleanalgebra.


Numbers

I Binary has two digits: 0, and 1.

I A binary digit is called a bit.

I Numbers are stored in a collection of bits, of fixed width. Thecollection of bits is called a processor word. A 13 in a 4-bitword would be 1101. In an 8-bit word, it would be 00001101.

I Decimal expansion:365 = 3 102 + 6 101 + 5 100.

I Digits: The leftmost digit is referred to as the high-orderdigit, and the rightmost digit is the low-order digit.

I Decimal is base 10 (the radix in the expansion is ten), and hasten digits: 0 through 9.


Binary Numbers

I Binary expansion:00110101 = 0 27 + 0 26 + 1 25 + 1 24 + 0 23

+1 22 + 0 21 + 1 20 = 25 + 24 + 22 + 20

I Converting from binary to decimal: simple do the calculationsin the binary expansion in decimal.

00110101 = 25 + 24 + 22 + 20 = 32 + 16 + 4 + 1 = 53


Binary Numbers (cont.)

Converting from decimal to binary.

Examples (Converting 365 to binary using successive division.)Calculation Quotient Remainder

365 2 182 1182 2 91 091 2 45 145 2 22 122 2 11 011 2 5 15 2 2 12 2 1 01 2 0 1


Understanding Successive Division

Successive division in decimal:

ExamplesCalculation Quotient Remainder

365 10 36 536 10 3 63 10 0 3I Each division pulls off one digit of the number.I Low-order digits are extracted first.I Division by 10 extracts decimal digits. Division by 2 extracts

bits.I To form a binary number outof the results of successive

division, list the remainders from last extracted to firstextracted, left to right. For the example that would be 365 =101101101.


Hexadecimal Numbers

I Hexadecimal is base 16, with 16 digits: 0, 1, 2, 3, 4, 5, 6, 7,8, , A, B, C, D, E, F. (A - F represent the digits 10 - 15.)

I To convert from hexadecimal to decimal, use the hexexpansion.

A3F = 10162 +3161 +1520 = 2, 560+48+15 = 2, 623


Hexadecimal, & Binary

I Converting hex from/into binary. A single hex digit is fourbinary digits.

I To convert from hex to binary, replace each hex digit with itscorresponding 4-bit representation.

I To convert from binary to hexadecimal, replace each group offour bits by the corresponding hex digit.

Examples

A3F = 1010 0011 11110010111010001011 = 0010 1110 1000 1011 = 2E 8B


Adding Binary Numbers

Examples (Decimal addition)0 10

13

06

05

+11922557

I You add column by column.

I In each column, you add two operand digits, and a carry-indigit.

I Each addition results in a sum digit, and a carry-out digit.


Adding Binary Numbers (cont.)

Examples (Binary addition)0 01

10

11

01

+00111110

I Carry-in to the low-order column is 0.

I A carry-out of 1 occurs when the column sum is greater thanor equal to 2.

I When a carry-out occurs, the sum digit is the sum minus 2.


Representing Negative Numbers

I Computers support two numbering systems:I Unsigned integers - all bit configurations of teh word are used

to represent non-negative integers.I Signed integers - half of the processor word bit configurations

are used to represent negative integers, and half are used torepresent non-negative integers.

I For signed integers, the top bit is the sign bit.I A 0 bit indicates a non-negative number.I A 1 bit indicates a negative number.


Signed Notations

Notation 107 -107

Sign-magnitude 0 1101011 1 1101011Ones Compliment 0 1101011 1 0010100Twos Compliment 0 1101011 1 0010101

Notations:

I Sign-magnitude - formed by writing the magnitude in binary,and tacking on the correct sign bit.

I Ones compliment - formed by inverting every bit in thenumber.

I Twos compliment - formed by adding 1 to the onescompliment.


Signed Notations (cont.)

I Problem: sign-magnitude has two values of 0:I +0: 00000000I -0: 10000000

I Problem: ones compliment also has two values of 0:I +0: 00000000I -0: 11111111

I

Examples (Twos compliment of +107 = 01101011.)

Ones compliment: 10010100

0 01

00

00

01

00

01

00

00

+110010101


Desirable Properties of Twos Compliment

1. There is only one representation of 0. (This can be seen bytaking the 2s comp. of 0.) (Taking the 1s comp. of 0 andadding 1.)

1 11

11

11

11

11

11

11

01

+100000000

2. Negation is idempotent. ( a = a)2s-comp(00011010) = 111001102.s-comp(11100110) = 00011010

3. The negative of a number is its additive inverse.(a +a = 0) As an example, we do 26 +26.

1 10

10

10

11

11

10

01

00

+1110011000000000


Shortcut 2s Comp. Calculation

A copy transformation is used to calculate the 2s comp. of abinary number.

00111001

00100110

trail. 0's1st 1rest

as isas is1's comp.


Boolean Algebra

I Boolean algebra is an algebra, like arithmetic algebra, in whichwe form expressions from operators, and operands.

I Arithmetic algebra, the expressions are used to describefunctions that operate on numbers.

I In Boolean algebra the expressions operate on Boolean values:false, written a 0, and true, written as 1.

Examples

Arithmetic expression:x + 2 y

Boolean expression:a b + a b

(+ is the OR operator, and is the AND operator.)


AND, OR, and NOT Operations

Truth tables:

a b a b a + b0 0 0 00 1 0 11 0 0 11 1 1 1

a a

0 11 0

I The truth table shows the output of a Boolean function, forevery possible value of input.

I It is split into an input half, and an output half.

I To produce all input values, count in binary, with each rowhaving a different count in the input half. (In the table forAND, and OR, this would give 2-bit counts of 00, 01, 10, and11.)


Other Common Boolean Operators

Operators XOR, XNOR, NAND, and NOR.

a b a b a b a b a + b0 0 0 1 1 10 1 1 0 1 01 0 1 0 1 01 1 0 1 0 0


Operation Summary

I a b (AND): outputs 1 iff all of its operands are 1.I a + b (OR): outputs 1 if any of its operands are 1.

I a (NOT): outputs 1 only if its operand is 0.

I a b (XOR): outputs 1 iff its operands are not equal.I a b = a b (XNOR): outputs 1 iff its operands are equal.I a b (NAND): outputs 1 only iff at least one of its operands is

0.

I a + b (NOR): outputs 1 iff all of its operands are 0.


Boolean Expressions, & Truth Tables

Examples

g = (ab + c) (ac + b)a b c ab ab ab + c c ac b ac + b g

0 0 0 0 1 1 1 0 1 1 00 0 1 0 1 1 0 0 1 1 00 1 0 0 1 1 1 0 0 0 10 1 1 0 1 1 0 0 0 0 11 0 0 0 1 1 1 1 1 1 01 0 1 0 1 1 0 0 1 1 01 1 0 1 0 0 1 1 0 1 11 1 1 1 0 1 0 0 0 0 1

I Boolean operators are combined to form Boolean expressions.I To build a truth table from a Boolean expression, form

columns for intermediate subexpressions.


Boolean Expressions, & TruthTables (cont.)

Examples (Converting from table to equation.)a b c h

0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1

h = abc + abc + abc + abc


Table to Equation

I h is 1 only if a is 0, b is 1, and c is 0, or a is 1, b is 0, and cis 1, or a is 1, b is 1, and c is 0, or a is 1, b is 1, and c is 1.

I These correspond to the rows in the truth table that haveoutput of 1.

I The multiplicative terms that contain all input variables arecalled minterms.

I Minterms correspond to rows in the truth table.

I They are often referred to by there number. Reading theinput values of a row as a binary number yields the number.For example for a = 0, b = 1, and c = 1, we get the mintermnumber 011, so abc is Minterm 3.


Dont Care Conditions

An analogous incomplete function.

B(n, k) =

B(n 1, k) + B(n 1, k 1), 0 < k n1, n = k

1, k = 0

I When k = 0, the value of n doesnt matter - we dont carewhat it is; the function always returns 1.

I In Boolean algebra, we indicate dont care conditions with thesymbol X.


Dont Care Conditions (cont.)

Examplesa b c f g

0 0 X 0 10 1 0 1 X0 1 1 X 11 0 0 0 11 0 1 1 01 1 X 1 0

I When the dont care is on the output, we do not care whatthe output is, and the designer can choose what to output, tooptimize a circuit.

I When the dont care is on the input side, the given output isfor both a 0, and a 1 value of the input. (The last line of thetable is for both Minterm 110, and Minterm 111.)


Boolean Simplification using Identities

Identities allow us to transform expressions into equivalentexpressions.

Examples (Arithmetic expression transformation using thedistributive law.)

(2a + 6) (2a 6)= (2a + 6) 2a (2a + 6) 6= 22a2 + 6 2a (6 2a + 62)

(Distributive Law: a(b + c) = ab + ac.)

There are other identities that allow further transformation.


Boolean Identities

Simplifying Boolean expressions allows us to build circuits thathave fewer components, consume less power, are faster, and takeless physical space.

Identities:

1. Double negation: a = a

2. Contradiction: a a = 03. Tautology: a + a = 1

4. Commutativity: a + b = b + a, a b = b a5. Associativity: a + (b + c) = (a + b) + c , a (b c) = (a b) c6. Identity elements: a + 0 = a, a 1 = a7. Zero elements: a + 1 = 1, a 0 = 08. Idempotency: a + a = a, a a = a


Boolean Identities (cont.)

Identities:

9. Distributive:a (b + c) = a b + a c , a + bc = (a + b) (a + c)

10. DeMorgans: a + b = a b, a b = a + b11. Definition of XOR: a b = a b + a b

I DeMorgans Law specifies how to bring a negation into agroup. It also specifies two algebraic forms for the NAND,and NOR operators.

I The XOR operator has an algebraic equivalent. So does theXNOR operator:

a b = ab + ab


Example Simplification using Identities

Examples

(ab + c) bc= ab + c bc + (ab + c) bc (R11)= (ab c)(b + c) + (ab + c)bc (R10)= (ab c)(b + c) + (ab + c)bc (R1)= (a + b) c)(b + c) + (ab + c)bc ((R10)= (a + b) c(b + c) + (ab + c)bc (R1)= c (a + b)(b + c) + bc (ab + c) (R4)= (c a + cb)b + (c a + cb)c + cabb + bc (R8, R4, R10)= b(c a + cb) + c(c a + cb) + 0 + bc (R4,R2, R7)= bc a + bcb + c c a + c cb + bc (R6, R9)


Example Simplification Using Identities (cont.)

Examples

= bc a + 0 + c a + cb + bc (R8, R4, R2, R7)= c a(b + 1) + b(c + c) (R6, R4, R9)= c a 1 + b 1 (R3, R7)= c a + b (R6)

I Algebraic simplification is difficult, requiring strategicplanning.

I To allow automation of simplification, a more mechanicalmethod is needed.


Boolean Simplification using Karnaugh-Maps

I There are only four Boolean functions with less than twoparameters.

1. f0 = 02. f1 = 13. fidentity (x) = x4. finverse(x) = x

I The smallest interesting functions have two independentvariables.

I K-maps come in differing sizes, depending on the number ofindependent variables.


K-Maps of Two Variables

Examples

g = ab + ab + ab

a b g

0 0 10 1 01 0 11 1 1

g b

a

0 1

0

1

1

1 1

0

g = a + bComputer Organization: Basic Processor Structure

Combining Cells in the K-Map

The 2-variable K-mapr is a square with one variable on each axis.

Cell combination:

1. Adjacent cells that contain 1 can be combined.

2. Combined cells must form a rectangular group.

3. The size of a group must be a power of two.

4. The groups copied out must cover all cells that are 1. (Notice,however, that cells may be covered by several groups.)

5. The group names are ORed together, to form a simplifiedequation.

6. Group names are the AND of all variables that do not changetheir value, in the group.

7. The covering groups must be as large as possible.


K-Maps for Functions of Three Variables

Examples

a b c h

0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

h

a

bc

0

1

00 01 11 101 1

1 1 1

0 0

0

h = c + ab


K-Maps for Functions of Three Variables (cont.)

I The 3-varaible K-Map is two 2-varaible K-maps stucktogether..

I The vertical axis is one of the variables, and the horizontalaxis is both of the other two variables.

I The horizontal coordinates are listed in Gray code sequence.

I Between elements of the Gray code sequence, only one bitchanges.

I K-Maps wrap around, both vertically, and horizontally. Thismeans that the cells on the let are next to the cells on theright of the Karnaugh-map.


K-Maps for Functions of Four Variables

Examples (Four variable)a b c d z

0 0 0 0 10 0 0 1 10 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 00 1 1 0 10 1 1 1 01 0 0 0 11 0 0 1 11 0 1 0 11 0 1 1 11 1 0 0 01 1 0 1 01 1 1 0 11 1 1 1 0

z

ab

cd

00

01

11

10

00 01 11 101 1 1 1

1 1

1

1 1 1 1

0 0

0 0 0


K-Maps for Functions of Four Variables (cont.)

Examples (Four variable (cont.))

z = b + cd + a cdMore than 4-variable K-maps become large, and it is best to use asoftware authoring tool to do simplification, rather than draw amap by hand.


Dont Care Conditions in Karnaugh-Maps

Examples

a b c m

0 0 0 10 0 1 X0 1 0 00 1 1 11 0 0 X1 0 1 11 1 0 X1 1 1 0

m

a

bc

0

1

00 01 11 10

1 1

1X

X

X

0

0


Dont Care Conditions in Karnaugh-Maps (cont.)

I Dont cares in the output can be assigned either a value of 0,or 1, to yield the best simplification, allowing larger groups tobe pulled out of the K-map.

I Without using the dont cares.m = abc + abc + abc

I Using the dont cares.m = b + ac.


Chapter 3: Digital Circuitry

I Processors are digital circuits.I Digital circuits have wires that carry one of two possible

signals.I low : a low voltage, like 0V.I high: a high voltage, like 5V.

I we are not concerned with the actual voltage, and so we callthese signals 0, and 1.

I How 0, and 1 are assigned to voltage is irrelevant to us.I Types of digital circuits:

I Combinational circuits: they have no memory. The outputscan change immediately when the inputs are changed.

I Sequential circuits: they have memory. The outputs may notchange when the circuit is remembering a previous value.


Combinational Circuits

Logical gates:

ab ab

ab a + b

a a

ab a + b ab ab

ab a + b

ab a b

(AND, OR, NOT (inverter), XOR, NAND, NOR, XNOR)


Using Gates

Examples

Boolean function.f = (a b)(b + c)

Schematic.

a

b

c

f


Using Gates (cont.)

Examples (cont.)

Alternate drawing.

a

b

c

f


Buffers

The triangle on the inverter is a buffer, and the open circle is theinversion element.

Inverter types:

a a

a

a

c

m

a

(inverter, simple buffer, tri-state switch)


Simple Buffer

It boosts power. It is use in fanout situations, where splitting asignal weakens it.

x

x

x

x

x

x

x

x


Tri-State Switch

The control line, c, when cleared, turns the flow off (sets theoutput to a state of high impedance, Z ). The output has threestates: Z , 0, and 1.

a c m

0 0 Z0 1 01 0 Z1 1 1


Common Combinational Circuits

I The decoder - transforms a numeric code into trigger signals.

I The encoder - translates trigger signals into a code.

I The multiplexer - routes multiple inputs imnto a single outputline.

I The adder - Adds binary signals that represent numbers.


The Decoder

x1x0 p2

p0p1

p3

Dec2-4

I A decoder is a switch. It turns on (sets) one of several outputlines, and turns off (clears) the rest.

I The code x gives the index of the line to turn on.

I As an example, if x = 01, p1 would be 1, and all otheroutputs would be 0.

I Decoder sizes: k 2k . k is the number of inputs, 2k is thenumber of outputs.


The Decoder (cont.)

Examples (4-1 decoder)x1 x0 p0 p1 p2 p30 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

p0 = x1 x0p1 = x1x0p2 = x1x0p3 = x1x0

x1

x0

p0

p1

p2

p3


The Encoder

x1x0p2

p0p1

p3

Enc4-2

I An encoder checks several circuits, with only one circuit on(set), and reports a code indicating which circuit is.

I The code, x , gives the index of the line that is on.

I As an example, if p0 = 0, p1 = 0, p2 = 1, and p3 = 0, thenthe output x would be 10.

I Encoder sizes: 2j -j .


The Encoder (cont.)

Examplesp0 p1 p2 p3 x1 x01 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1

(Rows that are not shown aredont cares.)

x1 = p2 + p3x0 = p1 + p3

x1

p0p1

p2p300 01 1011

00

01

10

11

11

0

0

X X

X X X

X X X

X X

X

X

x0

p0p1

p2p300 01 1011

00

01

10

11

01

0

1

X X

X X X

X X X

X X

X

X

x0

x1

p0

p3

p2

p1


Encoder Schematic

Examples (cont.)

x0

x1

p0

p3

p2

p1


The Multiplexer (MUX)

MUX4-1 p

i0i1

i3i2

s1 s0

I A MUX routes one of several inputs to a single output.

I Only one input is allowed to pass through. The other inputsare stopped.

I The input allowed through is specified by the code s.

I As an example if s = 11, the output p would be whatever ison the line i3.

I MUX sizes: 2k 1. Width of the selector line s: k bits.


The Multiplexer (cont.)

Examplesi0 i1 i2 i3 s1 s0 p

0 X X X 0 0 01 X X X 0 0 1X 0 X X 0 1 0X 1 X X 0 1 1X X 0 X 1 0 0X X 1 X 1 0 1X X X 0 1 1 0X X X 1 1 1 1

p = i0s1 s0+i1s1s0+i2s1s0+i3s1s0(Simplification is either byK-map, or by copying out eachminterm, ignoring the dont careconditions.)


MUX Schematic

Examples (cont.)

s1s0

i1i0

i2i3

p


MUX Composition

Examples (4-1 MUX from 2-1 MUXs)

MUX2-1

MUX2-1

MUX2-1

i0i1

i2

i3

s0 s1

p

I The MUXs are structuredinto a tournament, in theprocess called interleaving.

I The low-order bit, s0, isused to choose the betweenodd, and even indexes, inthe first round.

I The high-order bit, s1,chooses between the twofirst-round-heats, in the finalround.


The Adder

cin 0 1a 0 1

+b +1 +1scout 01 11

a

b

cin

cout

s+

An adder adds three 1-bit numbers, a, b, and cin, to form a sumbit, s, and a carry bit, cout .


The Adder (cont.)

cin a b cout s

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

s = cin a bcout = cina + cinb + ab

Checkerboard pattern for cout :

I XOR - odd parity cellcoordinates (the oddfunction).

I XNOR - even parity cellcoordinates (the evenfunction).

couts

cin cin

abab

0 0

11

00 01 11 10 00 01 11 101

1 11

0

0

0 0

1

1

1

1

0

0

0

0


Adder Schematic

a

b

cin

s

cout


The Ripple-Carry Adder

To add multi-bit numbers we use several adders, one per column ofthe long addition problem, to add the a operand, b operand, andthe carry-in. The carry-out becomes the carry-in of the nextcolumn.

1 11

10

11

01

+11011000

Notice that the carry ripples up from the bottom column, to thetop. (The calculation of one column has to wait until thecalculation of the previous column is complete.)


The Ripple-Carry Adder (cont.)

a0

a1

a2

a3

b0

b1

s0

b3

b2

s1

s2

s3

cin

cout

+1

+0

+3

+2

a

b+

4-bits

4

cin

cout

4

4

(4-bit bus line in the interface diagram indicate inputs of fourlines.)


Sequential Circuits

I Sequential circuits are called sequential because the flowthrough a sequence of states.

I Code example:sum = 0

for i = 1 to n do

sum = sum + i

I The state is the variables, and their values.


The Clock

The clock is a device that produces regular beat type signal.

0

1

t

period

I The signal has a rising edge, and a falling edge.I The time for one cycle is called the period.I The frequency is the number of cycle per second.

F = 1P , where F is the frequency, and P is the period.I The unit of measurement for frequency is a Hertz. 1 Htz = (1

cycle) / (1 second). (50MHtz = 50,000,000 cycles persecond.)


The Clock (cont.)

I The clock is used to synchronize the state changes ofsequential circuits.

I On of the two signal edges is designated as the trigger edge.

I All all state changes occur on the trigger edge. This simplifiesthe interaction between circuits.

I In our discussion we assume that the trigger edge is the risingedge.

I Although must circuitry in the processor are synchronized,there are a small number of asynchronous circuits. Not havingto wait for the trigger edge for a state change helps speed upasynchronous circuitry.


Storage Devices

Types:

I The latch - an unclocked device that stores one bit.

I The flip-flop - a 1-bit clocked storage device.I Device subtypes:

I D-typeI J-K-type


The D-latch

D-latchD

C

Q

Q

The D-latch is controlled by the input C . When C = 1, the latchis loaded with the value D. When C = 0 the latch locks its currentvalue, ignoring D. The output Q is the value stored in the latch.

D-latch exitation table:

D C Q(1)X 0 Q(0)0 1 01 1 1

(Q(0) - old latch value, Q(1) - new latch value)


The D-latch (cont.)

Examples

Example timing diagram for the D-latch.

D

C

Q


The D-flip-flop

DD

Clk

Q

Q>

On the D-flip-flop, the control signal is the clock. The flip-floponly loads exactly at the trigger edge.

D-flip-flop excitation table:

D Clk Q(1)X / Q(0)0 01 1

(Arrows indicate passing trigger edge.)


The D-flip-flop (cont.)

Examples

Example timing diagram for the D-flip-flop.

D

Clk

Q


The J-k Storage Devices

>J-K-latch J-K

J J

KK

Clk

Q Q

Q Q

J-K excitation tables.

J K Q(1)0 0 Q(0)0 1 01 0 1

1 1 Q(0)

J K Clk Q(1)X X / Q(0)0 0 Q(0)0 1 01 0 11 1 Q(0)


The J-K Storage Device (cont.)

Operations of the J-K Device:

I Lock: The device keeps its current value. This operation isspecified with J = K = 0.

I Set: The value of the device changes to 1. This operation isspecified with J = 1,K = 0.

I Reset: The value of the device changes to 0. This operation isspecified with J = 0,K = 1.

I Compliment: The value of the device is toggled from 0 to 1,or from 1 to 0. This operation is specified with J = K = 1.


Flip-Flops with Extra Pins

DD

Clk >

ST CL

LD

Q

Q

I The set pin (ST) is asynchronous (changes do not wait forthe clock pulse, but occur instantly). It initializes the flip-flopto 1.

I The clear pin (CL) is also asynchronous, and initializes theflip-flop value to 0.

I The load pin (LD) disables the clock signal, locking the valueof the flip-flop.


Flip-Flops with Extra Pins (cont.)

It is possible to implement the LD line on flop-flops that do nothave a load input, using a feedback loop.

>D

D

LD

Clk

Q

Q0

1


Sequential Design using the FSM

The tool for sequential circuit design is the finite state machine(FSM). The state diagram is a graphical representation of an FSM.

Examples (FSA0)

1

0

1

0

10

1

0

00/1 01/1

10/111/0

I States are the circles. Theirlabels are S/P, where S isthe state number, and P isthe output.

I Transitions are the arrows.They are labeled with I , theinput. Transitions from agiven state must havemutually exclusive labels.


The FSM and State Diagrams

Examples (FSA0 (cont.))

The interface for FSA0.

>i

ClkpFSA0

The FSM shows the output ateach state, and the transitionform one state to the next, onthe clock pulse, and based on theinput.

Examples (FSA1)

0/10 1/01

00,10

01,11

00,11

01,10

>Clk

ab c1

c0FSA1


The FSM and the State Transition Table

The state transition table is a tabular representation of the statediagram.

Examples (FSA0)i Q(0)1 Q(0)0 Q(1)1 Q(1)0 p

0 0 0 0 1 10 0 1 0 1 10 1 0 0 0 10 1 1 0 0 01 0 0 0 0 11 0 1 1 0 11 1 0 1 1 11 1 1 1 1 0


The FSM and the State Transition Table (cont.)

I The table has an input half, and an output half.

I In the input half you list the circuit inputs, and the bits of thecurrent state number, Q(0).

I In the output half you list the next state, Q(1), and the circuitoutputs.

I Each row represents a transition.

I Circuit output is based on the current state.


The FSM and the State Transition Table (cont.)

Examples (FSA1)

The transition table for FSA1.

a b Q(0) Q(1) c1 c00 0 0 0 1 00 0 1 1 0 10 1 0 1 1 00 1 1 0 0 11 0 0 0 1 01 0 1 0 0 11 1 0 1 1 01 1 1 1 0 1


State Diagrams, and Transition Tables; Building OneRepresentation from the Other

From table to diagram.

I Lay down states using numbers from the current state column.

I Fill in outputs from the output columns.

I Draw arrows, one per row in the state table, from the currentstate to the next state.

I Fill in the input labels on the diagram, from the inputcolumns in the table.


State Diagrams, and Transition Tables; Building OneRepresentation from the Other (cont.)

From diagram to table.

I Create the state table heading, listing out the input variables,the bits of the current state number, the bits of the next statenumber, and the output variables.

I Fill in all possible bit configurations on the input half of thetable.

I On each row, fill in the output for the current state.

I On each row, fill in the next state, using the arrow in thestate diagram corresponding to the row in the transition table.

Bits in the state number: for m states, you will have dlog me bits.


Moore versus Mealy Machines

A Moore machine associates output with the current state only. AMealy machine associates output with the current state, and theinput. The result, in the Mealy diagram, is that the output label ison the transition, and not the state.

Examples (Mealy machine for FSA1)

0 1

00/10,10/10

01/01,11/01

00/01,11/01

01/10,10/10


Implementing a Sequential Design

The Structure of a sequential circuit.

>ControlRegister

Input

Output

Q(0)Q(1)

I The register is a collection of flip-flops that store the currentstate number.

I The control circuit is a combinational circuit that calculatesthe output, and the next state.


Implementing a Sequential Design (cont.)

Examples (FSA0)

Equations for next state, and output are derived using K-maps, inhe usual way.

Q(1)1 = iQ(0)0 + iQ(0)1 = i(Q(0)0 + Q(0)1)

Q(1)0 = i Q(0)1 + iQ(0)1 + Q(0)1Q(0)0p = Q(0)1 + Q(0)0

I Use one flip flop to stoer each bit of the current state number.

I The input of the flip-flop is the next state, and the output ofthe flip-flop is the current state.



Examples (FSA0 (cont.))

Schematic of FSA0.

>

>D0

D1

pi

Q(0)0

Q(0)1

Q(1)0

Q(1)1



Examples (FSA1)

Equations.Q(1) = ab + aQ(0)b + aQ(0)b = ab + a(Q(0) b)c1 = Q(0)c0 = Q(0)

Schematic.

>D

ab c0

c1


Sequential Circuit Analysis

Going from schematic to FSM. Reverse the procedure used indesign.

Examples

Schematic:

zp

D0

D1

>

>


Sequential Circuit Analysis (cont.)

Examples (cont.)

Equations (byfollowing connectionsin the schematic):

p = Q(0)0 Q(0)1Q(1)0 = zQ(0)0Q(1)1 = Q(0)0 +zQ(0)1

Table:

z Q(0)1 Q(0)0 Q(1)1 Q(1)0 p

0 0 0 1 0 10 0 1 0 1 00 1 0 1 0 00 1 1 0 1 11 0 0 1 0 11 0 1 0 0 01 1 0 1 0 01 1 1 1 0 1


Sequential Circuit Analysis (cont.)

Examples (cont.)

State Diagram (copy out rows as transitions):

00/1 01/0

10/011/1

10

00,1

0,1

1


Common Sequential Circuits

I Used to store multiple bit binary numbers.

I They use one flip flop to store each of the bits.

I Bit numbering:x = 1100 = x3x2x1x0

I Register types.I Parallel load register.I Shift register.I Counter.


The Parallel-Load Register

Its a multi-bit flip-flop.The LD input causes the MUXs to feed the value back, for a lockoperation, or feed in a new value, for a load operation.

D0D1D2D3> > > >

0

1

0

1

0

1

0

1d0d1d2d3

Q0Q1Q2Q3

LD


The Shift Register

The input SH controls the operation: SH = 0, to lock the register,and SH = 1 to perform a shift.Input MUXs implement the operations with feedback loops, or theoutput of the adjacent bit.

Cincout

cin cout

Shift-left

Shift-right


The Shift Register (cont.)

Shl-Reg4-bit

SH

Q>

4cin

cout

D0D1D2D3> > > >

0

1

0

1

0

1

0

1

Q0Q1Q2Q3

SH

cout

cin


The Counter

I An input IN chooses an operation: IN = 0, the register islocked, and IN = 1, the register increments.

I The increment takes the register through the sequence 0000,0001, 0010, ..., 1111, 0000, ..., one value per clock cycle.

I It uses an adder to increment.

I The input MUX now chooses between a feedback, or theadder.


The Counter (cont.)

Count4-bit

IN

Q>

4

cout

D0D1D2D3> > > >

0

1

0

1

0

1

0

1

Q0Q1Q2Q3

INcout

+ ++ +1

0000


The Standard Register

Reg4-bit>

d Q

cout

LD IN CL

4 4

d

LDINCL

Qcout

0123

Enc

D +>0000

0001

4

4

4

4

4

4

44

2

4


The Standard Register (cont.)

I We combine an increment, a load, and a clear operation toform a register that we use regularly.

I All 4-bit inputs are are shown by abrevieted notation, using abus.

I A MUX chooses between one of four computation units thatcalculate one of the operations.

I An encoder turns the three trigger lines into a code that canbe used to operate the MUX.


Chapter 4: Devices and the Bus

I Devices that interact with the processor are mostly external tothe processor, but on the motherboard

I Device types (collectively knwn as external devices):I Memory devices.I Peripheral devices.

I Connection:I Direct connection - the processor can be connected to each

device using dedicated connections.I Bus connection - the processor is connected via a single shared

line to all devices.

I Comparison:I Wiring complexity - Bus connection produces simpler wiring.I Concurrent communication - Direct connection allows several

devices to communicate with the processor, simultaneously.


Devices and the Bus (cont.)

CPU Mem IO DevIO Dev

Bus


Memory

I Stores multi-bit values.

I Each storage device is calleda word.

I The memory unit has a size:l w , where l is the lengthof the unit (number ofwords), and w is the widthof the unit (number of bitsper word).

I Words are given addresses(numbers) to identify them.

0

1

2

3

4

5

6

7

Address

Memory8x4


Memory (cont.)

Memory operations:

I Read : produce the contents of a particular memory location.

I Write: store a given value in a particular memory location.

Memory types:

I Read Only Memory (ROM). (Allows a read operation only)

I Random Access Memory (RAM). (does both read and writeoperations)

RAM8x4 ROM

8x4DinDout

A

W E

DoutA

E

3 3

4 44


Memory Types

I ROMs are used, for example, to provide manufacturerinformation to an OS. (like the BIOS)

I RAMs are the standard working memory in a computer.I Inputs

I A - the address of the word.I Din - the input data for a write operation.I W and E - control the operation on a RAM unit. Assert W

for a write operation, and assert E for a read operation.I Dout - the output data for a read operation.


Memory Types (cont.)

Performing a read operation.

1. Assert he desired address on the A port.

2. Strobe the E line, and allow time for the data to present itselfon the Dout port.

Performing a write operation.

1. Set up the inputs.

1.1 Assert the desired address on the A port.1.2 Assert the desired data on the Din port.

2. Perform the operation by strobing (setting and the thenresetting) the W line.


Memory Composition

The size of a memory unit is 2k m, where 2k is its length, and mis its width. The unit would have a k-bit address port, to representaddresses between 0 and 2k .

Examples

An 8 4 memory has eight 4-bit words.An address is 3 bits (8 = 23). to specify addresses between 0 and7 (000 - 111).

Composition types:

I Horizontal - Creating a wider memory unit out of thinnerunits.

I Vertical - Creating a longer memory unit out of shorter units.


Horizontal Composition

Examples (Building an 8 4 RAM from two 8 2 RAMs.)

RAM8x4

A Dout43

E

RAM8x2

RAM8x2

A

E

Dout,3-2

Dout,1-03

3

3 2 1 0 3 2 1 0

RAM 8x4 RAM 2x(8x2)

2

2

W

Din,1-0

Din,2-34Din


Vertical Composition

Examples (Building an 8 4 ROM from four 2 4 ROMs.)01234567

01234567

ROM 8x4 ROM 4x(2x4)

ROM8x4

A Dout43

EDec2-4

012

3

A0

A1A2

ROM2x4

ROM2x4

ROM2x4

ROM2x4

E Dout

4

4

4

4

4


Vertical Composition (cont.)

I The ROM is split into four sections. Each section is coveredby a small ROM unit.

I We number the small units, 0 - 3, for our example. The 3-bitaddress is split into a unit number, and an internal address.

(The field sizes depend onthe composition beingperformed.) A0A1A2

Unit # Int. Address

I The unit number is used to enable the correct ROM, and theinternal address is fed into the ROM as its address signal.

I This, where the unit number is the high-order part of theaddress, is called high-order interleaving.

I When the unit number is the low-order part of the address,that is called low-order interleaving.


Internal Memory Structure

Dec2-4

0

1

2

3

Reg0

Reg1

Reg2

Reg3

2

2

2

LD

LD

LD

LD

W EDout

Din

A

2

2

2

2


Internal Memory Structure (cont.)

I Shown is a 4 2 RAM. Each word is stored in a register.I An address decoder turns an address into trigger lines.

I AND gates check for the the selected row, and the correctoperation.

I The input, Din, presents itself at each register, and enters theregister only if its LD input is triggered.

I The output, from each row is allowed onto the output bus,Dout , only if the tri-state switch is opened.

I A ROM has the same output structure, and no input.


RAM Types

RAM units can be classified as follows.

I Dynamic RAM (DRAM). It uses capacitors to store bits.(Charged is a 1, and depleted is a 0.) Capacitors leak overtime. A capacitpor memory has to be rewritten (refreshed) topersist.

I Static RAM (SRAM). It uses latches to store Boolean values.

Comparison:

I Access Speed: DRAM units tend to be slower than SRAM.This is because charging capacitors requires a latency.

I Density: Capacitors can be built much smaller than gates, andthe DRAM can be built more compactly than the SRAM.

I Cost: Storage using capacitor technology is cheaper to buildthan storage using the technology used in gates.


ROM Types

I ROM: Standard read-only memory. Contents are burnt in oncreation.

I PROM: Programmable ROM. Chips are originally blank.Using a PROM burner you ip;oad its contents. Once burnt, itis permanent.

I EPROM: Erasable PROM. The chip contains a window,through which you shine UV light, which erases the chipcontents. So, the chip can be reprogrammed.

I EEPROM: Electrically EPROM. The chip is erasable, like theEPROM, only with a special high voltage input pin.


Word and Byte Addressing

I The same memory is used o store both integers, andcharacters, which have radically different sizes.

I A character requires 8 bits (1 byte) to represent 256 possiblekeyboard characters.

I Use a combined memory. For a 16-bit integer, each wordwould be 16 bits. It would be split into 4 bytes, allowing us tostore 4 characters in it.

I Each byte has an address.

I Word addresses are multiples of 4. Byte addresses aremultiples of 1


Word and Byre Addressing (cont.)

Addressing for a 16 4 memory:

02468

101214

RAM 8x16

01byte

Instructions to store data into a bytemovb M[7], R0

or a wordmovw M[6], R0


Machine Byte Order

Addressing Schemes

I little-endian

I big-endian

0123 0 1 2 3

little-endian big-endian


Peripheral Devices

I Input devices. These are devices from which the processorreads data. The keyboard and pointer devices like the mouseare examples of input devices.

I Output devices. These are devices to which the processorwrites data. The monitor and printer are examples of suchdevices.

I I/O devices. These are devices that combine both an inputelement and an output element. The processor can write to,and read from, these devices. An example of such a device isa disk drive.


Peripheral Device Types

Reg

Reg

In

Out

I/O

Din

Din

Dout

Dout

LD

LD

E

E

Output Device

Input Device

I/O Device


Device Interface

I The output device has a register that is loaded with theoutput value.

I The input device has a switch that lets the input out of theoutput port.

I The I/O device has both interfaces.


Device Polling

I Problem: There is no way to determine when a device is readywith new input/output.

I Solution: Every device has a READY bit associated with it.

I The READY bit is raised to a 1 by the device, when thedevice is free.

I When the read/write operation is performed, the RFEADY bitis lowered to 0 by the processor.

I Before the processor accesses the device, it checks theREADY bit to see if it is 1, indicating the device is ready.


Interrupts

I When using device polling, the processor spends a lot of timebusy waiting. (In a loop where it checks the READY bit,over and over and over.)

I With interrupts, the processor is sent a signal when theREADY bit is raised. It no longer needs to busy wait.

I The processor can now work on another process, whileprocessing I/O.

I When an in interrupt is received, the processor suspends theprocess it is executing, and jumps to an Interrupt ServiceRoutine (ISR). The ISR handles the interrupt request.

I When the ISR is done, the processor jumps back to where itleft off in the other process.


Interrupts (cont.)

Interrupts have many causes. A CAUSE register is used by thedevice to pass the ISR a cause code, so that the ISR knows how to

handle the interrupt.

PC

ISR

User Program

Memory


Software Interrupts

I Even a user program can request to be interrupted. (Asoftware interrupt.) Why?

I System security:I User mode The process in user mode is limited in what

operations it can perform.I Kernel mode The process in kernel mode is unlimited.

I To do a kernel operation, the user program (operating in usermode) it requests a service of the OS by asking to beinterrupted, and passing the ISR information on its request.


The CPU

The processor is a device that executes the machine cycle over andover. Each time the machine cycle is executed, a single machineinstruction is executed.

Machine cycle:

1. Fetch. The PC contains the address of the next instruction tobe executed. The instruction indicated by the PC is fetchedinto the CPU from memory, and the PC is updated.

2. Decode. The processor determines the operation to beperformed, and the location of the operands required.

3. Execute. Any operands are fetched, the operation isperformed, and the result is written to the destination.


Bus Communication

Bus structure:

bus

A

D

Ct RdWt


Bus Use

There are three buses:

I The data bus carries data from the processor to the device. Italso carries data from a device to the CPU.

I The address bus carries addresses to memory units.

I The control bus carries the control signals read, to inputdevices, and write, to output devices.

How does a bus device know if a message is for it, or some otherdevice?


Bus Addressing

Every device has a collection of bus addresses that belong to it.The bus address is split into two fields:

I The unit number every device on the bus is given a numberthat identifies it.

I The internal address memory units are sent addresses forread and write operations.


Bus Addressing Example

I An 8 4 RAM unit; addresses range from 0000000 to0000111.

I A 16 4 ROM unit; addresses range from 0010000 to0011111.

I An input device with address 0100000.

I An output device with address 0110000.

I An I/O device with address 1000000.


Bus Addressing Example (cont.)

Deduce:

I The unit number is 3 bits (there are 5 devices).

I The internal address is 4 bits (the largest memory unit is oflength 16).

I The bus address is 7 bits. This is the size of the address bus.

I The data bus is of width 4 (all units are at must 4 bits wide).

I The RAM should perform a read operation only if the CPUsends a unit number of 000, and a read request.

I The RAM should perform a write operation only if the CPUsends a unit number of 000, and a write request.


Bus Addressing Example (cont.)

I The ROM performs a read when the CPU asks for a readoperation on Unit 001.

I The input device performs a read when the request is for aread from Unit 010.

I The output device performs a write operation when therequest is for a write operation on Unit 011.

I The I/O device performs a read or write when the thatoperation is requested on Unit 100.

I For each device control input we use 2 gates:

1. Addressing gate checks for proper unit number.2. operation gate checks for the proper operation (read or

write).


Example Memory Connection

RAM8x4 ROM

16x4

A

D

Rd

Wt

7

4

4 44

A3-0A3-0

A6-4

A6,5 A4

W E

E

Din DoutA

DoutA


Example Peripheral Connection

A

D

Rd

Wt

7

4

InOut

I/O

Reg

Reg

E

LD E

LD

A6,4 A5 A6 A5,4

A5,4A6

44

4 4


Chapter 5: The Register Transfer Language Level

I RTL (register transfer langauge) provides a tool for describingcircuitry at a higher level than the FSM or truth-table.

I The tools we have developed so far are structural descriptions.They describe the structure of a circuit.

I RTL is a behaviorla description. It describes the behavior of acircuit.

I An RTL description is a collection of -instructions.

I Each -instruction describes a circuit.

I A -instruction is composed of one or more -operations.


RTL Design

A -instruction has two parts (separated by a colon):I A data-path specification, describing how data flows through

the circuit.I A control part indicating when the -operations are

performed.

Examples (RTL implementation)

T : R1 R2

R1

R2

T

LD>

>


RTL Design (cont.)

Examples (Use of trigger gates to generate control.)

ab + c : R1 0

abc

R1

CL

>


RTL Design (cont.)

Examples

ab : R1 R1 + R2,R2 3

ab

3

+

R1

R2>

>

LD

LD


RTL Design (cont.)

Examples (RTL with input choice, using a MUX and OR gate.)ab : R1 R1 + R2ab : R1 3

a

b

R1

R2

+

013

LD

>

>


A Larger Example

Examples (Use of decoder instead of trigger gates.)x y : R1 R1 + R3,R2 0xy : R3 R3 + 1xy : R2 R1,R0 R3xy : R1 R0,R3 5

R0 R1

R2R3

+

01

Decxy

5LD CLLD IN

LD LD

0123

> >

> >


RTL Analysis

To generate an RTL description from a schematic:

1. Write down control signals, using the decoder values. For theprevious example, Option 0 gives us xy , Option 1 gives us xy ,and so on.

2. Follow the decoder trigger lines to determine the -operationsperformed. For example for Option 2, the trigger line triggersthe LD line on R0, and the IN line on R3. This means that a-operation is performed on R0, and Another is performed onR3.

3. Follow the data-path lines to determine the exact-instruction. In the example the input port of R0 isconnected to R3, giving us the -instructionxy : R0 R3,R3 R3 + 1

4. Repeat the procedure for all decoder options.


From Structural to Behavioral Description

The method of transforming from circuit diagram to RTL is notuniversal. Here is a universal method.

i Q(0)1 Q(0)0 Q(1)1 Q(1)0 p

0 0 0 0 1 10 0 1 0 1 10 1 0 0 1 10 1 1 0 0 01 0 0 0 0 11 0 1 1 0 11 1 0 1 1 11 1 1 1 1 0


Structural to Behavioral (cont.)

Copy of each row as a -instruction.

i Q1 Q0 : Q 1, p 1i Q1Q0 : Q 1, p 1iQ1Q0 : Q 1, p 1iQ1Q0 : Q 0, p 0iQ1 Q0 : Q 0, p 1iQ1Q0 : Q 2, p 1iQ1Q0 : Q 3, p 1iQ1Q0 : Q 3, p 0


Problems with Reverse Engineering

Building a circuit from this -program, with data-path and control,yields a poor design, compared to the original design. Themechanical translation looses semantic information.)

Q

01234567

p

01234567

1

1

1

11

10

0

0

1

2

1

3

1

3

0

>

i

2

2

222

22

22

2

LD

1


Common Processor -Instructions

RTL is good at describing high-level circuitry, but it can be used atall levels.

Examples (Combinational Circuit: the MUX)s1 s0 : p i0s1s0 : p i1s1s0 : p i2s1s0 : p i3

Examples (Sequential Circuit: the J-K flip-flop)JK : Q 0JK : Q 1JK : Q Q

Examples (Sequential Circuit: the counter)

IN : Q Q + 1Computer Organization: Basic Processor Structure

Processor -Instructions

Arithmetic

1. Addition: X X + Y2. Subtraction: X X Y3. Increment: X X + 14. Decrement: X X 15. Transfer: X Y6. Clear: X 0

Logic

1. AND: X X Y2. OR: X X Y3. NOT: X X4. XOR: X X Y


Processor -Instructions (cont.)

Shift

1. Logic Shift left: X shl X2. Logic Shift right: X shr X3. Circular shift left: X cir X4. Circular shift right: X cil X5. Arithmetic shift left: X ashl X6. Arithmetic shift right: X ashr X

Memory

1. Read: X M[AR]2. Write: M[AR] X


Processor -Instructions (cont.)

Logic operations are bitwise. (they are done column by column.)

0110 0 1 1 0 0101 0 1 0 1

0100 0 1 0 0

Shifts of 1110

1. shl: 1100

2. shr: 0111

3. cil: 1101

4. cir: 0111

5. ashl: 1100

6. ashr: 1111

Memory addresses arespecified using the addressregister (AR). To fetch aninstruction from thelocation specified by thePC requires two-operations.

AR PCX M[AR]


Shift types

Left Right

shl shr

cil cir

ashl ashr

0cout0

cout

cout cout

cout cout0


Algorithmic Machines

RTL is typically considered a declarative language: it specifies howa circuit is put together.

We can, however, use it as a procedural language: specifying asequence of steps, or actions.

Examples (The Teapot Example)

Design a control circuit for a teapot.

>

teaS

T H

X


Teapot Example

I InputsI S , the switch sensor: S = 0 if the switch is off, and S = 1 if

the switch is on.I T , the temperature sensor: T = 0 if the liquid is too cool, and

T = 1 if the liquid is hot enough.

I OutputsI X , turns off the on/off switch: X = 0 to turn the switch off,

and X = 0 to leave the switch state unchanged.I H, turns on the heating element: H = 0 turns off the element,

and H = 1 turns on the element.


Teapot Control Algorithm

stuck = 0

loopforever

if S and not stuck and not T then

H = 1

X = 0

stuck = 0

else if S and not stuck and T then

H = 0

X = 1

stuck = 1

else if S and stuck then

H = 0

X = 0

stuck = 1

else if not S then

H = 0

X = 0

stuck = 0


Teapot Flowchart

stuck = 0 S(stuck)T

S(stuck)T

S(stuck)

S

H = 1X = 0stuck = 0

H = 0X = 1stuck = 1

H = 0X = 0stuck = 1

H = 0X = 0stuck = 0

0

0

0

0

1

1

1

1

T0 T1

T2

T3

T4

T5

T6

T7

T8

I Each node of the chart isgiven a state name, Ti .

I A sequencer is a circuit thatproduces timing triggersignals, Ti .

I It consists of a counter, anda decoder.

I Each node becomes a-instruction in RTL, withthe timing signals as control,and the node actions asdata-path.


Teapot Sequencer

CDec

0123456789ABCDEF

T0T1T2T3T4T5T6T7T8

4


Generating RTL from the Flowchart

Def : T0 C = 0,T1 C = 1,T2 C = 2,T3 C = 3,T4 C = 4,T5 C = 5,T6 C = 6,T7 C = 7,T8 C = 8

T0 : stuck 0,C 1T1S(stuck) T : C 5T1S(stuck) T : C 2T2S(stuck)T : C 6T2S(stuck)T : C 3T3S(stuck) : C 7T3S(stuck) : C 4T4S : C 8T4S : C 1T5 : H 1,X 0, stuck 0,C 1T6 : H 0,X 1, stuck 1,C 1T7 : H 0,X 0, stuck 1,C 1T8 : H 0,X 0, stuck 0,C 1


RTL and Verilog

RTL can be thought of as pseudo-code for VHDL (VLSICHardware Description Language).

// tea pot controller

module teapot(clk, S, T, H, X);

// input ports

input clk, S, T;

// output ports

output reg H, X;

// internal registers

reg stuck;

reg [3:0] C;

// define the states

assign T0 = C == 4b0000;

assign T1 = C == 4b0001;

assign T2 = C == 4b0010;

assign T3 = C == 4b0011;

assign T4 = C == 4b0100;

assign T5 = C == 4b0101;

assign T6 = C == 4b0110;

assign T7 = C == 4b0111;

assign T8 = C == 4b1000;

// the circuit behavior

always @(posedge clk) begin

if (T0) begin

stuck = 0;

C = 4b0001;

end

if (T1) begin

if (S && !stuck && !T)

C = 4b0101;

else

C = 4b0010;

end


RTL and Verilog (cont.)

if (T2) begin

if (S && !stuck && T)

C = 4b0110;

else

C = 4b0011;

end

if (T3) begin

if (S && stuck)

C = 4b0111;

else

C = 4b0100;

end

if (T4) begin

if (!S)

C = 4b1000;

else

C = 4b0001;

end

if (T5) begin

H = 1;

X = 0;

stuck = 0;

C = 4b0001;

end

if (T6) begin

H = 0;

X = 1;

stuck = 1;

C = 4b0001;

end

if (T7) begin

H = 0;

X = 0;

stuck = 1;

C = 4b0001;

end



if (T8) begin

H = 0;

X = 0;

stuck = 0;

C = 4b0001;

end

end // behavior

// initialize the state

initial begin

C = 4b0000;

H = 0;

X = 0;

end

endmodule

I The moduledefinition gives thenames of the inputand output ports.This is followed bydeclarations that givethe port types, andsizes.

I Types are either inputor output, or reg, aregister, with optionalbit numbers tospecify the size.



I We define the timing signals, Ti , according to the sequencervalues.

I An action section specifies that the action takes place on thepositive edge of the clock signal.

I -instructions are implemented as if expressions. The testimplements the control, and the body implements thedata-path.

I The code contains -instructions for all timing signals, T0 T8.

I The last section initializes the registers.


Chapter 6: Common Computer Architectures

I We examine some common ways of organizing a processor.

I Each organization is currently in use in some processor.I Topics

I ISA (instruction set architecture) what instructions areavailable.

I Instruction format how information is codded as a number.I Addressing modes how location of operands is specified as

a number.


Instruction Set Architecture

Instruction types

I Data transfer. Move data from one location to another.

I Data manipulation. Perform arithmetic, logic, or shiftoperations on data.

I Control. Change the order of execution of machineinstructions.


Data Transfer Instructions

Categories based on location of the data.

I Register-to-Register. Movement inside the processor from oneregister to another.

mov R0, R1 ; R0

Data Transfer Instructions (cont.)

I Register-to-Device. Movement from a register out to anoutput device. (Devices are designated by their channelnumber.)

out 3, R0 ; D[3]

Data Manipulation & Data-Types

The processor operates on Data.

Common data-types

I Integer data.

I Real data.

I Boolean data.

I Character data.

I Binary coded decimal (BCD) data.


The Integer Data-Type

I Integer data consists of whole numbers.

I Integers are stored in a word.

I Word-size must be large enough to store the integer values auser is interested in operating on. Eight bits is not sufficient.A typical word size might be 32 bits.

I Integer typesI Unsigned integer all bit configurations of the word are used

to represent non-negative numbers. (The range for a 32-bitword is 0 232 1 < 4 109.)

I Signed integer half the bit configurations are used fornon-negative integers, and half are used for negative integers.


The Real Data-Type

I A real number is a number with a fractional part.I Real number representation is based on scientific notation.I There are three important pieces of information in the

scientific notation: sign, mantissa, and exponent.I On a computer, this scientific notation representation is called

floating-point formatI There are two sized floating-point formats: single precision,

with a 32-bit FP word., and douple precision, with a 64-bitword.

45.375 = 4.5375 101

sign

exponent mantissa


The Boolean Data-Type

I It only takes a single bit to store the values true, or false.

I Most computer memories can only be accessed by the word,or byte, and so this is not convenient.

I Boolean values are stored in a byte: 0 for false, and not 0 fortrue.


The Character Data-Type

I To represent characters on a computer, (we can only storenumbers on a computer) the characters must be encoded.

I All of the characters on a keyboard can be numbered withcode from 0 to 255. This requires 8 bits.

I Eight bits is called a byte. It is possible to encode allcharacter on the keyboard with code that fits in a byte.

I The standard 1-byte code is ASCII (American Standard Codefor Information Interchange).

I The ASCII byte is only large enough for the Latin characters.TO represent other languages and scripts a larger code isneeded.

I UNICODE is a 16-bit code. ASCII is a subset of UNICODE.To form the UNICODE code for a Latin character you prefix itwith a byte of 0. (Other languages have prefix bytes that arenot 0.)


Binary Code Decimal (BCD)

I Humans work in decimal. When inputing and outputingnumbers, numbers typically need to be converted to or fromdecimal and binary.

I BCD is a way of representing integers that allows easyconversion to or from binary and decimal. The drawback, isthat arithmetic is more complex for BCD than it is forpositional binary.

I In BCD, an integer is represented as astring of 4-bit binaryencodings of its digits.

Examples

Decimal 365 has digits3 0011 6 0110 5 0101

In BCD: 0011 0110 0101


Data Manipulation Operation Types

I Arithmetic operations. The usual arithmetic operations, likeaddition, subtraction, multiplication, and division.

I Logic operations. Bitwise Boolean operation, like AND, OR,and NOT.

I Shift operations. Shifting integers left or right.


Data Manipulation Operations: Arithmetic

Arithmetic Operations.

I A processor must support arithmetic on all numericdata-types.

I The ISA may contain an instructioniadd R0, R1

for integer addition, andfadd F0, F1

for floating-point addition.


Data Manipulation Operations: Logic

Logic Operations.

I Logic operators allow us to manipulate individual bits in aninteger.

I As an exampleor R0, #00010000b

sets Bit 4 in R0, ORing R0 with the mask 00010000.

I In the exampleand R0, #00010000b

the AND operator clears all bits but Bit 4 in R0.


Data Manipulation Operations: Shift

Shift Operations.

I Shift operations can be to the right, or left, and can belogical, circular, or arithmetic.

I As an exampleshl R0

shifts R0 by one bit to the left.

I Shift operators can be used to perform multiplication by aconstant. They can do this faster than a full multiplicationinstruction.

I As an example, to multiply R0 by 5:mov R1, R0 ; R1

Control Operations

Control operations change the flow of control of a program fromthe next sequential instruction to another instruction.

Types of instructions

I Unconditional branches.

I Conditional branches.

I Machine reset.

I Context manipulation.


Unconditional Branches

...jump xyz

...xyz:...

I The jump causes the execution of the instruction at label xyz.A label is a symbolic address.

I The smbolic address represents the memory address of thenext instruction in machine language.

I The jump instruction is called unconditional because thebranch is always taken. In a conditional branch, the branch istaken only under certain circumstances.


Conditional Branches: Arithmetic

...beq R0, xyz

...xyz:...

I The beq checks to see if R0 is equal to zero. If so it branchesto address xyz.

I If R0 6= 0, execution continues with the sequentially nextinstruction.

I It is called an arithmetic branch because the beq instructionperforms arithmetic (compares R0 with 0) to determine if thebranch should be taken.


Conditional Branches: Status Flag...

sub R0, #0

bz R0, xyz

...xyz:

...

I In status flag branches, there is a processor register (theFLAGS register) which is a collection of status bits.

I When the processor performs arithmetic it sets the status bitsaccording to the results.

I The bz (Branch if zero) instruction checks the Z status FLAGto determine if a jump should occur. The Z flag is set if theresults of the last arithmetic operation were zero.

I The subtract instruction before the bz instruction is used toset the Z flag to 1 if R0 is 0.


Machine Reset Instruction

halt

I This instruction halts the machine.

I Usually the user does not want to terminate a program byhalting the machine.

I Usually, when a program finishes it should return control tothe operating system.

I Only low level OS programs would need to halt the machine.


Context Manipulation Instructions: Subroutines

High and low-level subroutine instructions....f()...function f()

begin...

return

end

...call f

...f:...

ret


Context Manipulation: Subroutines (cont.)

I A function call is translated into a call instruction.

I A return statement is translated into a ret instruction.

I A call instruction causes a jump to the address specified.

I A ret instruction causes a jump back to the instructionfollowing the call instruction. (This jump is back to what iscalled the return address.)

I The return address is pushed on to the system stack by thecall instruction.

I When the ret instruction needs the return address, it ispopped off the stack.



Stack:I A LIFO (last in first out) data structure.I It supports a pop operation, which takes the top element off

the stack.I It supports a push operation that places a new element on the

top of the stack.

SP

SPSP

push(x)push(y)

xy

x

pop() = y



call instruction actions:

1. Push the return address on to the system stack.

2. Jump to the subroutine address.

ret instruction actions:

1. Pop the return address off of the system stack.

2. Load the popped return address into the PC.



Examples (A function f calls a function g)

SPSP

SPra(f) ra(f)

ra(g)

call f call g

retret


Context Manipulation Instructions: Interrupts

I Interrupts are like subroutines, except there is no callinstruction executed.

I Upon an interrupt, the control jumps to the start of the ISR.

I The interrupted program must be unaware that it has beeninterrupted.

I When the interrupt occurs, the state of the processor registersmust be saved. (This is called context saving.)

I On return from the interrupt, the processor registers must berestored (context restoration).

I An interrupt may be caused by stack problems. The returnaddress, and the context are therefor save in the ISR area,rather than on the stack.


Context Manipulation: Interrupts (cont.)

I A prgram can request to be interrupted with a syscallinstruction.

I A syscall instruction is issued when the program requests theOS to perform a service which it does not have permission toperform itself (like use a printer).

Examples (A syscallexecution.)...

syscall...ISR:...

iret

I The syscallinstruction jumps tothe fixed ISRlocation, and savesthe context.

I The iret instructionjumps back to thereturn address, afterrestoring the context.


Context Manipulation: Interrupts (cont.)

Executipon Modes:

I User mode. The program operating in user mode hasrestrictions. It cannot access certian devices, and certainmemory sections.

I Kernel mode. The program operating in kernel mode can doanything.

The users programs, typically operate in user mode. Many partsof the OS operate in kernel mode.

To terminate, a program asks the OS to take over. This is donethrough a syscall.


Instruction Format

Assembly instructions must be represented numerically.

Instruction partsadd R0, R1

I The operation: the operation being performed. In thisinstruction it is addition.

I The destination: the operand where the result will be stored.In this instruction this would be R0.

I The source: the other operand. In this case this would be R1.

Machine code equivalent

op dst src

6 5 5


Instruction Format (cont.)

Example instruction

001001 00000 00001

dst srcop

Full instruction: 0010010000000001

I The machine has 26 = 64 instructions in its ISA.

I The machine has 25 = 32 registers.


Addressing Modes

Numbers in operand fields have several interpretations, in a lesssimplistic computer. They could indicate a register number, amemory address, or a constant.Addressing modes indicate where the operand is found.Addressing Modes:

1. Direct mode.

2. Indirect mode.

3. Register direct mode.

4. Register indirect mode.

5. Immediate mode.

6. Implicit mode

7. Relative mode.

8. Indexed mode.


Addressing Modes (cont.)

Direct mode: The operand field gives the address of the effectiveoperand.

load R0, 5

R0 M[5]

Indirect mode: Theoperand field gives theaddress of a pointer to theeffective operand.

load R0, (5)

R0 M[M[5]]

RAM

5

9 3

9



Register direct mode: The operand field contains the number of aregister which contains the effective operand.

mov R0, R5

R0 R5

Register indirect mode: The operand field contains the number ofa register that contains a pointer to the effective operand.

load R0, @R5

R0 M[R5]

Immediate mode: The operand field contains the effective operand.mov R0, #5

R0 5



Implicit mode: An operand is not explicitly given.Operand explicitly given (subroutine address):

call 5

Operand not given explicitly (ISR address):syscall

Relative mode: The address of the effective operand is calculatedas the contents of the operand field added as an offset to thecontents of the PC.

load R0, $5

R0 M[PC + 5]


Addressing Modes: Relative Mode

Relative mode addressing allows the relocation of a program,without modifying addresses.

Examples (A program that addresses a location 125, inside itsworkspace.)

I VA: The address is absolute.load R0, 125

I VR : The address is relative to the PC.load R0, $25


Addressing Modes: Relative Mode (cont.)

If the workspace is moved, the load instruction is VA will fetchfrom outside the workspace. The load for VR will fetch from thesame offset inside the workspace.

PC125

PC

125

PC

80100

3050 75

5030

75 50 + 25

VA VR

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