Computer Structure Slides 1228491584281589 9

8/11/2019 Computer Structure Slides 1228491584281589 9

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Computer Structure

Mr Arthur


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Aims of Lesson 1

1. To discuss the 3 main parts of the

processor

2.

To discuss the functions of these 3 parts3. To introduce the address, data and control

buses


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Block Diagram of the

Computer System

PROCESSOR

MAIN MEMORY

BACKING STORAGE

DEVICES

INPUT

DEVICES

OUTPUT

DEVICES


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Parts of the Processor

Control Unit Makes sure the program instructions are carried out

in the correct order

Controls the ALU and Registers

Makes sure everything happens in the correct placeat the correct time

Registers A group of storage locations in the processor for

holding instructions being executed and addresses tobe accessed

Arithmetic Logic Unit Carries out all calculations in the processor

Carries out all logic functions using AND, OR and

NOT gates


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The Processor Structure

Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses


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Buses

Buses

Three sets of wires

called busesconnect the

processor to the memoryand input/output devices

Address Bus

Data Bus

Control Bus


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Buses

Address Bus

The address bus carries the address

information from the processor to main

memory and is unidirectional The number of wires in the address bus

affects how many storage locations can

be accessed

Each of the wires in the bus can be

switched on or off

A typical microcomputer has 32 wires in

the address bus and can therefore

address 2 locations32

Using 2 wires you

could address 4

locations i.e.

01

10

00

11

4 wires = 16locations

8 wires = 256locations

16 wires = 65,536

locations


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Aims of Lesson 2

1. To revise the role of the address bus

2. To introduce the data and control buses

3. To discuss the different control lines1. Read/Write

2. Maskable/Non Maskable Interrupt

3. Reset


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Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses

1000 0001


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Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses

0001 0001

READ LINE


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Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses

0001 0001

WRITE LINE


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Control Bus

The control bus is made up of a number of

separate wires each with their own functions

Read/Write Line

Reading from or writing to Main Memory

Reset Used to return the processor to its initial state

when the system freezes

Clock

The clock line carries a series of clock pulse at a

constant rate. These pulses synchronise the

processing

Measure in Giga hertz


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Control Bus

Interrupts

A signal from an input or output device that

causes a break in the processors current

program, for example, printer out of paper etc

Maskable

A piece of code can be written to ignore certain interrupts

Non Maskable Interrupts

The processor cannot mask or ignore the interrupt


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Aims of Lesson 3

Last Lessons

To revise the 3 differentbuses

1. Address

2. Data3. Control

To discuss the differentcontrol lines

1. Read/Write

2. Maskable/Non MaskableInterrupt

3. Reset

4. Clock

Todays Lesson

Discuss the Fetch Executecycle

Total Addressable Memory


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Memory Read Operation

Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses

1001 0111

READ LINE


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Fetch Execute Cycle

1. The processor places a value in the

Memory Address Register and sets up

theAddressBus with address

2. Control Unit activates the Read line3. Instruction is transferred from memory

to processor using data bus

4. Instruction is decoded

5. Instruction is executed This may result inanother Memory Read

Operation or a

Memory Write

Operation

Memory Read

Operation


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Memory Write Operation

Main

Memory

Other

registers

Arithmetic

and LogicUnit

Memory

Address

Register

Memory

Data

Register

Control

Unit

Address Bus

Data Bus

Control Bus

Electronic

Clock

Clock Pulses

0001 0001

WRITE LINE


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Memory Write Operation

1. The processor sets up theAddress bus

2. Processor sets up the data

bus with value to be written tomemory

3. Write line is activated

4. Contents are transferred tothe required storage locationin Main Memory


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= Number of storage locations X Size of eachstorage location

What is the total addressable memory if you

have an 8 bit address bus and a 16 bit databus?

= 2 X 16

= 256 X 16 = 4096 bits

8

= 512 kilobytes

8


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What is the totaladdressable memory ifyou have a 32 bitaddress bus and a 16bit data bus?

= 2 X 16 bits

2 X 2 bytes

= 2

= 1 Gigabyte X 2

= 8 Gigabytes

2 = 1 kilobyte

2 = 1 megabyte

2 = 1 gigabyte

32

32

33

10

20

30

3


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Aims of Lesson 4Last Lessons To revise the 3 different

buses1. Address

2. Data

3. Control

To discuss the differentcontrol lines

1. Read/Write


3. Reset

4. Clock

Discuss the Fetch Executecycle


Todays Lesson

Elements of ComputerMemory

Registers

Cache Main Memory

Backing Storage

Types of RAM

Dynamic Random Access

Memory Static Random Access

Memory

Video Random AccessMemory


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Computer Memory

The elements ofcomputer memory areregisters, cache, mainmemory and backingstorage

Registers Storage locations inside

the processor where data

can be accessedimmediately, or around 1nanosecond 10seconds

-9


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Cache Memory

A small amount of memory used to store often used

instructions

Level 1 Cache = build in to the processor chip, speeds of

access = 5 nanoseconds Level 2 Cache = build on to processor or very close to it,

speed of access = 15 nanoseconds

Cache

Memory

(SRAM)

ProcessorMain

Memory

(DRAM)


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Dynamic Random Access

Memory

DRAM is a type of RAM chip which needs to

have its contents constantly refreshed (about

1000 times per second)

Typical access time = 50 nanoseconds

Majority of computers main memory is made

up of DRAM as it is much cheaper that

SRAM


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Static Random Access

Memory

Used in the processorscache memory

SRAM does not need

to be constantlyrefreshed

Much faster thatDRAM, typically 10nanoseconds

Keep contents as longas power is applied toRAM chip


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Aims of Lesson 5Last Lessons To revise the 3 different buses

1. Address

2. Data

3. Control

To discuss the different control

lines1. Read/Write


3. Reset

4. Clock

Discuss the Fetch Execute

cycle Total Addressable Memory

Elements of Computer Memory Register, Cache, Main Memory,

Backing Storage

DRAM, SRAM

Todays Lesson

Video Random AccessMemory

Types of ROM

Backing Storage

Comparing Computer Memory Measures of Performance


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Video Random Access

Memory

VRAM is used to hold the data which is

displayed on the monitor

The amount of VRAM is directly related to the

number of colours and the screen resolution VRAM is sometimes contained in a separate

graphics card and can be upgraded to display

3D graphics


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ROM

Read Only Memory is a type of Memory where thecontents are stored permanently

Holds the Bootstrap loader

Programmable Read Only Memory= is empty of

data when you buy it and is programmed by theuser

Erasable PROM= can be programmed, erasedand reprogrammed, using a UV light

Flash ROM= May be programmed whilst inside

the computer and used in USB Pens and Memorycards for cameras


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Type of Memory Speed (nano seconds)

Registers Immediate 1

Cache

SRAMVery Fast 5/15

Main Memory

DRAMFast 50

Main Memory

ROMFast 50 to 100

Backing Store

Hard Disk(Virtual Memory)

Slow 1000000

Backing Store

Optical DiskSlow >1000000


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Measures of Performance

Clock Speed= The number of pulses per secondmeasured in Ghz

More clock cycles = more data fetched and executed

Fetching 1 instruction may take 10 clock cycles

MIPS= Millions of Instructions per second Measure of the average number of machine code

instructions executed

FLOPS= Floating Point Operations Per Second

Measure of the Arithmetical Calculating Speed of thecomputer


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Aims of Lesson 6Last Lessons

To revise the 3 different buses

1. Address2. Data

3. Control

To discuss the different controllines

1. Read/Write

2. Maskable/Non Maskable Interrupt

3. Reset4. Clock

Discuss the Fetch Execute cycle


Elements of Computer Memory Register, Cache, Main Memory,

Backing Storage DRAM, SRAM

Video Random Access Memory

Types of ROM

Backing Storage

Comparing Computer Memory

Measures of Performance

Todays Lesson Computer Structure Revision

Quiz

Factors affecting systemperformance Data Bus Width

Use of cache Rate of transfer from

peripherals

Other Factors Increasing clock speed

Adding more Main Memory

Increasing VRAM Adding more processors


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Computer Structure Quiz

1. Name the 3 buses connecting the processorto Memory and Input and Output devices

2. List 4 functions of control bus

3. Give the 5 steps in the fetch execute cycle

4. My computer has a 24 bit address bus anda 16 bit data bus. Calculate the total

addressable memory5. Which bus affects computer performance,

explain your answer


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Computer Structure Quiz

6. What is cache memory

7. Name the 2 main types of RAM

8. List the following in order of speed ofaccess, with the fastest firstCache Registers Backing Storage Main Memory

9. Name the 3 different types of ROM

10. Give 3 measures of computer performance


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Factors Affecting System

Performance Data Bus Width

Increasing the data bus widthincreases the quantity of dataflowing between the processor andmemory

word length

Use of cache It is much faster to access

instructions and data from cachethan main memory

Cache may have a separate databus called the backside bus

Rate of transfer fromperipherals The rate of transfer is

determined by the type ofinterface connecting peripheralto processor

USB 1 = 12 Megabits persecond

USB 2 = 480 Megabits persecond

Increasing clock speed

Adding more MainMemory

Increasing VRAM

Adding more processors


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D R i


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Data Representation

Learning Aims

1. Detailed description of the purpose of the ALU andthe Control Unit

2. Description of the purpose of registers, to hold databeing processed, instructions being executed, andaddresses to be accessed

3. Description of the function of the data bus and theaddress bus

4. Description of the read, write and timing functionsof the control lines

5. Identification of other control lines, including resetand interrupt lines

D t R t ti


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Data Representation

Learning Aims

6. Simple description, referring to the appropriate

buses and control lines, of the steps in the fetch

and execute cycle

7. Description of the following elements of computermemory, registers, cache, main memory and

backing storage

8. Distinction between the above elements of

memory according to function and speed of access9. The concept of addressability

D t R t ti


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Data Representation

Learning Aims

10. Description and evaluation of the following

measures of performance; clock speed, MIPS,

FLOPS and application based tests

11. Description of the effect the following factors haveon system performance; data bus width, use of

cache memory, rate of data transfer to and from

peripherals

12. Description of the following trends in computerhardware, including increasing clock speeds,

increasing memory and backing storage capacity

Documents

Computer Structure Slides 1228491584281589 9