© 2004 Xilinx, Inc. All Rights Reserved© 2004 Xilinx, Inc. All Rights Reserved

Implemented by :Alon Ben Shalom Yoni Landau

Project supervised by: Mony Orbach

High speed digital systems laboratory

Technion - Israel institute of technologydepartment of Electrical Engineering

Characterization PresentationCharacterization Presentation

Spring 2007

© 2004 Xilinx, Inc. All Rights Reserved

AgendaBackgroundPlatforms & DevicesProject Goals Stages of the projectSchedule

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BackgroundWhat is a CCD camera ?A silicon based camera – using the photoelectric principal

Why using a CCD camera ?Cheap high quality solution for videoimage applications CCD - Charge-Coupled Device

© 2004 Xilinx, Inc. All Rights Reserved

Background (Cont.)What is Virtex-II Pro ?

Virtex-II Pro ,supported by XUP board, is a complete FPGA system which includes up to 2GB DDR SDRAM, 10/100 Ethernet MAC/PHY, High/Low speed expansion connectors, USB2, PS/2 for mouse/keyboard and a serial port.

© 2004 Xilinx, Inc. All Rights Reserved

Platforms & Devices

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M4088 is a ¼ ” Monochrome digital camera

The M4088 digital camera is based on OV5017 CCD chip manufactured by OmniVision.Chip Interface : M4088 camera module.

M4088

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Camera Highlights

Low power consumption (< 100mW ).Array size 384*288 pixels.Built in A/D output – 8 bit pixel resolution.Programmable exposure setting.Single 5-volt supply operation for analog

and 5/3.3 volts for digital.

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Project Goals

Implementation By an adapter that convert voltage/current to/from the camera and the XUP board.

Capture a single frame and forward it to DDR SDRAM using Virtex II PRO.

© 2004 Xilinx, Inc. All Rights Reserved

M4088

ov5017

External power supply

Biases and data to/from adapter (from there to XUP)

Adapter

XUP

Vertex II PRO

Biases and data to/from adapter (from there to the camera)

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Stages of the ProjectDive in spec of Virtex II pro & CCD

cameraGet familiar with development tools

(EDK , VHDL…)Submit mid term report Implementing the connection between

the devices Presentation of the adapterSubmit final report

© 2004 Xilinx, Inc. All Rights Reserved

Schedule29 May – middle term report – include pin to

pin scheme28 June - perform first tests to the adapter29 June – Presentation of the Adapter