© 2004 Xilinx, Inc. All Rights Reserved© 2004 Xilinx, Inc. All Rights Reserved

Implemented by :Alon Ben Shalom Yoni Landau

Project supervised by: Mony Orbach

High speed digital systems laboratory

Technion - Israel institute of technologydepartment of Electrical Engineering

A single semester ProjectA single semester Project

Mid Semester PresentationMid Semester Presentation

Spring 2007

© 2004 Xilinx, Inc. All Rights Reserved

AgendaProject GoalsBlock DiagramTasks accomplishedStages of the projectSchedule

© 2004 Xilinx, Inc. All Rights Reserved

Project Goals

Please note that project goal was changed:1.We believe that it is possible to store one frame in BRAM as originally stated (instead of storing the data in SDRAM)2.There is no need for voltage transformation, both the XUP and camera work with same standard (TTL)

•Capture a single frame and forward it to BRAM using Virtex II PRO.•Retrieve data from BRAM to PC

© 2004 Xilinx, Inc. All Rights Reserved

M4088

ov5017

External power supply

Data to/from adapter (from there to XUP)

Adapter

XUP

Vertex II PRO

Data to/from adapter (from there to the camera)

Block Diagram

© 2004 Xilinx, Inc. All Rights Reserved

M4088 is a ¼ ” Monochrome digital camera

The M4088 digital camera is based on OV5017 CCD chip manufactured by OmniVision.Chip Interface : M4088 camera module.

M4088

© 2004 Xilinx, Inc. All Rights Reserved

Tasks accomplished Counter Implementation

1. Design of a custom IPIF that contains a 32bit register connected to OBP BUS.

2. Implementation of C code that initializes the register to a certain value and increase the value by 1 in a loop.

BRAM control

1. Write to memory2. Read from memory

© 2004 Xilinx, Inc. All Rights Reserved

1. Initialize the register2. Read the value in the register3. Add 14. Save result in the register5. If not done go to step 2

Pseudo code and animation

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Actual EDK scheme

Our IP

OBP2PLB

BRIDGE

Processor

PLB OPB

© 2004 Xilinx, Inc. All Rights Reserved

Stages of the ProjectDive in spec of Virtex II pro & CCD cameraGet familiar with development tools (EDK , VHDL…)Submit mid term report Design the interface Connector (much less resource

since we don’t need to convert voltage)Understand how to control the low speed

connectors (timing, voltage)Write VHDL and C codeIntegrate all components to achieve a working

systemSubmit final report

© 2004 Xilinx, Inc. All Rights Reserved

Schedule12-26/6

Understand how to control the low speed connectors in pin resolution

Create a pin to pin diagram27/6 – 10/7

Build an interface connection between camera & SOPC (in background)

Implement main VHDL and C code11/7 – 2/8

Debug HW/SW – making all players work out together