Cortex-M3
Revision: r0p0
Technical Reference Manual
Copyright 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337B
Cortex-M3Technical Reference Manual
Copyright 2005, 2006 ARM Limited. All rights reserved.
Release Information
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This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
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The information in this document is Final (information on a developed product).
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http://www.arm.com
Change History
Date Issue Confidentiality Change
15 December 2005 A Confidential First Release
13 January 2006 B Non-Confidential Confidentiality status amended
ii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
ContentsCortex-M3 Technical Reference Manual
PrefaceAbout this manual ...................................................................................... xviiiFeedback ................................................................................................... xxiii
Chapter 1 Introduction1.1 About the processor .................................................................................... 1-21.2 Components of the processor ..................................................................... 1-41.3 Configurable options ................................................................................. 1-121.4 Instruction set summary ............................................................................ 1-13
Chapter 2 Programmers Model2.1 About the programmers model ................................................................... 2-22.2 Privileged access and User access ............................................................ 2-32.3 Registers ..................................................................................................... 2-42.4 Data types ................................................................................................. 2-102.5 Memory formats ........................................................................................ 2-112.6 Instruction set ............................................................................................ 2-13
Chapter 3 System Control3.1 Summary of processor registers ................................................................. 3-2
ARM DDI 0337B Copyright 2005, 2006 ARM Limited. All rights reserved. iii
Contents
Chapter 4 Memory Map4.1 About the memory map .............................................................................. 4-24.2 Bit-banding ................................................................................................. 4-54.3 ROM memory table .................................................................................... 4-8
Chapter 5 Exceptions5.1 About the exception model ......................................................................... 5-25.2 Exception types .......................................................................................... 5-35.3 Exception priority ........................................................................................ 5-55.4 Privilege and stacks .................................................................................... 5-85.5 Pre-emption .............................................................................................. 5-105.6 Tail-chaining ............................................................................................. 5-135.7 Late-arriving .............................................................................................. 5-145.8 Exit ............................................................................................................ 5-165.9 Resets ...................................................................................................... 5-195.10 Exception control transfer ......................................................................... 5-235.11 Setting up multiple stacks ......................................................................... 5-245.12 Abort model .............................................................................................. 5-265.13 Activation levels ........................................................................................ 5-315.14 Flowcharts ................................................................................................ 5-33
Chapter 6 Clocking and Resets6.1 Cortex-M3 clocking ..................................................................................... 6-26.2 Cortex-M3 resets ........................................................................................ 6-46.3 Cortex-M3 reset modes .............................................................................. 6-5
Chapter 7 Power Management7.1 About power management ......................................................................... 7-27.2 System power management ....................................................................... 7-3
Chapter 8 Nested Vectored Interrupt Controller8.1 About the NVIC ........................................................................................... 8-28.2 NVIC programmers model ......................................................................... 8-38.3 Level versus pulse interrupts .................................................................... 8-39
Chapter 9 Memory Protection Unit9.1 About the MPU ........................................................................................... 9-29.2 MPU programmers model .......................................................................... 9-39.3 MPU access permissions ......................................................................... 9-149.4 MPU aborts ............................................................................................... 9-169.5 Updating an MPU region .......................................................................... 9-179.6 Interrupts and updating the MPU .............................................................. 9-20
Chapter 10 Core Debug10.1 About core debug ..................................................................................... 10-2
iv Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337B
Contents
10.2 Core debug registers ................................................................................ 10-310.3 Core debug access example .................................................................. 10-1210.4 Using application registers in core debug ............................................... 10-13
Chapter 11 System Debug11.1 About system debug ................................................................................. 11-211.2 System Debug Access .............................................................................. 11-311.3 System debug programmers model ......................................................... 11-511.4 Flash Patch and Breakpoint ...................................................................... 11-611.5 Data Watchpoint and Trace .................................................................... 11-1311.6 Instrumentation Trace Macrocell ............................................................. 11-2811.7 AHB Access Port .................................................................................... 11-37
Chapter 12 Debug Port12.1 About the Debug Port ............................................................................... 12-212.2 JTAG-DP ................................................................................................... 12-312.3 SW-DP .................................................................................................... 12-2012.4 Common Debug Port (DP) features ........................................................ 12-4112.5 Debug Port Programmers Model ............................................................ 12-47
Chapter 13 Trace Port Interface Unit13.1 About the Trace Port Interface Unit .......................................................... 13-213.2 TPIU registers ........................................................................................... 13-8
Chapter 14 Bus Interface14.1 About bus interfaces ................................................................................. 14-214.2 ICode bus interface ..........................................................................
