Cost-Effective A/D Flash MCU with EEPROM - Home - · PDF fileCost-Effective A/D Flash MCU with EEPROM Pin Descriptions With the exception of the power pins, all pins on these devices

Cost-Effective A/D Flash MCU with EEPROM

HT66F007/HT66F008

Revision: V1.50 Date: ��st �� 01��st �� 01�

Rev. 1.50 � ��st �� 01� Rev. 1.50 3 ��st �� 01�

HT66F007/HT66F008Cost-Effective A/D Flash MCU with EEPROM


Table of Contents

Features ............................................................................................................ 6CPU Feat�res ......................................................................................................................... 6Peripheral Feat�res ................................................................................................................. 6

General Description ........................................................................................ 7Block Diagram .................................................................................................. 7Selection Table ................................................................................................. 8Pin Assignment ................................................................................................ 8Pin Descriptions .............................................................................................. 9Absolute Maximum Ratings .......................................................................... 10D.C. Characteristics ....................................................................................... 10A.C. Characteristics ....................................................................................... 12A/D Converter Electrical Characteristics ..................................................... 14Comparator Electrical Characteristics ........................................................ 15Power on Reset Electrical Characteristics .................................................. 15System Architecture ...................................................................................... 15

Clockin� and Pipelinin� ......................................................................................................... 16Pro�ram Co�nter ................................................................................................................... 1�Stack ..................................................................................................................................... 1��rithmetic and Lo�ic Unit – �LU ........................................................................................... 18

Flash Program Memory ................................................................................. 18Str�ct�re ................................................................................................................................ 18Special Vectors ..................................................................................................................... 1�Look-�p Table ........................................................................................................................ 1�Table Pro�ram Example ........................................................................................................ 1�In Circ�it Pro�rammin� ......................................................................................................... �0On-Chip Deb�� S�pport – OCDS ......................................................................................... �1

RAM Data Memory ......................................................................................... 22Str�ct�re ................................................................................................................................ ��

Special Function Register Description ........................................................ 23Indirect �ddressin� Re�isters – I�R0� I�R1 ......................................................................... �3Memory Pointers – MP0� MP1 .............................................................................................. �3Bank Pointer – BP ................................................................................................................. �4�cc�m�lator – �CC ............................................................................................................... �4Pro�ram Co�nter Low Re�ister – PCL .................................................................................. �4Look-�p Table Re�isters – TBLP� TBHP� TBLH ..................................................................... �4Stat�s Re�ister – ST�TUS .................................................................................................... �5

EEPROM Data Memory .................................................................................. 26EEPROM Data Memory Str�ct�re ........................................................................................ �6EEPROM Re�isters .............................................................................................................. �6

Rev. 1.50 � ��st �� 01� Rev. 1.50 3 ��st �� 01�



Readin� Data from the EEPROM ........................................................................................ ��Writin� Data to the EEPROM ................................................................................................ ��Write Protection ..................................................................................................................... ��EEPROM Interr�pt ................................................................................................................ ��Pro�rammin� Considerations ................................................................................................ 30Pro�rammin� Examples ........................................................................................................ 30

Oscillators ...................................................................................................... 31Oscillator Overview ............................................................................................................... 31System Clock Configurations ................................................................................................ 31External Crystal/Ceramic Oscillator – HXT ........................................................................... 3�Internal RC Oscillator – HIRC ............................................................................................... 33Internal 3�kHz Oscillator – LIRC ........................................................................................... 33S�pplementary Oscillator ...................................................................................................... 33

Operating Modes and System Clocks ......................................................... 33System Clocks ...................................................................................................................... 33System Operation Modes ...................................................................................................... 35Control Re�ister .................................................................................................................... 36Fast Wake-�p ........................................................................................................................ 3�Operatin� Mode Switchin� ................................................................................................... 38Standby C�rrent Considerations ........................................................................................... 4�Wake-�p ................................................................................................................................ 4�Pro�rammin� Considerations ................................................................................................ 43

Watchdog Timer ............................................................................................. 44Watchdo� Timer Clock So�rce .............................................................................................. 44Watchdo� Timer Control Re�ister ......................................................................................... 44Watchdo� Timer Operation ................................................................................................... 45

Reset and Initialisation .................................................................................. 46Reset F�nctions .................................................................................................................... 46Reset Initial Conditions ......................................................................................................... 4�

Input/Output Ports ......................................................................................... 51P�ll-hi�h Resistors ................................................................................................................ 51Port � Wake-�p ..................................................................................................................... 5�I/O Port Control Re�isters ..................................................................................................... 5�Special Pin Control ................................................................................................................ 53Pin-remappin� F�nctions ...................................................................................................... 53I/O Pin Str�ct�res .................................................................................................................. 55Pro�rammin� Considerations ................................................................................................ 56

Timer Modules – TM ...................................................................................... 56Introd�ction ........................................................................................................................... 56TM Operation ........................................................................................................................ 5�TM Clock So�rce ................................................................................................................... 5�TM Interr�pts ......................................................................................................................... 5�TM External Pins ................................................................................................................... 5�

Rev. 1.50 4 ��st �� 01� Rev. 1.50 5 ��st �� 01�



TM Inp�t/O�tp�t Pin Control Re�ister ................................................................................... 58Pro�rammin� Considerations ................................................................................................ 60

Compact Type TM – CTM .............................................................................. 61Compact Type TM Operation ................................................................................................ 61Compact Type TM Re�ister Description................................................................................ 6�Compact Type TM Operatin� Modes .................................................................................... 65

Standard Type TM – STM .............................................................................. 71Standard Type TM Operation ................................................................................................ �1Standard Type TM Re�ister Description ............................................................................... ��Standard Type TM Operatin� Modes .................................................................................... �5

Analog to Digital Converter .......................................................................... 82�/D Overview ........................................................................................................................ 8��/D Converter Re�ister Description ...................................................................................... 8��/D Converter Data Re�isters – �DRL� �DRH ..................................................................... 83�/D Converter Control Re�isters – �DCR0� �DCR1� �CER ................................................. 83�/D Operation ....................................................................................................................... 86�/D Inp�t Pins ....................................................................................................................... 8�S�mmary of �/D Conversion Steps ....................................................................................... 8�Pro�rammin� Considerations ................................................................................................ 8��/D Transfer F�nction ........................................................................................................... 8��/D Pro�rammin� Examples ................................................................................................. �0

Comparator .................................................................................................... 92Comparator Operation .......................................................................................................... ��Comparator Re�ister ............................................................................................................. ��Comparator Interr�pt ............................................................................................................. �3Pro�rammin� Considerations ................................................................................................ �3

Interrupts ........................................................................................................ 94Interr�pt Re�isters ................................................................................................................. �4Interr�pt Operation ................................................................................................................ �8External Interr�pt ................................................................................................................... ��Comparator Interr�pt ........................................................................................................... 100M�lti-f�nction Interr�pt ........................................................................................................ 100�/D Converter Interr�pt ....................................................................................................... 100Time Base Interr�pts ........................................................................................................... 100EEPROM Interr�pt .............................................................................................................. 10�TM Interr�pts ....................................................................................................................... 10�Interr�pt Wake-�p F�nction ................................................................................................. 10�Pro�rammin� Considerations .............................................................................................. 10�

Configuration Options ................................................................................. 103Application Circuits ..................................................................................... 103Instruction Set .............................................................................................. 104

Instr�ction ............................................................................................................................ 104Instr�ction Timin� ................................................................................................................ 104

Rev. 1.50 4 ��st �� 01� Rev. 1.50 5 ��st �� 01�



Movin� and Transferrin� Data ............................................................................................. 104�rithmetic Operations .......................................................................................................... 104Lo�ical and Rotate Operations ............................................................................................ 105Branches and Control Transfer ........................................................................................... 105Bit Operations ..................................................................................................................... 105Table Read Operations ....................................................................................................... 105Other Operations ................................................................................................................. 105

Instruction Set Summary ............................................................................ 106Table Conventions ............................................................................................................... 106

Instruction Definition ................................................................................... 108Package Information ....................................................................................117

8-pin DIP (300mil) O�tline Dimensions ................................................................................1188-pin SOP (150mil) O�tline Dimensions ..............................................................................11�10-pin MSOP O�tline Dimensions ...................................................................................... 1�016-pin NSOP (150mil) O�tline Dimensions ......................................................................... 1�1

Rev. 1.50 6 ��st �� 01� Rev. 1.50 � ��st �� 01�



Features

CPU Features• OperatingVoltage

♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=16MHz:3.3V~5.5V♦ fSYS=20MHz:4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• ThreeOscillators♦ ExternalCrystal--HXT♦ InternalRC--HIRC♦ Internal32kHz--LIRC

• Fullyintergratedinternal4MHz,8MHz,12MHzoscillatorrequiresnoexternalcomponents

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 8-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:2K×16~4K×16

• RAMDataMemory:160×8~256×8

• TrueEEPROMMemory:512×8~1024×8

• WatchdogTimerfunction

• 8bidirectionalI/Olines

• Onepin-sharedexternalinterrupt

• MultipleTimerModulefortimemeasure,comparematchoutput,PWMoutputfunctionorsinglepulseoutputfunction

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• 5-channel12-bitresolutionA/Dconverter

• SingleComparatorFunction

• Lowvoltageresetfunction

• PackageTypes:8-pinDIP/SOPand10-pinMSOP

• Flashprogrammemorycanbere-programmedupto100,000times

• Flashprogrammemorydataretention>10years

• TrueEEPROMdatamemorycanbere-programmedupto1,000,000times

• TrueEEPROMdatamemorydataretention>10years

Rev. 1.50 6 ��st �� 01� Rev. 1.50 � ��st �� 01�



General Description ThesedevicesareFlashMemorytype8-bithighperformanceRISCarchitecturemicrocontrollers.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures, thesedevicesalsoincludeawide rangeof functionsandfeatures.Othermemory includesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeaturesincludeamulti-channel12-bitA/Dconverterandacomparatorfunctions.Multipleandextremely flexibleTimerModulesprovide timing,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

AfullchoiceofHXT,HIRCandLIRCoscillatorfunctionsareprovidedincludingafullyintegratedsystemoscillatorwhichrequiresnoexternalcomponents for its implementation.Theability tooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontrolleroperationandminimizepowerconsumption.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethatthedeviceswillfindexcellentuseinapplicationssuchaselectronicmetering,environmentalmonitoring,handheldinstruments,householdappliances,electronicallycontrolledtools,motordrivinginadditiontomanyothers.

Block Diagram

8-bitRISCMCUCore

16-bit STM×1

FlashPro�ram Memory

EEPROMData

Memory

Flash/EEPROMPro�rammin� Circ�itry

R�MData

Memory

TimeBases

Watchdo� Timer

Interr�ptController

ResetCirc�it

ExternalOscillator

Low Volta�eReset

10-bit CTM×�I/O

1�-bit �/DConverter

Comparator

Internal RCOscillators

Rev. 1.50 8 ��st �� 01� Rev. 1.50 � ��st �� 01�



Selection TableMostfeaturesarecommonto thesedevices, themainfeaturesdistinguishing themareMemorycapacity.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. VDD ROM RAM EEPROM I/O Ext.Int. A/D Timer

ModuleTimeBase Stack Package

HT66F00� �.�V~5.5V �K×16 160×8 51�×8 8 1 1�-bit×5

10-bit CTM×�16-bit

STM×1

� 8 8DIP/SOP10MSOP

HT66F008 �.�V~5.5V 4K×16 �56×8 10�4×8 8 1 1�-bit×5

10-bit CTM×�16-bit

STM×1

� 8 8DIP/SOP10MSOP

Pin Assignment

� � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � � � � � � ��

� � � �

� � � � � � � � � � � � � � � ��

� � � � � �

��

� ��

��

� � � � � � � � � � � � � � � � � � � � � � � � � ��

� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � ��

� � � � � � � � � � � � � � � ��

� � � � �

� � � � � � � � � � � � � � � � ��

��

��

� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � ��

� � � � � � � � � � � � � � ��

Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.2.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe“/”signcanbeusedforhigherpriority.

3.AVDD&VDDmeans theVDDandAVDDare thedoublebonding.VSS&AVSSmeans theVSSandAVSSarethedoublebonding.

Rev. 1.50 8 ��st �� 01� Rev. 1.50 � ��st �� 01�



Pin DescriptionsWiththeexceptionofthepowerpins,allpinsonthesedevicescanbereferencedbytheirPortname,e.g.PA0,PA1etc,whichrefertothedigitalI/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchas theAnalogtoDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

AsthePinDescriptiontableshowsthesituationforthepackagewiththemostpins,notallpinsinthetablewillbeavailableonsmallerpackagesizes.

Pin Name Function OP I/T O/T Pin-Shared Mapping

P�0~P�� General p�rpose I/O port � P�PUP�WU ST CMOS —

�N0~�N4 �/D Converter inp�t 0~4 �CER �N — P�0~P�3� P�5VREF �/D Converter reference volta�e inp�t �DCR1 �N — P�1INT External interr�pt PRM ST — P�5 or P�� or P�3 or P��TCK0 TM0 inp�t PRM ST — P�� or P�6TCK1 TM1 inp�t PRM ST — P�� or P�4 or P��TP0_0 TM0 I/O PRM ST CMOS P�0TP0_1 TM0 I/O PRM ST CMOS P�5 or P�1TP1_0 TM1 I/O PRM ST CMOS P�6 or P��TP1_1 TM1 I/O PRM ST CMOS P�4 TP�_0 TM� I/O PRM ST CMOS P��OSC1 HXT pin CO HXT — P�6OSC� HXT pin CO — HXT P�5CP Comparator positive inp�t

CPC�N — P�0

CN Comparator ne�ative inp�t �N — P�1CX Comparator o�tp�t — CMOS P��ICPCK ICP clock inp�t — ST — P�1ICPD� ICP data inp�t/o�tp�t — ST CMOS P�0VDD Positive power s�pply* — PWR — —�VDD �/D Converter power s�pply* — PWR — —VSS Ne�ative power s�pply� �ro�nd** — PWR — —�VSS �/D Converter �ro�nd** — PWR — —The following pins are only for the HT66V007/HT66V008OCDSCK On-chip deb�� s�pport clock pin — ST — —OCDSD� On-chip deb�� s�pport data/address pin — ST CMOS —

Legend::I/T:InputtypeO/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:PowerCO:ConfigurationoptionST:SchmittTriggerinputCMOS:CMOSoutputAN:AnalogsignalHXT:Highfrequencyctystaloscillator*:VDDisthedevicepowersupplywhileAVDDistheADCpowersupply.TheAVDDpinisbondedtogetherinternallywithVDD.

**:VSSisthedevicegroundpinwhileAVSSistheADCgroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.

Rev. 1.50 10 ��st �� 01� Rev. 1.50 11 ��st �� 01�



Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal..................................................................................................................................-100mAIOLTotal................................................................................................................................... 100mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=�5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD1Operatin� Volta�e(HXT) —

fSYS=8MHz �.� — 5.5 VfSYS=1�MHz �.� — 5.5 VfSYS=16MHz 3.3 — 5.5 VfSYS=�0MHz 4.5 — 5.5 V

VDD�Operatin� Volta�e(HIRC) —

fSYS=4MHz �.� — 5.5 VfSYS=8MHz �.� — 5.5 VfSYS=1�MHz �.� — 5.5 V

IDD1

Operatin� C�rrent�Normal Mode� fSYS=fH(HXT)

3VNo load� fH=4MHz� �DC off� WDT enable

— 0.6 0.� m�5V — 1.8 �.� m�3V

No load� fH=8MHz� �DC off� WDT enable— 1.1 1.� m�

5V — �.� 4.4 m�3V

No load� fH=1�MHz� �DC off� WDT enable— 1.6 �.5 m�

5V — 4.1 6.� m�3.3V

No load� fH=16MHz� �DC off� WDT enable— �.0 3.0 m�

5V — 5.� �.8 m�5V No load� fH=�0MHz� �DC off� WDT enable — 6.4 �.6 m�

IDD�

Operatin� C�rrent�Normal Mode� fSYS=fH(HIRC)

3VNo load� fH=4MHz� �DC off� WDT enable

— 0.6 0.� m�5V — 1.8 �.� m�3V

No load� fH=8MHz� �DC off� WDT enable— 1.1 1.� m�

5V — �.� 4.4 m�3V

No load� fH=1�MHz� �DC off� WDT enable— 1.6 �.5 m�

5V — 4.1 6.� m�

Rev. 1.50 10 ��st �� 01� Rev. 1.50 11 ��st �� 01�





IDD3

Operatin� C�rrent�Normal Mode� fH=1�MHz (HIRC)

3VNo load� fSYS=fH/�� DC off� WDT enable

— 1.� �.4 m�5V — �.6 4.4 m�3V

No load� fSYS=fH/4� �DC off� WDT enable— 1.6 �.4 m�

5V — �.4 4.0 m�3V

No load� fSYS=fH/8� �DC off� WDT enable— 1.5 �.� m�

5V — �.� 3.6 m�3V

No load� fSYS=fH/16� �DC off� WDT enable— 1.4 �.0 m�

5V — �.0 3.� m�3V

No load� fSYS=fH/3�� DC off� WDT enable— 1.3 1.8 m�

5V — 1.8 �.8 m�3V

No load� fSYS=fH/64� �DC off� WDT enable— 1.� 1.6 m�

5V — 1.6 �.4 m�

IDD4

Operatin� C�rrent�Normal Mode� fH=1�MHz (HXT)

3VNo load� fSYS=fH/�� DC off� WDT enable

— 0.�0 1.50 m�5V — �.50 3.�5 m�3V

No load� fSYS=fH/4� �DC off� WDT enable— 0.� 1.0 m�

5V — �.0 3.0 m�3V

No load� fSYS=fH/8� �DC off� WDT enable— 0.6 0.� m�

5V — 1.6 �.4 m�3V

No load� fSYS=fH/16� �DC off� WDT enable— 0.50 0.�5 m�

5V — 1.50 �.�5 m�3V

No load� fSYS=fH/3�� DC off� WDT enable— 0.4� 0.�4 m�

5V — 1.45 �.18 m�3V

No load� fSYS=fH/64� �DC off� WDT enable— 0.4� 0.�1 m�

5V — 1.40 �.10 m�

IDD5

Operatin� C�rrent�Slow Mode� fSYS=fL=LIRC�fSUB=LIRC

3V No load� fSYS=LIRC� �DC off� WDT enable�LVR disable

— 10 �0 μA

5V — 30 50 μA

IDD5�

Operatin� C�rrent�Slow Mode� fSYS=fL=LIRC�fSUB=LIRC

3V No load� fSYS=LIRC� �DC off� WDT enable�LVR enable

— 40 60 μA

5V — �0 135 μA

IIDLE01IDLE0 Mode Standby C�rrent (LIRC on)

3VNo load� �DC off� WDT enable

— 1.3 3.0 μA5V — �.� 5.0 μA

IIDLE11IDLE1 Mode Standby C�rrent (HXT)

3V No load� �DC off� WDT enable� fSYS=4MHz on

— 0.4 0.8 m�5V — 0.8 1.6 m�

IIDLE11�IDLE1 Mode Standby C�rrent (HIRC)


— 0.4 0.8 m�5V — 0.8 1.6 m�

IIDLE1�IDLE1 Mode Standby C�rrent (HXT)


— 0.5 1.0 m�5V — 1.0 �.0 m�

IIDLE1��IDLE1 Mode Standby C�rrent (HIRC)


— 0.8 1.6 m�5V — 1.0 �.0 m�


3V No load� �DC off� WDT enable� fSYS=1�MHz on

— 0.6 1.� m�5V — 1.� �.4 m�

IIDLE13�IDLE1 Mode Standby C�rrent (HIRC)

3V No load� �DC off� WDT enable� fSYS=1�MHz on

— 0.6 1.� m�5V — 1.� �.4 m�


3.3V No load� �DC off� WDT enable� fSYS=16MHz on

— 1.0 �.0 m�5V — �.0 4.0 m�

IIDLE15IDLE1 Mode Standby C�rrent (HXT) 5V No load� �DC off� WDT enable�

fSYS=�0MHz on — �.5 5.0 m�

Rev. 1.50 1� ��st �� 01� Rev. 1.50 13 ��st �� 01�





ISLEEP0SLEEP0 Mode Standby C�rrent (LIRC off)

3V No load� �DC off� WDT disable� LVR disable

— 0.� 0.8 μA5V — 0.5 1.0 μA

ISLEEP1SLEEP1 Mode Standby C�rrent (LIRC on)

3V No load� �DC off� WDT enable� LVR disable

— 1.3 5.0 μA5V — �.� 10 μA

VIL1Inp�t Low Volta�e for I/O Ports or Inp�t Pins

5V — 0 — 1.5 V— — 0 — 0.�VDD V

VIH1Inp�t Hi�h Volta�e for I/O Ports or Inp�t Pins

5V — 3.5 — 5.0 V— — 0.8VDD — VDD V

VIL�TTL Inp�t Low Volta�e for P�� P�5� P�6 and P�� 5V 5V±10% 0 — 0.8 V

VIH�TTL Inp�t Hi�h Volta�e for P�� P�5� P�6 and P�� 5V 5V±10% �.0 — VDD V

VLVR Low Volta�e Reset Volta�e —

LVR enable� �.1V option

-5%×Typ.

�.1

+5%×Typ.

VLVR enable� �.55V option �.55 VLVR enable� 3.15V option 3.15 VLVR enable� 3.8V option 3.8 V

ILVR�dditional Power Cons�mption if LVR is �sed

3VLVR disable → LVR enable

— 30 45 μA5V — 60 �0 μA

IOL I/O Port Sink C�rrent3V VOL=0.1VDD 8 16 — m�5V VOL=0.1VDD 16 3� — m�

IOH I/O Port So�rce C�rrent3V VOH=0.�VDD -3.�5 -�.5 — m�5V VOH=0.�VDD -�.5 -15 — m�

RPHP�ll-hi�h Resistance for I/O Ports

3V — �0 60 100 kΩ5V — 10 30 50 kΩ

IOCDS

Operatin� C�rrent� Normal Mode� fSYS=fH (HIRC) (for OCDS EV testin�� connect to an e-Link)

3V No load� fH=4MHz� �DC off� WDT enable — 0.� 1.0 m�

A.C. CharacteristicsTa=�5°C



fCPU Operatin� Clock

�.�V~5.5V

─

DC ─ 8 MHz�.�V~5.5V DC ─ 1� MHz3.3V~5.5V DC ─ 16 MHz4.5V~5.5V DC ─ �0 MHz

fSYS System clock (HXT)

�.�V~5.5V

─

0.4 ─ 8 MHz�.�V~5.5V 0.4 ─ 1� MHz3.3V~5.5V 0.4 ─ 16 MHz4.5V~5.5V 0.4 ─ �0 MHz

Rev. 1.50 1� ��st �� 01� Rev. 1.50 13 ��st �� 01�





fHIRC System Clock (HIRC)

3V/5VTa=�5°C

-�% 4 +�% MHz3V/5V -�% 8 +�% MHz3V/5V -�% 1� +�% MHz3V/5V

Ta=0°C~�0°C-4% 4 +3% MHz

3V/5V -4% 8 +3% MHz3V/5V -4% 1� +3% MHz3V/5V

Ta=-40°C~85°C-�% 4 +�% MHz

3V/5V -�% 8 +�% MHz3V/5V -�% 1� +�% MHz

�.�V~4.0VTa=0°C~�0°C

-�% 4 +6% MHz3.0V~5.5V -5% 4 +1�% MHz�.�V~4.0V

Ta=0°C~�0°C-�% 8 +5% MHz

3.0V~5.5V -5% 8 +11% MHz�.�V~4.0V Ta=0°C~�0°C -10% 1� +10% MHz3.0V~5.5V Ta=0°C~�0°C -10% 1� +10% MHz�.�V~4.0V Ta=-40°C~85°C -1�% 4 +6% MHz3.0V~5.5V Ta=-40°C~85°C -8% 4 +1�% MHz�.�V~4.0V Ta=-40°C~85°C -1�% 8 +6% MHz3.0V~5.5V Ta=-40°C~85°C -8% 8 +1�% MHz�.�V~4.0V Ta=-40°C~85°C -13% 1� +13% MHz3.0V~5.5V Ta=-40°C~85°C -13% 1� +13% MHz�.�V~5.5V

Ta=-40°C~85°C-15% 4 +15% MHz

�.�V~5.5V -15% 8 +15% MHz�.�V~5.5V -15% 1� +15% MHz

fLIRC System Clock (LIRC)5V Ta=�5°C -10% 3� +10% kHz

�.�V~5.5V Ta=-40°C~85°C -50% 3� +60% kHztTIMER TCKn Inp�t P�lse Width ─ ─ 0.3 ─ ─ μstINT Interr�pt P�lse Width ─ ─ 10 ─ ─ μstLVR Low Volta�e Width to Reset ─ ─ 1�0 �40 480 μstSRESET Software Reset Width to Reset ─ ─ 45 �0 1�0 μstEERD EEPROM Read Time ─ ─ ─ � 4 tSYS

tEEWR EEPROM Write Time ─ ─ ─ � 4 ms

tSSTSystem Start-�p Timer Period (Wake-�p from H�LT)

─ fSYS=HXT ─ 10�4 ─ tSYS

─ fSYS=HIRC ─ 15~16 ─ tSYS

─ fSYS=LIRC ─ 1~� ─ tSYS

tRSTD

System Reset Delay Time(Power On Reset� LVR reset� LVR S/W reset(LVRC)� WDT S/W reset(WDTC))

─ ─ �5 50 100 ms

System Reset Delay Time(WDT normal reset) ─ ─ 8.3 16.� 33.3 ms

Note:1.tSYS=1/fSYS

2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

Rev. 1.50 14 ��st �� 01� Rev. 1.50 15 ��st �� 01�



A/D Converter Electrical Characteristics

HT66F007 Ta=�5°C



�VDD �/D Converter Operatin� Volta�e ─ ─ �.� ─ 5.5 VV�DI �/D Converter Inp�t Volta�e ─ ─ 0 ─ VREF VVREF �/D Converter Reference Volta�e ─ ─ � ─ �VDD VVBG Reference Volta�e with B�ffer Volta�e ─ ─ -3% 1.�5 +3% V

DNL Differential Non-linearity�.�V~�.�V VREF=�VDD=VDD� t�DCK=8μs — ±15 — LSB�.�V~5.5V VREF=�VDD=VDD� t�DCK=0.5μs -3 ─ +3 LSB

INL Inte�ral Non-linearity�.�V~�.�V VREF=�VDD=VDD� t�DCK=8μs — ±16 — LSB�.�V~5.5V VREF=�VDD=VDD� t�DCK=0.5μs -4 ─ +4 LSB

I�DC�dditional Power Cons�mption if �/D Converter is �sed

3V No load (t�DCK=0.5μs) ─ 0.� 1.35 m�5V No load (t�DCK=0.5μs) ─ 1.� 1.8 m�

IBG�dditional Power Cons�mption if VBG Reference with B�ffer is �sed ─ ─ ─ �00 300 μA

t�DCK �/D Converter Clock Period�.�V~�.�V ─ 8 — 10 μs�.�V~5.5V ─ 0.5 ─ 10 μs

t�DC�/D Conversion Time (Incl�de Sample and Hold Time) ─ 1�-bit �/D converter ─ 16 ─ t�DCK

t�DS �/D Converter Samplin� Time ─ ─ ─ 4 ─ t�DCK

tON�ST �/D Converter On-to-Start Time ─ ─ � ─ ─ μstBGS VBG T�rn on Stable Time ─ ─ �00 ─ ─ μs

HT66F008 Ta=�5°C



�VDD �/D Converter Operatin� Volta�e ─ ─ �.� ─ 5.5 VV�DI �/D Converter Inp�t Volta�e ─ ─ 0 ─ VREF VVREF �/D Converter Reference Volta�e ─ ─ � ─ �VDD VVBG Reference Volta�e with B�ffer Volta�e ─ ─ -3% 1.�5 +3% V

DNL Differential Non-linearity ─ VREF=VDD� t�DCK=0.5μs, Ta=-40°C~85°C -3 ─ +3 LSB

INL Inte�ral Non-linearity ─ VREF=VDD� t�DCK=0.5μs, Ta=-40°C~85°C -4 ─ +4 LSB

I�DC�dditional Power Cons�mption if �/D Converter is �sed

�.�V No load (t�DCK=0.5μs) ─ 1.0 �.0 m�3V No load (t�DCK=0.5μs) 1.0 �.0 m�5V No load (t�DCK=0.5μs) ─ 1.5 3.0 m�

IBG�dditional Power Cons�mption if VBG Reference with B�ffer is �sed ─ ─ ─ �00 300 μA

t�DCK �/D Converter Clock Period ─ ─ 0.5 ─ 10 μs

t�DC�/D Conversion Time (Incl�de Sample and Hold Time) ─ 1�-bit �/D converter ─ 16 ─ t�DCK

t�DS �/D Converter Samplin� Time ─ ─ ─ 4 ─ t�DCK

tON�ST �/D Converter On-to-Start Time ─ ─ � ─ ─ μstBGS VBG T�rn on Stable Time ─ ─ �00 ─ ─ μs

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Comparator Electrical CharacteristicsTa=25°C



— Comparator operatin� volta�e — — �.� — 5.5 V

ICM Comparator operatin� c�rrent3V

—— 50 �5 μA

5V — 85 130 μAVCMPOS Comparator inp�t offset volta�e 5V — -10 — +10 mVVHYS Hysteresis width 5V — �0 40 60 mVVCM Comparator common mode volta�e ran�e — — VSS — VDD-1.4 V�OL Comparator open loop �ain — — 60 80 — dBtPD Comparator response time — With 100mV overdrive (Note) — 300 600 ns

Note:MeasuredwithcomparatoroneinputpinatVCM=(VDD-1.4)/2whiletheotherpininputtransitionfromVSSto(VCM+100mV)orfromVDDto(VCM-100mV).

Power on Reset Electrical CharacteristicsTa=25°C



VPOR VDD Start Volta�e to Ens�re Power-on Reset ─ ─ ─ ─ 100 mVRRVDD VDD Risin� Rate to Ens�re Power-on Reset ─ ─ 0.035 ─ ─ V/ms

tPORMinim�m Time for VDD Stays at VPOR to Ens�re Power-on Reset ─ ─ 1 ─ ─ ms

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Rev. 1.50 16 ��st �� 01� Rev. 1.50 1� ��st �� 01�



Clocking and PipeliningThemainsystemclock,derivedfromeitheraHXT,HIRCorLIRCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

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System Clock and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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Instruction Fetching

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Program CounterDuringprogramexecution, theProgramCounterisusedtokeeptrackof theaddressof thenextinstruction tobeexecuted. It isautomatically incrementedbyoneeach timean instruction isexecutedexceptforinstructions,suchas“JMP”or“CALL”thatdemandajumptoanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecutinginstructionsrequiringjumpstonon-consecutiveaddressessuchasajumpinstruction,asubroutinecall,interruptorreset,etc.,themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Program Counter High byte PCL RegisterHT66F00� PC10~PC8 PCL�~PCL0HT66F008 PC11~PC8 PCL�~PCL0

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Rev. 1.50 18 ��st �� 01� Rev. 1.50 1� ��st �� 01�



Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrement:INCA,INC,DECA,DEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthesedevicestheProgramMemory isFlash type,whichmeans itcanbeprogrammedandre-programmedalargenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusing theappropriateprogramming tools, theseFlashdevicesofferusers the flexibility toconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×16to4K×16bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory, isaddressedbyaseparatetablepointerregister.

Device CapacityHT66F00� �K×16HT66F008 4K×16

000H004H

0�4H

�FFH

Reset

Interr�pt Vector

16 bits

Reset

16 bitsFFFH

HT66F007 HT66F008

Interr�ptVector

Program Memory Structure

Rev. 1.50 18 ��st �� 01� Rev. 1.50 1� ��st �� 01�



Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reserved foruseby thedevice reset forprograminitialisation.Afteradevice reset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

Last Pa�e or TBHP Re�ister

�ddress

TBLP Re�ister

Data16 bits

Pro�ram Memory

Re�ister TBLH User Selected Re�ister

Hi�h Byte Low Byte

Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“700H”whichreferstothestartaddressofthelastpagewithinthe2KwordsProgramMemoryoftheHT66F007.Thetablepointerissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“706H”or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or present pagemov a,07h ; initialise high table pointermov tbhp,a::tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “706H” transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address “705H” transferred to tempreg2 and TBLH in this ; example the data “1AH” is transferred to tempreg1 and data “0FH” to ; register tempreg2::org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh: :

In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Write Pins MCU Programming Pins FunctionICPD� P�0 Pro�rammin� Serial Data/�ddressICPCK P�1 Pro�rammin� Serial ClockVDD VDD Power S�pplyVSS VSS Gro�nd

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandground.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicesarebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

On-Chip Debug Support – OCDSTherearetwoEVchipsnamedHT66V007andHT66V008whichareusedtoemulatetheHT66F007andHT66F008repectively.TheseEVchipdevicesalsoprovidean“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicesarealmostfunctionallycompatibleexceptfor the“On-ChipDebug”function.Userscanuse theEVchipdevicetoemulate therealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Addressinput/outputpinwhiletheOCDSCKpinistheOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription,refertothecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSD� OCDSD� On-chip Deb�� S�pport Data/�ddress inp�t/o�tp�tOCDSCK OCDSCK On-chip Deb�� S�pport Clock inp�t

VDD VDD Power S�pplyGND VSS Gro�nd

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



RAM Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevices.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforthedevicesistheaddress00H.

Device RAM Address

HT66F00�Special P�rpose Bank0: 00H~3FH

Bank1: 00H~40H (EEC in 40H)General P�rpose: 160×8 Bank0: 40H~DFH

HT66F008Special P�rpose Bank0: 00H~40H

Bank1: 00H~40H (EEC in 40H)

General P�rpose: �56×8 Bank0: 80H~FFHBank1: 80H~FFH

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Special Purpose Data Memory Structure

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbymp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

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Bank Pointer – BPForthesedevices, theDataMemoryisdividedintotwobanks,Bank0andBank1.SelectingtherequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

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Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVisset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

STATUS Register

Bit 7 6 5 4 3 2 1 0Name — — TO PDF OV Z �C CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 × × × ×

"×" �nknownBit7~6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

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Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

EEPROM Data MemoryOneofthespecialfeaturesinthedevicesistheirinternalEEPROMDataMemory.EEPROM,whichstandsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatileformofmemory,withdataretentionevenwhenitspowersupply is removed.Byincorporatingthiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproduct identificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithintheproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityvaries from512×8 to1024×8bits.Unlike theProgramMemoryandRAMDataMemory, theEEPROMDataMemory isnotdirectlymappedand isthereforenotdirectlyaccessible in thesamewayas theother typesofmemory.ReadandWriteoperations to theEEPROMarecarriedout insinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

Device Capacity AddressHT66F00� 51�×8 000H~1FFHHT66F008 10�4×8 000H~3FFH

EEPROM RegistersFourregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregisters,EEAandEEAH,thedataregister,EEDandasinglecontrolregister,EEC.AsalltheEEA,EEAHandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

RegisterName

Bit

7 6 5 4 3 2 1 0EE� D� D6 D5 D4 D3 D� D1 D0

EE�H — — — — — — — D8EED D� D6 D5 D4 D3 D� D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Control Registers List – HT66F007

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RegisterName

Bit

7 6 5 4 3 2 1 0EE� D� D6 D5 D4 D3 D� D1 D0

EE�H — — — — — — D� D8EED D� D6 D5 D4 D3 D� D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Control Registers List – HT66F008

EEA Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 DataEEPROMaddressDataEEPROMaddressbit7~bit0

EEAH Register – HT66F007

Bit 7 6 5 4 3 2 1 0Name — — — — — — — D8R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 DataEEPROMaddress

DataEEPROMaddressbit8

EEAH Register – HT66F008

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 DataEEPROMaddress

DataEEPROMaddressbit9~bit8

EED Register


Bit7~0 DataEEPROMdataDataEEPROMdatabit7~bit0

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EEC Register

Bit 7 6 5 4 3 2 1 0Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

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Reading Data from the EEPROM ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAandEEAHregisters.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationiftheRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.TheapplicationprogramcanpolltheRDbittodeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustthenbeplacedintheEEAandEEAHregistersandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,in theEECregistermustfirstbesethightoenablethewritefunction.After this, theWRbit intheEECregistermustbe immediatelysethigh to initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbeforeimplementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.Notethatsetting theWRbithighwillnot initiateawritecycle if theWRENbithasnotbeenset.As theEEPROMwritecycle iscontrolledusingan internal timerwhoseoperation isasynchronous tomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.Theapplicationprogramcanthereforepoll theWRbit todeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided in severalways.After thedevicesarepowered-ontheWriteEnablebit in thecontrolregisterwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.IftheglobalandEEPROMinterruptsareenabledandthestackisnotfull,ajumptotheassociatedInterruptvectorwilltakeplace.WhentheinterruptisservicedtheEEPROMinterruptflagwillbeautomaticallyreset.MoredetailscanbeobtainedintheInterruptsection.

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Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrol registerexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.NotethatthedevicesshouldnotentertheIDLEorSLEEPmodeuntiltheEEPROMreadorwriteoperationistotallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples

Reading data from the EEPROM – polling methodMOVA,EEPROM_ADRES_H ;userdefinedhigh-byteaddressMOVEEAH,AMOVA,EEPROM_ADRES_L ;userdefinedlow-byteaddressMOVEEA,AMOVA,040H ;setupmemorypointerMP1MOVMP1,A ;MP1pointstoEECregisterMOVA,01H ;setupBankPointerMOVBP,ASETIAR1.1 ;setRDENbit,enablereadoperationsSETIAR1.0 ;startReadCycle-setRDbitBACK:SZIAR1.0 ;checkforreadcycleendJMPBACKCLRIAR1 ;disableEEPROMread/writeCLRBPMOVA,EED ;movereaddatatoregisterMOVREAD_DATA,A

Writing Data to the EEPROM – polling methodMOVA,EEPROM_ADRES_H ;userdefinedhigh-byteaddressMOVEEAH,AMOVA,EEPROM_ADRES_L ;userdefinedlow-byteaddressMOVEEA,AMOVA,EEPROM_DATA ;userdefineddataMOVEED,AMOVA,040H ;setupmemorypointerMP1MOVMP1,A ;MP1pointstoEECregisterMOVA,01H ;setupBankPointerMOVBP,ACLREMISETIAR1.3 ;setWRENbit,enablewriteoperationsSETIAR1.2 ;startWriteCycle-setWRbitSETEMIBACK:SZIAR1.2 ;checkforwritecycleendJMPBACKCLRIAR1 ;disableEEPROMread/writeCLRBP

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OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfortheWatchdogTimerandTimeBaseInterrupts.Anexternaloscillatorrequiringsomeexternalcomponentsaswellasfullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Thehighspeedoscillatoroptionsareselected throughtheconfigurationoptions.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywith it thedisadvantageofhigherpowerrequirements,while theoppositeisofcoursetruefor thelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedeviceshave theflexibility tooptimize theperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq. PinsExternal Crystal HXT 400kHz~�0MHz OSC1/OSC�Internal Hi�h Speed RC HIRC 4� 8� 1�MHz —Internal Low Speed RC LIRC 3�kHz —

Oscillator Types

System Clock ConfigurationsTherearethreemethodsofgeneratingthesystemclock,twohighspeedoscillatorsandalowspeedoscillator.Thehighspeedoscillatorsare theexternalcrystal/ceramicoscillatorand the internal4MHz,8MHz,12MHzRCoscillator.Thelowspeedoscillatoristheinternal32kHzRCoscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforthehighspeedoscillatorischosenviaconfigurationoptions.ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.It isnotpossible tochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.TheOSC1andOSC2pinsareusedtoconnecttheexternalcomponentsfortheexternalcrystal.

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System Clock Configurations

External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer’sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

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Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C21�MHz 0pF 0pF8MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pFNote: C1 and C� val�es are for ��idance only.

Crystal Recommended Capacitor Values

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesofeither4MHz,8MHzor12MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof3Vor5Vandattemperatureof25°C,thethreefixedoscillationfrequenciesoftheHIRCwillhaveatolerancewithin2%.Notethatifthisinternalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation,I/OpinsPA6andPA5arefreeforuseasnormalI/Opins.

Internal 32kHz Oscillator – LIRCThe Internal32kHzSystemOscillator is the lowfrequencyoscillator. It isa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor itsimplementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationson theoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary OscillatorThelowspeedoscillator, inadditiontoprovidingasystemclocksourceisalsousedtoprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedeviceshavemanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

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Themainsystemclock,cancomefromeitherahighfrequency,fH,oralowfrequency,fL,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromeitheranHXTorHIRCoscillator,selectedviaaconfigurationoption.ThelowspeedsystemclocksourcecanbesourcedfromtheinternalclockfL.IffLisselectedthenitcanbesourcedfromtheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfor theperipheralcircuits, thesubstituteclock,fSUB,andtheTimeBaseclock,fTBC.EachoftheseinternalclocksissourcedbytheLIRCoscillator.ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.

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System Clock ConfigurationsNote:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillatorwillstoptoconserve

thepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

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System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modesareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operating ModeDescription

CPU fSYS fLIRC/fSUB fTBC

NORM�L mode On fH~fH/64 On OnSLOW mode On fL On OnILDE0 mode Off Off On OnIDLE1 mode Off On On OnSLEEP0 mode Off Off Off OffSLEEP1 mode Off Off On Off

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,HXTorHIRC.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1 to64, theactualratiobeingselectedby theCKS2~CKS0andHLCLKbits in theSMODregister.Althoughahighspeedoscillator isused, running themicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThis isalsoamodewhere themicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromthelowspeedoscillatorLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisteris low.IntheSLEEP0modetheCPUwillbestopped,andthefLIRCclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.

SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefLIRCclockswillcontinuetooperateiftheWatchdogTimerfunctionisenabled.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.

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IDLE1 ModeTheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fLIRC,willbeon.

Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevices.

SMOD Register

Bit 7 6 5 4 3 2 1 0Name CKS� CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 0 1 1

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fL(fLIRC)001:fL(fLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbetheLIRC,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0mode,butafterawake-uphasoccurredtheflagwillchangetoahighlevelafter1~2cyclesiftheLIRCoscillatorisused.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Mode,butafterpoweronresetorawake-uphasoccurred, theflagwillchangetoahighlevelafter1024clockcycles if theHXToscillator isusedandafter15~16clockcycles if theHIRCoscillatorisused.

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Bit1 IDLEN:IDLEModeControl0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:SystemClockSelection0:fH/2~fH/64orfL1:fH

Thisbit isusedtoselect if thefHclockor thefH/2~fH/64orfLclockisusedas thesystemclock.When thebit ishigh the fH clockwillbe selectedand if low thefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

Fast Wake-upTominimisepowerconsumption thedevicescanenter theSLEEPor IDLE0Mode,where thesystemclocksourcetothedeviceswillbestopped.Howeverwhenthedevicesarewokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedevicesareupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelytheLIRCoscillator, toactasa temporaryclocktofirstdrivethesystemuntil theoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunction is fSUB, theFastWake-upfunction isonlyavailable in theSLEEP1andIDLE0modes.WhenthedevicesarewokenupfromtheSLEEP0mode, theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclock,andif theFastWake-upfunction isenabled, then itwill takeone to twotSUBclockcyclesof theLIRCoscillatorfor thesystemtowake-up.ThesystemwilltheninitiallyrununderthefSUBclocksourceuntil1024HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

If theHIRCoscillatorsorLIRCoscillatorisusedasthesystemoscillatorthenitwill take15~16clockcyclesof theHIRCor1~2cyclesof theLIRCtowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

System Oscillator

FSTEN Bit

Wake-up Time(SLEEP0 Mode)

Wake-up Time (SLEEP1 Mode)

Wake-up Time (IDLE0 Mode, FSYSON=0)

Wake-up Time (IDLE1 Mode, FSYSON=1)

HXT

0 10�4 HXT cycles 10�4 HXT cycles 1~� HXT cycles

1 10�4 HXT cycles1~� fSUB cycles(System r�ns with fSUB first for 1024 HXT cycles and then switches over to r�n with the HXT clock)

1~� HXT cycles

HIRC × 15~16 HIRC cycles 15~16 HIRC cycles 1~� HIRC cyclesLIRC × 1~� LIRC cycles 1~� LIRC cycles 1~� LIRC cycles

NotethatiftheWatchdogTimerisdisabled,whichmeansthattheLIRCisoff,thentherewillbenoFastWake-upfunctionavailablewhenthedeviceswake-upfromtheSLEEP0Mode.

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Operating Mode Switching Thedevicescanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedevicesentertheIDLEModeortheSLEEPModeisdeterminedbytheconditionof theIDLENbit in theSMODregisterandFSYSONintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchas theTMs.Theaccompanyingflowchartshowswhathappenswhenthedevicesmovebetweenthevariousoperatingmodes.

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NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower, thesystemclockcanswitch to run in theSLOWModebysetting theHLCLKbitto“0”andsettingtheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequires thisoscillator tobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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SLOW Mode to NORMAL Mode Switching InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,where thehighspeedsystemoscillator isused, theHLCLKbit shouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusoftheHTObit ischecked.Theamountof timerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

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Entering the SLEEP0 ModeThereisonlyonewayforthedevicestoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDToff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstopped.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Entering the SLEEP1 ModeThereisonlyonewayforthedevicestoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefLIRCclock.


• TheWDTwillbeclearedandresumecountingastheWDTisenabled.



Entering the IDLE0 ModeThereisonlyonewayforthedevicestoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheTimeBaseclockfTBCandthefSUBclockwillbeon.


• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.



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Entering the IDLE1 ModeThereisonlyonewayforthedevicestoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.


• TheWDTwillbeclearedandresumecountingiftheWDTisenabled.



Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinson thedevices.Allhigh-impedance inputpinsmustbeconnected toeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobe takenwith the loads,whichareconnected to I/Opins,whichare setupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Modethesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator, theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedevicesarewokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagisset ifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

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EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Programming ConsiderationsThehighspeedandlowspeedoscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandtheHIRCoscillatorsneedtostart-upfromanoffstate.

• If thedevicesarewokenupfromtheSLEEP0Modeto theNORMALMode, thehighspeedsystemoscillatorneedsanSSTperiod.ThedeviceswillexecutefirstinstructionafterHTOis“1”.

• IfthedevicesarewokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLIRCoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasTMs,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfHto fL, theclocksource to theperipheral functionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceissourcedfromfLIRC.

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Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalfLIRCclockwhichissuppliedbytheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.TheWRFsoftwareresetflagwillbeindicatedintheCTRLregister.ThisregistercontrolstheoveralloperationoftheWatchdogTimer.

WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE� WE1 WE0 WS� WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol10101:WDTdisable01010:WDTenableOthervalues:ResetMCU

Whenthesebitsarechangedtoanyothervaluesbytheenvironmentalnoisetoresetthemicrocontroller,theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitintheCTRLregisterwillbesetto1toindicatetheresetsource.

Bit2~0 WS2~WS0:WDTTime-outperiodselection000:28/fLIRC001:210/fLIRC010:212/fLIRC011:214/fLIRC100:215/fLIRC101:216/fLIRC110:217/fLIRC111:218/fLIRC

Thesethreebitsdeterminethedivisionratioof theWatchdogTimersourececlock,whichinturndeterminesthetimeoutperiod.

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CTRL Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

"x": �nknownBit7 FSYSON:fSYSControlIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribeelsewhereBit1 LRF:LVRCregistersoftwareresetflag

DescribeelsewhereBit0 WRF:WDTCregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearWDTinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertoadditionalenable/disableandresetcontroloftheWatchdogTimer.

WE4~WE0 Bits WDT Function10101B Disable01010B Enable

�ny other val�e Reset MCU

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansavalueotherthan01010Band10101BiswrittenintotheWE4~WE0bitlocations,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthethirdisviaaHALTinstruction.ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

Themaximumtime-outperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

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“CLR WDT”Instr�ction

8-sta�e Divider WDT Prescaler

WE4~WE0 bitsWDTC Re�ister Reset MCU

LIRCfLIRC fLIRC/�8

8-to-1 MUX

CLR

WS�~WS0 WDT Time-o�t(�8/fLIRC ~ �18/fLIRC)

“H�LT”Instr�ction

Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringinternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

VDD

Power-on Reset

SST Time-o�t

tRSTD

Note:tRSTDispower-ondelay,typicaltime=50msPower-On Reset Timing Chart

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Low Voltage Reset – LVRThemicrocontrollerscontainalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevices,whichisselectedviatheLVRCregister.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbit intheCTRLregisterwillalsobesetto1.ForavalidLVRsignal,a lowvoltage, i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.characteristics.Ifthelowvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRcanbeselectedbytheLVSbits in theLVRCregister. If theLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoise, theLVRwillreset thedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.Notethat theLVRfunctionwillbeautomaticallydisabledwhenthedevicesenterthepowerdownmode.

LVR

Internal ResettRSTD + tSST

Note:tRSTDispower-ondelay,typicaltime=50msLow Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS� LVS6 LVS5 LVS4 LVS3 LVS� LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7~LVS0:LVRVoltageSelectcontrol01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VAnyothervalue:GeneratesMCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.Theresetoperationwillbeactivatedafter2~3LIRCclockcycles.Inthissituationthisregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,other thanthefourdefinedvaluesabove,willalsoresult in thegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3LIRCclockcycles.HoweverinthissituationthisregistercontentswillberesettothePORvalue.

Rev. 1.50 48 ��st �� 01� Rev. 1.50 4� ��st �� 01�



• CTRL Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — × 0 0

"x": �nknownBit7 FSYSON:fSYSControlIDLEMode

0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRCregistersoftwareresetflag0:Notoccur1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynondefinedLVRvoltageregistervalues.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit0 WRF:WDTCregistersoftwareresetflagDescribeelsewhere

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperationisthesameasanLVRresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

WDT Time-o�t

Internal ResettRSTD + tSST

Note:tRSTDispower-ondelay,typicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-o�t

Internal ResettSST

Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbytheHIRC.ThetSSTis1024clocksforHXT.ThetSSTis1~2clockfortheLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Rev. 1.50 48 ��st �� 01� Rev. 1.50 4� ��st �� 01�



Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Power-on reset� � LVR reset d�rin� NORM�L or SLOW Mode operation1 � WDT time-o�t reset d�rin� NORM�L or SLOW Mode operation1 1 WDT time-o�t reset d�rin� IDLE or SLEEP Mode operation

Note: “�” stands for �nchan�edThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETPro�ram Co�nter Reset to zeroInterr�pts �ll interr�pts will be disabledWDT Clear after reset� WDT be�ins co�ntin�Timer Mod�les Timer Mod�les will be t�rned offInp�t/O�tp�t Ports I/O ports will be set�p as inp�ts and �N0~�N4 as �/D inp�t pinsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrollerisinafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.Notethatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

RegisterH

T66F007

HT66F008

Reset(Power On) LVR Reset

WDT Time-out(Normal

Operation)

WDT Time-out(HALT)*

I�R0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP0 ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �I�R1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP1 ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �BP ● ● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - ��CC ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �PCL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �TBLH ● ● x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �

TBHP● - - - - - - x x - - - - - - � � - - - - - - � � - - - - - - � �

● - - - - x x x x - - - - � � � � - - - - � � � � - - - - � � � �ST�TUS ● ● - - 0 0 x x x x - - � � � � � � - - 1 � � � � � - - 1 1 � � � �SMOD ● ● 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 � � � � � � � �INTEG ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �INTC0 ● ● - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �INTC1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC� ● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �MFI0 ● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �MFI1 ● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �MFI� ● ● - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �

Rev. 1.50 50 ��st �� 01� Rev. 1.50 51 ��st �� 01�



Register

HT66F007

HT66F008

Reset(Power On) LVR Reset

WDT Time-out(Normal

Operation)

WDT Time-out(HALT)*

P� ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �P�C ● ● 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �P�PU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�WU ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PRM ● ● 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 � � � � � - � �LVRC ● ● 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 � � � � � � � �WDTC ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 � � � � � � � �TBC ● ● 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 0 0 1 1 - 1 1 1 � � � � - � � �CTRL ● ● 0 - - - - x 0 0 0 - - - - y y y 0 - - - - y y y � - - - - � � �

EE�H● - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - �

● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �EE� ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �EED ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � ��DRL (�DRFS=0) ● ● x x x x - - - - x x x x - - - - x x x x - - - - � � � � - - - -�DRL (�DRFS=1) ● ● x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � ��DRH (�DRFS=0) ● ● x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � ��DRH (�DRFS=1) ● ● - - - - x x x x - - - - x x x x - - - - x x x x - - - - � � � ��DCR0 ● ● 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 � � � - - � � ��DCR1 ● ● 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 � � � � � � � ��CER ● ● - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - � � � � �CPC ● ● 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 � � � � � � � �TMPC ● ● - - - 0 0 1 0 1 - - - 0 0 1 0 1 - - - 0 0 1 0 1 - - - � � � � �TM0C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM0�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM0�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM1C0 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1DH ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM1�L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM1�H ● ● - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �TM�C0 ● ● 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -TM�C1 ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�DL ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�DH ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM��L ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM��H ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �TM�RP ● ● 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �SPC ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � �EEC ● ● - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � �

Note:"*"standsforwarmreset"-"notimplement"u"standsfor"unchanged""x"standsfor"unknown""y"standsfor"byregisterbitfunction"

Rev. 1.50 50 ��st �� 01� Rev. 1.50 51 ��st �� 01�



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedevicesprovidebidirectionalinput/outputlineslabeledwithportnamesPA.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

RegisterName

Bit

7 6 5 4 3 2 1 0P� P�� P�6 P�5 P�4 P�3 P�� P�1 P�0

P�C P�C� P�C6 P�C5 P�C4 P�C3 P�C� P�C1 P�C0P�PU P�PU� P�PU6 P�PU5 P�PU4 P�PU3 P�PU� P�PU1 P�PU0P�WU P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0PRM TCK1PS1 TCK1PS0 TCK0PS TP10PS TP01PS — INTPS1 INTPS0SPC — — — — SPC3 SPC� SPC1 SPC0

I/O Control Register List

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasan inputhave thecapabilityofbeingconnected toan internalpull-highresistor.Thesepull-highresistorsareselectedusingregisterPAPU,andareimplementedusingweakPMOStransistors.

PAPU Register

Bit 7 6 5 4 3 2 1 0Name P�PU� P�PU6 P�PU5 P�PU4 P�PU3 P�PU� P�PU1 P�PU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 I/OPortAbit7~bit0Pull-HighControl0:Disable1:Enable

Rev. 1.50 5� ��st �� 01� Rev. 1.50 53 ��st �� 01�



Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU Register

Bit 7 6 5 4 3 2 1 0Name P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU� P�WU1 P�WU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 I/OPortAbit7~bit0WakeUpControl0:Disable1:Enable

I/O Port Control RegistersEachI/OporthasitsowncontrolregisterknownasPAC,tocontroltheinput/outputconfiguration.With thiscontrol register,eachCMOSoutputor inputcanbe reconfigureddynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinitsassociatedportcontrolregister.FortheI/Opintofunctionasaninput, thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswill thenallowthe logicstateof the inputpin tobedirectly readbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC Register

Bit 7 6 5 4 3 2 1 0Name P�C� P�C6 P�C5 P�C4 P�C3 P�C� P�C1 P�C0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input

Rev. 1.50 5� ��st �� 01� Rev. 1.50 53 ��st �� 01�



Special Pin ControlTherearefourpins,namedPA2,PA5,PA6andPA7,canbesettoTTLorCMOSinputforspecialapplications.

SPC Register

Bit 7 6 5 4 3 2 1 0Name — — — — SPC3 SPC� SPC1 SPC0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 SPC3:PA7Specialpincontrol

0:CMOSinput1:TTLinput

Bit2 SPC2:PA6Specialpincontrol0:CMOSinput1:TTLinput



Pin-remapping FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyof thesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremorethanonepinfunctionisselectedsimultaneously.Additionally there isaPRMregistertoestablishcertainpinfunctions.Generallyspeaking,theanalogfunctionhashigherprioritythanthedigitalfunction.However,ifmorethantwoanalogfunctionsareenabledandtheanalogsignalinputcomesfromthesameexternalpin,theanaloginputwillbeinternallyconnectedtoalloftheseactiveanalogfunctionalmodules.

Rev. 1.50 54 ��st �� 01� Rev. 1.50 55 ��st �� 01�



Pin-remapping RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.

• PRM Register

Bit 7 6 5 4 3 2 1 0Name TCK1PS1 TCK1PS0 TCK0PS TP10PS TP01PS — INTPS1 INTPS0R/W R/W R/W R/W R/W R/W — R/W R/WPOR 0 0 0 0 0 — 0 0

Bit7~6 TCK1PS1, TCK1PS0:TCK1pin-remappingfunctionselectionbit00:TCK1onPA201:TCK1onPA710:Undefined11:TCK1onPA4

Bit5 TCK0PS:TCK0pin-remappingfunctionselectionbit0:TCK0onPA71:TCK0onPA6

Bit4 TP10PS:TP1_0pin-remappingfunctionselectionbit0:TP1_0onPA61:TP1_0onPA7

Bit3 TP01PS:TP0_1pin-remappingfunctionselectionbit0:TP0_1onPA51:TP0_1onPA1

Bit2 Unimplemented,readas“0”Bit1~0 INTPS1, INTPS0:INTpin-remappingfunctionselectionbit

00:INTonPA501:INTonPA210:INTonPA311:INTonPA7

Rev. 1.50 54 ��st �� 01� Rev. 1.50 55 ��st �� 01�



I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

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A/D Input/Output Structure

Rev. 1.50 56 ��st �� 01� Rev. 1.50 5� ��st �� 01�



Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.If theportcontrolregister,PAC,is thenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregister,PA,isfirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

Thepower-onresetconditionof theA/Dconvertercontrolregistersensures thatanyA/DinputpinswhicharealwayssharedwithotherI/Ofunctionswillbesetupasanaloginputsafterareset.AlthoughthesepinswillbeconfiguratedasA/Dinputsafterareset,theA/Dconverterwillnotbeswitchedon.It is thereforeimportant tonotethat if it isrequiredtousethesepinsasI/Odigitalinputpinsorasotherfunctions,theA/DconvertercontrolregistersmustbecorrectlyprogrammedtoremovetheA/Dfunction.Notealsothatas theA/Dchannelisenabled,anyinternalpull-highregistorconnectionswillberemoved.

PortAhastheadditionalcapabilityofprovidingwake-upfunctions.WhenthedevicesareintheSLEEPorIDLEMode,variousmethodsareavailabletowakethedevicesup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevices includeseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividualinterrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandStandardTMsections.

IntroductionEachdevicecontains two10-bitCompactTMsanda16-bitStandardTM,the10-bitCTMsarenamedtoTM0andTM1,the16-bitSTMisnamedtoTM2.Althoughsimilarinnature,thedifferentTMtypesvary in their featurecomplexity.Thecommonfeatures to theCompactandStandardTMswillbedescribedinthissectionandthedetailedoperationwillbedescribedincorrespondingsections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMsaresummarisedintheaccompanyingtable.

Rev. 1.50 56 ��st �� 01� Rev. 1.50 5� ��st �� 01�



Function CTM STMTimer/Co�nter √ √Compare Match O�tp�t √ √PWM Channels 1 1Sin�le P�lse O�tp�t — 1PWM �li�nment Ed�e Ed�ePWM �dj�stment Period & D�ty D�ty or Period D�ty or Period

TM Function Summary

TM0 TM1 TM210-bit CTM 10-bit CTM 16-bit STM

TM Name/Type Reference

TM OperationThetwodifferenttypesofTMsofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheTnCK2~TnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefTBCclocksourceortheexternalTCKnpin.Notethatsettingthesebitstothevalue101willselectareservedclockinput,ineffectdisconnectingtheTMclocksource.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompactandStandardtypeTMseachhastwointernalinterrupts, theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhaveoneormoreoutputpins.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpin isalso thepinwhere theTMgenerates thePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutput

Rev. 1.50 58 ��st �� 01� Rev. 1.50 5� ��st �� 01�



functionmustfirstbesetupusingregisters.Asinglebit inoneof theregistersdetermines if itsassociatedpinistobeusedasanexternalTMoutputpinorif it is tohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.

BothCTMandSTMoutputpinnameshavean“_n”suffix.Pinnamesthatincludea“_0”or“_1”suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplementaryoutputpair,selectedusingtheI/Oregisterdatabits.

TM0 TM1 TM2TP0_0� TP0_1 TP1_0� TP1_1 TP�_0

TM Output PinsNote:TheTP2_1pinofSTMisnotbondedtotheexternalTMoutputpin.

TM Input/Output Pin Control RegisterSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingoneregister,withasinglebitineachregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output,ifresettozerothepinwillretainitsoriginalotherfunction.

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TM0 Function Pin Control Block Diagram

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TM1 Function Pin Control Block Diagram

Rev. 1.50 58 ��st �� 01� Rev. 1.50 5� ��st �� 01�



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TM2 Function Pin Control Block DiagramNote:1.TheI/OregisterdatabitsshownareusedforTMoutputinversioncontrol.

2.FortheTM2,theTP2_1pinisnotbondedtotheexternalpin.3.TheabovediagramsdonotincludethePin-remappingfunction,refertothePRMregisterforthePin-remappingfunction.

• TMPC Register

Bit 7 6 5 4 3 2 1 0Name — — — T�CP0 T1CP1 T1CP0 T0CP1 T0CP0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 1 0 1

Bit7~5 Unimplemented,readas“0”Bit4 T2CP0:TP2_0pincontrol

0:Disable1:Enable

Bit3 T1CP1:TP1_1pinControl0:Disabled1:Enabled

Bit2 T1CP0:TP1_0pincontrol0:Disabled1:Enabled



Rev. 1.50 60 ��st �� 01� Rev. 1.50 61 ��st �� 01�



Programming ConsiderationsTheTMCounterRegistersandtheCompareCCRAregister,beingeither10-bitor16-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAregister is implementedinthewayshowninthefollowingdiagramandaccessingthisregisteriscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe“MOV”instruction to access theCCRA lowbyte register, namedTMxAL, in the following accessprocedures.AccessingtheCCRAlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

DataB�s

8-bit B�ffer

TMxDHTMxDL

TMx�HTMx�L

TM Co�nter Re�ister (Read only)

TM CCR� Re�ister (Read/Write)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRA♦ Step1.WritedatatoLowByteTMxAL

– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMxAH

– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRA♦ Step1.ReaddatafromtheHighByteTMxDH,TMxAH

– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDL,TMxAL– thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.50 60 ��st �� 01� Rev. 1.50 61 ��st �� 01�



Compact Type TM – CTMAlthoughthesimplestformofthetwoTMtypes,theCompactTMtypestillcontainsthreeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandriveoneortwoexternaloutputpins.Thesetwoexternaloutputpinscanbethesamesignalortheinversesignal.

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Compact Type TM Block Diagram (n=0, 1)

Compact Type TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltwooutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.50 6� ��st �� 01� Rev. 1.50 63 ��st �� 01�



Compact Type TM Register DescriptionOveralloperationofeachCompactTMiscontrolledusingseveralregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

RegisterName

Bit

7 6 5 4 3 2 1 0TMPC — — — T�CP0 T1CP1 T1CP0 T0CP1 T0CP0TMnC0 TnP�U TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRTMnDL D� D6 D5 D4 D3 D� D1 D0TMnDH — — — — — — D� D8TMn�L D� D6 D5 D4 D3 D� D1 D0TMn�H — — — — — — D� D8

Compact Type TM Register List (n=0, 1)

• TMnC0 Register

Bit 7 6 5 4 3 2 1 0Name TnP�U TnCK� TnCK1 TnCK0 TnON TnRP� TnRP1 TnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TnPAU:TMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 TnCK2~TnCK0:SelectTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:fTBC110:TCKnrisingedgeclock111:TCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 TnON:TMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.

Rev. 1.50 6� ��st �� 01� Rev. 1.50 63 ��st �� 01�



IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheTnOCbit,whentheTnONbitchangesfromlowtohigh.

Bit2~0 TnRP2~TnRP0:TMnCCRP3-bitregister,comparedwiththeTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024TMnclocks001:128TMnclocks010:256TMnclocks011:384TMnclocks100:512TMnclocks101:640TMnclocks110:768TMnclocks111:896TMnclocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theTnCCLRbit isset tozero.SettingtheTnCCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

• TMnC1 Register

Bit 7 6 5 4 3 2 1 0Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 TnM1~TnM0:SelectTMnOperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetothebits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 TnIO1~TnIO0:SelectTMnoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Undefined

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theTnIO1~TnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheTnIO1~TnIO0bits

Rev. 1.50 64 ��st �� 01� Rev. 1.50 65 ��st �� 01�



arebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheTnOCbit.NotethattheoutputlevelrequestedbytheTnIO1~TnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheTnOCbitotherwisenochangewilloccuron theTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to its initial levelbychangingtheleveloftheTnONbitfromlowtohigh.In thePWMMode, theTnIO1andTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheTnIO1andTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theTnIO1andTnIO0bitsarechangedwhentheTMisrunning.

Bit3 TnOC:TMnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputMode itdetermines the logic levelof theTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 TnPOL:TMnOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTMoutputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 TnDPX:TMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 TnCCLR:SelectTMnCounterclearcondition0:TMnComparatrorPmatch1:TMnComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheTnCCLRbitisnotusedinthePWMMode.

Rev. 1.50 64 ��st �� 01� Rev. 1.50 65 ��st �� 01�



• TMnDL Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TMnDL:TMnCounterLowByteRegisterbit7~bit0TMn10-bitCounterbit7~bit0

• TMnDH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnDH:TMnCounterHighByteRegisterbit1~bit0

TMn10-bitCounterbit9~bit8

• TMnAL Register


Bit7~0 TMnAL:TMnCCRALowByteRegisterbit7~bit0TMn10-bitCCRAbit7~bit0

• TMnAH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TMnAH:TMnCCRAHighByteRegisterbit1~bit0

TMn10-bitCCRAbit9~bit8

Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMOutputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheTnM1andTnM0bitsintheTMnC1register.

Compare Match Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothTnAFandTnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheTnCCLRbitintheTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theTnAFinterrupt request flagwillbe

Rev. 1.50 66 ��st �� 01� Rev. 1.50 6� ��st �� 01�



generatedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenTnCCLRishighnoTnPFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheTnAFinterruptrequestflagwillnotbegenerated.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaTnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheTnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theTnIO1andTnIO0bitsintheTMnC1register.TheTMoutputpincanbeselectedusingtheTnIO1andTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theTnONbitchangesfromlowtohigh,issetupusingtheTnOCbit.NotethatiftheTnIO1andTnIO0bitsarezerothennopinchangewilltakeplace.

Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

TnPOL

CCRP Int. Fla� TnPF

CCR� Int. Fla� Tn�F

TM O/P Pin

Time

CCRP=0

CCRP > 0

Co�nter overflowCCRP > 0Co�nter cleared by CCRP val�e

Pa�se

Res�me

Stop

Co�nter Restart

TnCCLR = 0; TnM [1:0] = 00

O�tp�t pin set to initial Level Low if TnOC=0

O�tp�t To��le with Tn�F fla�

Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnIO [1:0] = 11

To��le O�tp�t select

O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit

O�tp�t PinReset to Initial val�e

O�tp�t controlled by other pin-shared f�nction

O�tp�t Invertswhen TnPOL is hi�h

Compare Match Output Mode – TnCCLR=0Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag3.TheoutputpinresettoinitialstatebyaTnONbitrisingedge4.n=0or1

Rev. 1.50 66 ��st �� 01� Rev. 1.50 6� ��st �� 01�



Co�nter Val�e

0x3FF

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin

Time

CCR�=0

CCR� = 0Co�nter overflowCCR� > 0 Co�nter cleared by CCR� val�e

Pa�se

Res�me

Stop Co�nter Restart



Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select

Here TnIO [1:0] = 11 To��le O�tp�t select

O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t Pin

Reset to Initial val�eO�tp�t controlled by other pin-shared f�nction


TnPF not �enerated

No Tn�F fla� �enerated on CCR� overflow

O�tp�t does not chan�e

TnCCLR = 1; TnM [1:0] = 00

Compare Match Output Mode – TnCCLR=1Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag3.TheoutputpinresettoinitialstatebyaTnONrisingedge4.TheTnPFflagsisnotgeneratedwhenTnCCLR=15.n=0or1

Rev. 1.50 68 ��st �� 01� Rev. 1.50 6� ��st �� 01�



Timer/Counter ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsTnM1andTnM0intheTMnC1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theTnCCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheTnDPXbitintheTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheTnOCbitIntheTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoTnIO1andTnIO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• CTM, PWM Mode, Edge-aligned Mode, TnDPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod 1�8 �56 384 51� 640 �68 8�6 10�4D�ty CCR�

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100b,CCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• CTM, PWM Mode, Edge-aligned Mode, TnDPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod CCR�D�ty 1�8 �56 384 51� 640 �68 8�6 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.50 68 ��st �� 01� Rev. 1.50 6� ��st �� 01�



Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL

TM O/P Pin (TnOC=1)

Time

Co�nter cleared by CCRP

Pa�se Res�me Co�nter Stop if TnON bit low

Co�nter Reset when TnON ret�rns hi�h

PWM D�ty Cycle set by CCR�

PWM res�mes operationO�tp�t controlled by

other pin-shared f�nction O�tp�t Invertswhen TnPOL = 1PWM Period set by CCRP

TM O/P Pin (TnOC=0)



TnDPX = 0; TnM [1:0] = 10

PWM Mode – TnDPX=0Note:1.HereTnDPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0or1

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin (TnOC=1)

Time

Co�nter cleared by CCR�



PWM D�ty Cycle set by CCRP


other pin-shared f�nction O�tp�t Invertswhen TnPOL = 1

PWM Period set by CCR�

TM O/P Pin (TnOC=0)

TnDPX = 1; TnM [1:0] = 10

PWM Mode – TnDPX=1Note:1.HereTnDPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0or1

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



Standard Type TM – STMTheStandardTypeTMcontainsfouroperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,SinglePulseOutputandPWMOutputmodes.TheStandardTMcandriveoneexternaloutputpin.

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Note:TPn_1(n=2)pinisnotconnectedtotheexternalpin.Standard Type TM Block Diagram (n=2)

Standard Type TM OperationAtitscoreisa16-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis8-bitwidewhosevalueiscomparedwiththehighest8bitsinthecounterwhiletheCCRAisthesixteenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the16-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theT2ONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



Standard Type TM Register DescriptionOveralloperationof theStandardTMiscontrolledusingseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal16-bitCCRAvalue.Aread/writeregister isusedtostorethe8-bitCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

RegisterName

Bit

7 6 5 4 3 2 1 0TM�C0 T�P�U T�CK� T�CK1 T�CK0 T�ON — — —TM�C1 T�M1 T�M0 T�IO1 T�IO0 T�OC T�POL T�DPX T�CCLRTM�DL D� D6 D5 D4 D3 D� D1 D0TM�DH D15 D14 D13 D1� D11 D10 D� D8TM��L D� D6 D5 D4 D3 D� D1 D0TM��H D15 D14 D13 D1� D11 D10 D� D8TM�RP D� D6 D5 D4 D3 D� D1 D0

16-bit Standard Type TM Register List

• TM2C0 Register

Bit 7 6 5 4 3 2 1 0Name T�P�U T�CK� T�CK1 T�CK0 T�ON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 T2PAU:TM2CounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 T2CK2~T2CK0:SelectTM2Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:Reserved110:Reserved111:Reserved

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.TheclocksourcefSYS is thesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 T2ON:TM2CounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT2OCbit,whentheT2ONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas"0"

• TM2C1 Register

Bit 7 6 5 4 3 2 1 0Name T�M1 T�M0 T�IO1 T�IO0 T�OC T�POL T�DPX T�CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T2M1~T2M0:SelectTM2OperatingMode00:CompareMatchOutputMode01:Undefined10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetothebits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T2IO1~T2IO0:SelectTM2outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theT2IO1~T2IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheT2IO1~T2IO0bitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT2OCbit.NotethattheoutputlevelrequestedbytheT2IO1~T2IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT2OCbitotherwisenochangewilloccuron theTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate itcanbereset to its initial levelbychangingtheleveloftheT2ONbitfromlowtohigh.In thePWMMode, theT2IO1andT2IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheT2IO1andT2IO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theT2IO1andT2IO0bitsarechangedwhentheTMisrunning.

Rev. 1.50 �4 ��st �� 01� Rev. 1.50 �5 ��st �� 01�



Bit3 T2OC:TM2OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 T2POL:TM2OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTMoutputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T2DPX:TM2PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 T2CCLR:SelectTM2Counterclearcondition0:TMComparatrorPmatch1:TMComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT2CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT2CCLRbitisnotusedinthePWMorSinglePulseMode.

• TM2DL Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TM2DL:TM2CounterLowByteRegisterbit7~bit0TM216-bitCounterbit7~bit0

• TM2DH Register

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D1� D11 D10 D� D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TM2DH:TM2CounterHighByteRegisterbit7~bit0TM216-bitCounterbit15~bit8

Rev. 1.50 �4 ��st �� 01� Rev. 1.50 �5 ��st �� 01�



• TM2AL Register


Bit7~0 TM2AL:TM2CCRALowByteRegisterbit7~bit0TM216-bitCCRAbit7~bit0

• TM2AH Register

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D1� D11 D10 D� D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TM2AH:TM2CCRAHighByteRegisterbit7~bit0TM216-bitCCRAbit15~bit8

• TM2RP Register


Bit7~0 TM2RP:TM2CCRPHighByteRegisterbit7~bit0TM2CCRP8-bitregister,comparedwiththeTM2Counterbit15~bit8.ComparatorPMatchPeriod0:65536TM2clocks1~255:256×(1~255)TM2clocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT2CCLRbit isset tozero.SettingtheT2CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffouroperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheT2M1andT2M0bitsintheTM2C1register.

Compare Match Output ModeToselectthismode,bitsT2M1andT2M0intheTM2C1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheT2CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothT2AFandT2PFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheT2CCLRbitintheTM2C1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theT2AFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.Thereforewhen

Rev. 1.50 �6 ��st �� 01� Rev. 1.50 �� st �� 01�



T2CCLRishighnoT2PFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaT2AFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheT2PFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theT2IO1andT2IO0bitsintheTM2C1register.TheTMoutputpincanbeselectedusingtheT2IO1andT2IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theT2ONbitchangesfromlowtohigh,issetupusingtheT2OCbit.NotethatiftheT2IO1andT2IO0bitsarezerothennopinchangewilltakeplace.



Co�nter Val�e

0xFFFF

CCRP

CCR�

TnON

TnP�U

TnPOL

Time

CCRP=0

CCRP > 0

Co�nter overflowCCRP > 0Co�nter cleared by CCRP val�e

Pa�se

Res�me

Stop

Co�nter Restart



Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere TnIO [1:0] = 11

To��le O�tp�t select

O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit

O�tp�t PinReset to Initial val�e

O�tp�t controlled by other pin-shared f�nction


TnCCLR = 0; TnM [1:0] = 00

Compare Match Output Mode – TnCCLR=0Note:1.WithTnCCLR=0aComparatorPmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag3.TheoutputpinresettoinitialstatebyaTnONbitrisingedge4.n=2

Rev. 1.50 �6 ��st �� 01� Rev. 1.50 �� st �� 01�



Co�nter Val�e

0xFFFF

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin

Time

CCR�=0

CCR� = 0Co�nter overflowCCR� > 0 Co�nter cleared by CCR� val�e

Pa�se

Res�me

Stop Co�nter Restart



Note TnIO [1:0] = 10 �ctive Hi�h O�tp�t select

Here TnIO [1:0] = 11 To��le O�tp�t select

O�tp�t not affected by Tn�F fla�. Remains Hi�h �ntil reset by TnON bit O�tp�t Pin

Reset to Initial val�eO�tp�t controlled by other pin-shared f�nction


TnPF not �enerated

No Tn�F fla� �enerated on CCR� overflow

O�tp�t does not chan�e

TnCCLR = 1; TnM [1:0] = 00

Compare Match Output Mode – TnCCLR=1Note:1.WithTnCCLR=1aComparatorAmatchwillclearthecounter

2.TheTMoutputpincontrolledonlybytheTnAFflag3.TheoutputpinresettoinitialstatebyaTnONrisingedge4.TheTnPFflagsisnotgeneratedwhenTnCCLR=15.n=2

Rev. 1.50 �8 ��st �� 01� Rev. 1.50 �� st �� 01�



Timer/Counter ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto10respectivelyandalso theT2IO1andT2IO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theT2CCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheT2DPXbitintheTM2C1register.

ThePWMwaveformfrequencyanddutycyclecan thereforebecontrolledby thevalues in theCCRAandCCRPregisters.An interrupt flag,one foreachof theCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheT2OCbitIntheTM2C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoT2IO1andT2IO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheT2POLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 16-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=0

CCRP 1~255 0Period CCRP×�56 65536D�ty CCR�

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• 16-bit STM, PWM Mode, Edge-aligned Mode, T2DPX=1

CCRP 1~255 0Period CCR�D�ty CCRP×�56 65536

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto0.

Rev. 1.50 �8 ��st �� 01� Rev. 1.50 �� st �� 01�



Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL

TM O/P Pin (TnOC=1)

Time

Co�nter cleared by CCRP



PWM D�ty Cycle set by CCR�


other pin-shared f�nction O�tp�t Invertswhen TnPOL = 1PWM Period set by CCRP

TM O/P Pin (TnOC=0)



TnDPX = 0; TnM [1:0] = 10

PWM Mode – TnDPX=0Note:1.HereTnDPX=0-CounterclearedbyCCRP

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=2

Rev. 1.50 80 ��st �� 01� Rev. 1.50 81 ��st �� 01�



Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin (TnOC=1)

Time

Co�nter cleared by CCR�



PWM D�ty Cycle set by CCRP


other pin-shared f�nction O�tp�t Invertswhen TnPOL = 1

PWM Period set by CCR�

TM O/P Pin (TnOC=0)

TnDPX = 1; TnM [1:0] = 10

PWM Mode – TnDPX=1Note:1.HereTnDPX=1-CounterclearedbyCCRA

2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=2

Single Pulse ModeToselectthismode,bitsT2M1andT2M0intheTM2C1registershouldbesetto10respectivelyandalsotheT2IO1andT2IO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheT2ONbit,whichcanbeimplementedusingtheapplicationprogram.WhentheT2ONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheT2ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheT2ONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

Rev. 1.50 80 ��st �� 01� Rev. 1.50 81 ��st �� 01�



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� � � � � � � ��

� � � � � � � ��

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� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � � � � � �

Single Pulse Generation (n=2)

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheT2ONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.Thecountercanonlyberesetback tozerowhentheT2ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheT2CCLRandT2DPXbitsarenotusedinthisMode.

Co�nter Val�e

CCRP

CCR�

TnON

TnP�U

TnPOL



TM O/P Pin(TnOC=1)

Time

Co�nter stopped by CCR�

Pa�seRes�me Co�nter Stops

by software


P�lse Width set by CCR�

O�tp�t Invertswhen TnPOL = 1

No CCRP Interr�pts �enerated

TM O/P Pin(TnOC=0)

Software Tri��er

Cleared by CCR� match Software

ClearSoftware Tri��erSoftware

Tri��er

TnM [1:0] = 10 ; TnIO [1:0] = 11



Cleared by CCR� match

Single Pulse ModeNote:1.CounterstoppedbyCCRAmatch

2.CCRPisnotused3.ThepulseistriggeredbysettingtheTnONbithigh4.IntheSinglePulseMode,TnIO[1:0]mustbesetto“11”andcannotbechanged.5.n=2

Rev. 1.50 8� ��st �� 01� Rev. 1.50 83 ��st �� 01�



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicescontainamulti-channelanalog todigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.

Input Channels A/D Channel Select Bits Input Pins5 �CS4� �CS�~�CS0 �N0~�N4

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

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A/D Converter Structure

A/D Converter Register DescriptionOveralloperationoftheA/Dconverter iscontrolledusingfiveregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingthreeregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

RegisterName

Bit

7 6 5 4 3 2 1 0�DRL(�DRFS=0) D3 D� D1 D0 — — — —�DRL(�DRFS=1) D� D6 D5 D4 D3 D� D1 D0�DRH(�DRFS=0) D11 D10 D� D8 D� D6 D5 D4�DRH(�DRFS=1) — — — — D11 D10 D� D8�DCR0 ST�RT EOCB �DOFF �DRFS — �CS� �CS1 �CS0�DCR1 �CS4 VBGEN — VREFS — �DCK� �DCK1 �DCK0�CER — — — �CE4 �CE3 �CE� �CE1 �CE0

A/D Converter Register List

Rev. 1.50 8� ��st �� 01� Rev. 1.50 83 ��st �� 01�



A/D Converter Data Registers – ADRL, ADRHAsthedevicescontainaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.After theconversionprocess takesplace, these registerscanbedirectly readby themicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theADCR0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.

ADRFSADRH ADRL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D� D8 D� D6 D5 D4 D3 D� D1 D0 0 0 0 01 0 0 0 0 D11 D10 D� D8 D� D6 D5 D4 D3 D� D1 D0

A/D Data Registers

A/D Converter Control Registers – ADCR0, ADCR1, ACERTocontrolthefunctionandoperationoftheA/Dconverter,threecontrolregistersknownasADCR0,ADCR1,ACERareprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS2~ACS0bitsintheADCR0registerandtheACS4bitintheADCR1registerdefinetheADCinputchannelnumber.Asthedevicescontainonlyoneactualanalogtodigitalconverterhardwarecircuit,eachof theindividual5analoginputsmustberoutedtotheconverter. It is thefunctionoftheACS4,ACS2~ACS0bitstodeterminewhichanalogchannelinputsignalsorinternal1.25VisactuallyconnectedtotheinternalA/Dconverter.

TheACERcontrolregistercontainstheACE4~ACE0bitswhichdeterminewhichpinsonPortAareusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.SettingthecorrespondingbithighwillselecttheA/Dinputfunction,clearingthebittozerowillselecteithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

• ADCR0 Register

Bit 7 6 5 4 3 2 1 0Name ST�RT EOCB �DOFF �DRFS — �CS� �CS1 �CS0R/W R/W R R/W R/W — R/W R/W R/WPOR 0 1 1 0 — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:start0→1:resettheA/DconverterandsetEOCBto“1”

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunningthebitwillbehigh.

Rev. 1.50 84 ��st �� 01� Rev. 1.50 85 ��st �� 01�



Bit5 ADOFF :ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor

savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4 ADRFS:ADCDataFormatControl0:ADCDataMSBisADRHbit7,LSBisADRLbit41:ADCDataMSBisADRHbit3,LSBisADRLbit0

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.

Bit3 Unimplemented,readas“0”Bit2~0 ACS2~ACS0:SelectA/Dchannel(whenACS4is“0”)

000:AN0001:AN1010:AN2011:AN3Others:AN4

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachoftheeightA/Dinputsmustberoutedtotheinternalconverterusingthesebits.IfbitACS4intheADCR1registerissethighthentheinternal1.25VwillberoutedtotheA/DConverter.

• ADCR1 Register

Bit 7 6 5 4 3 2 1 0Name �CS4 VBGEN — VREFS — �DCK� �DCK1 �DCK0R/W R/W R/W — R/W — R/W R/W R/WPOR 0 0 — 0 — 0 0 0

Bit7 ACS4:SelecteInternal1.25VasADCinputControl0:Disable1:Enable

Thisbitenables1.25VtobeconnectedtotheA/Dconverter.TheVBGENbitmustfirsthavebeensettoenablethebandgapcircuit1.25VvoltagetobeusedbytheA/Dconverter.WhentheACS4bitissethigh,thebandgap1.25VvoltagewillberoutedtotheA/DconverterandtheotherA/Dinputchannelsdisconnected.

Bit6 VBGEN:Internal1.25VControl0:Disable1:Enable

Thisbitcontrols the internalBandgapcircuiton/offfunctionto theA/Dconverter.Whenthebitissethighthebandgap1.25VvoltagecanbeusedbytheA/Dconverter.If1.25VisnotusedbytheA/DconverterandtheLVRfunctionisdisabledthenthebandgapreferencecircuitwillbeautomaticallyswitchedofftoconservepower.When1.25VisswitchedonforusebytheA/Dconverter,atimetBGshouldbeallowedforthebandgapcircuittostabilisebeforeimplementinganA/Dconversion.

Bit5 Unimplemented,readas“0”

Rev. 1.50 84 ��st �� 01� Rev. 1.50 85 ��st �� 01�



Bit4 VREFS:SelecteADCreferencevoltage0:InternalADCpower1:VREFpin

ThisbitisusedtoselectthereferencevoltagefortheA/Dconverter.IfthebitishighthentheA/DconverterreferencevoltageissuppliedontheexternalVREFpin.IfthepinislowthentheinternalreferenceisusedwhichistakenfromthepowersupplypinVDD.WhentheA/DconverterreferencevoltageissuppliedontheexternalVREFpinwhichispin-sharedwithotherfunctions,allofthepin-sharedfunctionsexceptVREFonthispinaredisabled.

Bit3 Unimplemented,readas“0”Bit2~0 ADCK2~ADCK0:SelectADCclocksource

000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

• ACER Register

Bit 7 6 5 4 3 2 1 0Name — — — �CE4 �CE3 �CE� �CE1 �CE0R/W — — — R/W R/W R/W R/W R/WPOR — — — 1 1 1 1 1

Bit7~5 Unimplemented,readas“0”Bit4 ACE4:DefinePA5isA/Dinputornot

0:NotA/Dinput1:A/Dinput,AN4

Bit3 ACE3:DefinePA3isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN3




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A/D OperationTheSTARTbit in theADCR0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.

TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess is complete.Thisbitwillbeautomatically set to “0”by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.

AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsADCK2~ADCK0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod, tADCK, isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample, if thesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbesetto000Bor110B.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.

Refer to thefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)ADCK2,ADCK1,ADCK0

=000(fSYS)

ADCK2,ADCK1,ADCK0

=001(fSYS/2)

ADCK2,ADCK1, ADCK0

=010(fSYS/4)

ADCK2,ADCK1, ADCK0

=011(fSYS/8)

ADCK2,ADCK1,ADCK0

=100(fSYS/16)

ADCK2,ADCK1,ADCK0

=101(fSYS/32)

ADCK2,ADCK1,ADCK0

=110(fSYS/64)

ADCK2,ADCK1,ADCK0

=111

1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined�MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined4MHz �50ns* 500ns 1μs 2μs 4μs 8μs 16μs* Undefined8MHz 1�5ns* �50ns* 500ns 1μs 2μs 4μs 8μs Undefined

1�MHz 83ns* 16�ns* 333ns* 66�ns 1.33μs 2.67μs 5.33μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.WhentheADOFFbit isclearedtozerotopowerontheA/Dconverter internalcircuitryacertaindelay,asindicatedinthetimingdiagram,mustbeallowedbeforeanA/Dconversionisinitiated.EvenifnopinsareselectedforuseasA/DinputsbyclearingtheACE4~ACE0bitsintheACERregisters,iftheADOFFbitiszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

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ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,VDD,orfromanexternalreferencesourcessuppliedonpinVREF.ThedesiredselectionismadeusingtheVREFSbit.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFSbitissethigh,theVREFpinfunctionwillbeselectedandtheotherpinfunctionswillbedisabledautomatically.

A/D Input PinsAllof theA/Danalog inputpinsarepin-sharedwith the I/OpinsonPortAaswellasotherfunctions.TheACE4~ACE0bitsintheACERregisters,determinewhethertheinputpinsaresetupasA/Dconverteranaloginputsorwhethertheyhaveotherfunctions.IftheACE4~ACE0bitsforitscorrespondingpinissethighthenthepinwillbesetuptobeanA/Dconverterinputandtheoriginalpinfunctionsdisabled. In thisway,pinscanbechangedunderprogramcontrol tochange theirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePACportcontrolregistertoenabletheA/DinputaswhentheACE4~ACE0bitsenableanA/Dinput, thestatusof theportcontrolregisterwillbeoverridden.

TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheVREFSbitintheADCR1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

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A/D Input Structure

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS4,ACS2~ACS0bitswhicharealsocontainedintheADCR1andADCR0register.

• Step4SelectwhichpinsaretobeusedasA/DinputsandconfigurethembycorrectlyprogrammingtheACE4~ACE0bitsintheACERregister.

Rev. 1.50 88 ��st �� 01� Rev. 1.50 8� ��st �� 01�



• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,ADE,mustbothbesethightodothis.

• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCR0registerfromlowtohighandthenlowagain.Notethat thisbitshouldhavebeenoriginallyclearedtozero.

• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.

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A/D Conversion Timing

Rev. 1.50 88 ��st �� 01� Rev. 1.50 8� ��st �� 01�



Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicescontaina12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheVDDorVREFvoltage,thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.

1LSB=(VDDorVREF)/4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(VDDorVREF)/4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

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Ideal A/D Transfer Function

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockandswitchoff1.25Vclr ADOFFmov a,0Fh ;setupACERtoconfigurepinsAN0~AN3mov ACER,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/Dconverter:start_conversion:clr START ;highpulseonstartbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dpolling_EOC:sz EOCB ;polltheADCR0registerEOCBbittodetectendofA/Dconversionjmp polling_EOC ;continuepollingmov a,ADRL ;readlowbyteconversionresultvaluemov ADRL_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ;readhighbyteconversionresultvaluemov ADRH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnextA/Dconversion

Rev. 1.50 �0 ��st �� 01� Rev. 1.50 �1 ��st �� 01�



Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ; select fSYS/8asA/Dclockandswitchoff1.25VClr ADOFFmov a,0Fh ;setupACERtoconfigurepinsAN0~AN3mov ACER,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion:clr START ;highpulseonSTARTbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interruptset EMI ; enable global interrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory::mov a,ADRL ; read low byte conversion result valuemov adrl_buffer,a ;saveresulttouserdefinedregistermov a,ADRH ; read high byte conversion result valuemov adrh_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryreti

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



ComparatorOneindependentanalogcomparatoriscontainedwithinthedevices.Thisfunctionoffersflexibilityviaitsregistercontrolledfeaturessuchaspower-down,polarityselect,hysteresisetc.InsharingitspinswithnormalI/OpinsthecomparatordoesnotwastepreciousI/Opinsif therefunctionsareotherwiseunused.

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Comparator OperationThedevicescontainonecomparatorwhichisusedtocomparetwoanalogvoltagesandprovideanoutputbasedontheirdifference.Fullcontrolover theinternalcomparator isprovidedviathecontrolregister,CPC.Thecomparatoroutputisrecordedviaabitinthecontrolregister,butcanalsobetransferredoutontoasharedI/Opin.Additionalcomparatorfunctionsinclude,outputpolarity,hysteresisfunctionsandpowerdowncontrol.

Anypull-high resistorsconnected to the sharedcomparator inputpinswillbeautomaticallydisconnectedwhenthecomparatorisenabled.Asthecomparatorinputsapproachtheirswitchinglevel,somespuriousoutputsignalsmaybegeneratedonthecomparatoroutputdueto theslowrisingor fallingnatureof the inputsignals.Thiscanbeminimisedbyselecting thehysteresisfunctionwillapplyasmallamountofpositivefeedbacktothecomparator.Ideallythecomparatorshouldswitchat thepointwherethepositiveandnegativeinputssignalsareat thesamevoltagelevel,however,unavoidableinputoffsetsintroducesomeuncertaintieshere.Thehysteresisfunction,ifenabled,alsoincreasestheswitchingoffsetvalue.

Comparator RegisterThereisoneregisterforoverallcomparatoroperation.

CPC Register

Bit 7 6 5 4 3 2 1 0Name CSEL CEN CPOL COUT COS CINTE1 CINTE0 CHYENR/W R/W R/W R/W R R/W R/W R/W R/WPOR 1 0 0 0 0 0 0 1

Bit7 CSEL:SelectComparatorpinsorI/Opins0:I/Opinsselect1:ComparatorinputpinsCPandCNselected

ThisistheComparatorpinorI/Opinselectbit.Ifthebitishighthecomparatorwillbeselectedandthecomparatorinputpinswillbeenabled.Asaresult,thesetwopinswilllosetheirI/Opinfunctions.Anypull-highconfigurationoptionsassociatedwiththecomparatorsharedpinswillalsobeautomaticallydisconnected.

Bit6 CEN:ComparatorOn/Offcontrol0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedevicesentertheSLEEPorIDLEmode.

Rev. 1.50 �� st �� 01� Rev. 1.50 �3 ��st �� 01�



Bit5 CPOL:Comparatoroutputpolarity0:Outputnotinverted1:Outputinverted

This is thecomparatorpolaritybit. If thebit iszerothentheCOUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorCOUTbitwillbeinverted.

Bit4 COUT:ComparatoroutputbitCPOL=00:CP<CN1:CP>CN

CPOL=10:CP>CN1:CP<CN

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheCPOLbit.

Bit3 COS:Comparatoroutputpathselect0:CXpin1:Internaluse

This is thecomparatoroutputpathselectcontrolbit. If thebit isset to“0”andtheCSELbitis“1”thecomparatoroutputisconnectedtoanexternalCXpin.Ifthebitissetto“1”ortheCSELbitis“0”thecomparatoroutputsignalisonlyusedinternallyby thedeviceallowing thesharedcomparatoroutputpin to retain itsnormal I/Ooperation.

Bit2~1 CINTE1, CINTE0:ComparatorInterruptedgecontrol00:Risingedge01:Fallingedge1x:Risingedgeandfallingedge

Bit0 CHYEN:HysteresisControl0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

Comparator InterruptThecomparatorpossessesitsowninterruptfunction.Whenthecomparatoroutputbitchangesstate,itsrelevantinterruptflagwillbeset,andifthecorrespondinginterruptenablebitisset,thenajumptoitsrelevantinterruptvectorwillbeexecuted.NotethatitisthechangingstateoftheCOUTbitandnottheoutputpinwhichgeneratesaninterrupt.IfthemicrocontrollerisintheSLEEPorIDLEModeandthecomparatorisenabled,theniftheexternalinputlinescausethecomparatoroutputbittochangestate,theresultinggeneratedinterruptflagwillalsogenerateawake-up.Ifitisrequiredtodisableawake-upfromoccurring,thentheinterruptflagshouldbesethighbeforeenteringtheSLEEPorIDLEMode.

Programming ConsiderationsIf thecomparator isenabled, itwillremainactivewhenthemicrocontrollerenters theSLEEPorIDLEMode,howeverasitwillconsumeacertainamountofpower,theusermaywishtoconsiderdisablingitbeforetheSLEEPorIDLEModeisentered.

AscomparatorpinsaresharedwithnormalI/OpinstheI/Oregistersforthesepinswillbereadaszero(portcontrolregisteris“1”)orreadasportdataregistervalue(portcontrolregisteris“0”)ifthecomparatorfunctionisenabled.

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InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicescontainanexternalinterruptandinternal interruptsfunctions.Theexternal interrupt isgeneratedbytheactionof theexternalINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,Comparator,TimeBase,EEPROMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Theinterruptregistersfallintothreecategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI2registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlobal EMI — —INT Pin INTE INTF —�/D Converter �DE �DF —M�lti-f�nction MFnE MFnF n=0~�Comparator CPE CPF —Time Base TBnE TBnF n=0 or 1EEPROM DEE DEF —

TMTnPE TnPF

n=0~�Tn�E Tn�F

Interrupt Register Bit Naming Conventions

RegisterName

Bit

7 6 5 4 3 2 1 0INTEG — — — — — — INTS1 INTS0INTC0 — MF0F TB0F INTF MF0E TB0E INTE EMIINTC1 TB1F �DF DEF MF1F TB1E �DE DEE MF1EINTC� — — MF�F CPF — — MF�E CPEMFI0 — — T0�F T0PF — — T0�E T0PEMFI1 — — T1�F T1PF — — T1�E T1PEMFI� — — T��F T�PF — — T��E T�PE

Interrupt Register Contents

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• INTEG Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — INTS1 INTS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 INTS1, INTS0:DefinesINTinterruptactiveedge

00:DisabledInterrupt01:RisingEdgeInterrupt10:FallingEdgeInterrupt11:DualEdgeInterrupt

• INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — MF0F TB0F INTF MF0E TB0E INTE EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 MF0F:Multi-function0InterruptRequestFlag

0:Norequest1:Interruptrequest

Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 INTF:INTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 MF0E:Multi-function0InterruptControl0:Disable1:Enable

Bit2 TB0E:TimeBase0InterruptControl0:Disable1:Enable

Bit1 INTE:INTInterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

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• INTC1 Register

Bit 7 6 5 4 3 2 1 0Name TB1F �DF DEF MF1F TB1E �DE DEE MF1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TB1F :TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 DEF:DataEEPROMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit4 MF1F:Multi-function1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 TB1E :TimeBase1InterruptControl0:Disable1:Enable

Bit2 ADE:A/DConverterInterruptControl0:Disable1:Enable

Bit1 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit0 MF1E:Multi-function1InterruptControl0:Disable1:Enable

• INTC2 Register

Bit 7 6 5 4 3 2 1 0Name — — MF�F CPF — — MF�E CPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 MF2F:Multi-function2InterruptRequestFlag


Bit4 CPF:ComparatorInterruptRequestFlag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 MF2E:Multi-function2InterruptControl

0:Disable1:Enable

Bit0 CPE:ComparatorInterruptControl0:Disable1:Enable

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• MFI0 Register

Bit 7 6 5 4 3 2 1 0Name — — T0�F T0PF — — T0�E T0PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 T0AF:TM0ComparatorAmatchinterruptrequestflag


Bit4 T0PF:TM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 T0AE:TM0ComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 T0PE:TM0ComparatorPmatchinterruptcontrol0:Disable1:Enable

• MFI1 Register

Bit 7 6 5 4 3 2 1 0Name — — T1�F T1PF — — T1�E T1PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0





0:Disable1:Enable


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• MFI2 Register

Bit 7 6 5 4 3 2 1 0Name — — T��F T�PF — — T��E T�PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0





0:Disable1:Enable


Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchorA/Dconversioncompletionetc, therelevant interruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrom

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becomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

04H

08H

0CH

18H

Vector

Low

PriorityHi�h

Req�estFla�s

EnableBits

MasterEnable

Req�estFla�s

EnableBits

EMI a�to disabled in ISR

Interr�pts contained withinM�lti-F�nction Interr�pts

Interr�ptName

Interr�ptName

EMI

EMI

EMI

DEFEEPROM DEE

T0�FTM0 � T0�E

T0PFTM0 P T0PE

INTFINT Pin INTE

CPFComparator CPE

MF0FM. F�nct. 0 MF0E

�DF�/D �DE EMI

TB0FTime Base 0 TB0E

xxF

Legend

Req�est Fla� – no a�to reset in ISR

xxF Req�est Fla� – a�to reset in ISR

xxE Enable Bit

T1�FTM1 �

T1PFTM1 P

T1�E

T1PE

EMITB1FTime Base 1 TB1E

T��FTM� � T��E

T�PFTM� P T�PE �4HEMIMF�FM. F�nct. � MF�E

10HEMIMF1FM. F�nct. 1 MF1E

14HEMI

1CH

�0HEMI

Interrupt Structure

External InterruptTheexternal interrupt iscontrolledbysignal transitionson thepins INT.Anexternal interruptrequestwilltakeplacewhentheexternalinterruptrequestflag,INTF,isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpin.Toallowtheprogramtobranchtotheinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheexternalinterruptenablebit,INTE,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethe triggeredge type.As theexternal interruptpin ispin-sharedwithanI/Opin, itcanonlybeconfiguredasexternalinterruptpinifitsexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterrupt isenabled, thestackisnotfullandthecorrect transitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatthepull-highresistorselectionontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

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TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Comparator InterruptThecomparator interrupt iscontrolledbytheinternalcomparator.Acomparator interruptrequestwill takeplacewhenthecomparatorinterruptrequestflag,CPF,isset,asituationthatwilloccurwhenthecomparatoroutputbitchangesstate.Toallowtheprogramtobranch to its respectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andcomparator interruptenablebit,CPE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutputtransition,asubroutinecalltothecomparatorinterruptvector,will takeplace.When the interrupt is serviced, thecomparator interrupt request flag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Multi-function InterruptWithinthesedevicesthereareuptothreeMulti-functioninterrupts.Unliketheotherindependentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MF0F~MF2Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMInterrupts,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

A/D Converter InterruptThedevicescontainanA/Dconverterwhichhasitsownindependentinterrupt.TheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwill takeplacewhentheA/DConverterInterruptrequestflag,ADF, isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestack

Rev. 1.50 100 ��st �� 01� Rev. 1.50 101 ��st �� 01�



isnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

• TBC Register

Bit 7 6 5 4 3 2 1 0Name TBON TBCK TB11 TB10 — TB0� TB01 TB00R/W R/W R/W R/W R/W — R/W R/W R/WPOR 0 0 1 1 — 1 1 1

Bit7 TBON:TB0andTB1Controlbit0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11~TB10:SelectTimeBase1Time-outPeriod00:4096/fTB

01:8192/fTB

10:16384/fTB

11:32768/fTB

Bit3 Unimplemented,readas“0”Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod

000:256/fTB

001:512/fTB

010:1024/fTB

011:2048/fTB

100:4096/fTB

101:8192/fTB

110:16384/fTB

111:32768/fTB

��

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� � � � � � � ��

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Time Base Interrupt

Rev. 1.50 10� ��st �� 01� Rev. 1.50 103 ��st �� 01�



EEPROM InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,andtheEEPROMinterruptrequestflag,DEF,willalsobeautomaticallycleared.

TM InterruptsTheCompactandStandardTypeTMseachhastwointerrupts.AlloftheTMinterruptsarecontainedwithintheMulti-functionInterrupts.ForeachoftheCompactandStandardTypeTMstherearetwointerruptrequestflagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.ATMinterruptrequestwill takeplacewhenanyof theTMrequest flagsareset,asituationwhichoccurswhenaTMcomparatorPorcomparatorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtherespectiveTMInterruptenablebit,andassociatedMulti-functioninterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecall to therelevantTMInterruptvector locations,will takeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpin,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF2F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Rev. 1.50 10� ��st �� 01� Rev. 1.50 103 ��st �� 01�



Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Option

1Hi�h Speed/Low Speed System Oscillator Selection – fOSC:

1. HIRC+LIRC�. HXT+LIRC

�

HIRC Freq�ency Selection:1. 4MHz�. 8MHZ3. 1�MHz

Application Circuits

� � � ��

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� � � � � � � � � � � � � ��

� � � � � � �

� � � � � � �

�

� � �

� � � � �

�

� � � � � �

Rev. 1.50 104 ��st �� 01� Rev. 1.50 105 ��st �� 01�



Instruction Set

InstructionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.50 104 ��st �� 01� Rev. 1.50 105 ��st �� 01�



Logical and Rotate OperationsThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasubroutineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall, theprogrammustreturntotheinstructionimmediatelywhenthesubroutinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.Thereisnorequirementtojumpbacktotheoriginaljumpingoffpointas in thecaseof theCALLinstruction.Onespecialandextremelyusefulsetofbranch instructionsare theconditionalbranches.Hereadecision is firstmaderegarding theconditionofacertaindatamemoryorindividualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithintheprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmetic�DD ��[m] �dd Data Memory to �CC 1 Z� C� �C� OV�DDM ��[m] �dd �CC to Data Memory 1Note Z� C� �C� OV�DD ��x �dd immediate data to �CC 1 Z� C� �C� OV�DC ��[m] �dd Data Memory to �CC with Carry 1 Z� C� �C� OV�DCM ��[m] �dd �CC to Data memory with Carry 1Note Z� C� �C� OVSUB ��x S�btract immediate data from the �CC 1 Z� C� �C� OVSUB ��[m] S�btract Data Memory from �CC 1 Z� C� �C� OVSUBM ��[m] S�btract Data Memory from �CC with res�lt in Data Memory 1Note Z� C� �C� OVSBC ��[m] S�btract Data Memory from �CC with Carry 1 Z� C� �C� OVSBCM ��[m] S�btract Data Memory from �CC with Carry� res�lt in Data Memory 1Note Z� C� �C� OVD�� [m] Decimal adj�st �CC for �ddition with res�lt in Data Memory 1Note CLogic Operation�ND ��[m] Lo�ical �ND Data Memory to �CC 1 ZOR ��[m] Lo�ical OR Data Memory to �CC 1 ZXOR ��[m] Lo�ical XOR Data Memory to �CC 1 Z�NDM ��[m] Lo�ical �ND �CC to Data Memory 1Note ZORM ��[m] Lo�ical OR �CC to Data Memory 1Note ZXORM ��[m] Lo�ical XOR �CC to Data Memory 1Note Z�ND ��x Lo�ical �ND immediate Data to �CC 1 ZOR ��x Lo�ical OR immediate Data to �CC 1 ZXOR ��x Lo�ical XOR immediate Data to �CC 1 ZCPL [m] Complement Data Memory 1Note ZCPL� [m] Complement Data Memory with res�lt in �CC 1 ZIncrement & DecrementINC� [m] Increment Data Memory with res�lt in �CC 1 ZINC [m] Increment Data Memory 1Note ZDEC� [m] Decrement Data Memory with res�lt in �CC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRR� [m] Rotate Data Memory ri�ht with res�lt in �CC 1 NoneRR [m] Rotate Data Memory ri�ht 1Note NoneRRC� [m] Rotate Data Memory ri�ht thro��h Carry with res�lt in �CC 1 CRRC [m] Rotate Data Memory ri�ht thro��h Carry 1Note CRL� [m] Rotate Data Memory left with res�lt in �CC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLC� [m] Rotate Data Memory left thro��h Carry with res�lt in �CC 1 CRLC [m] Rotate Data Memory left thro��h Carry 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV ��[m] Move Data Memory to �CC 1 NoneMOV [m]�� Move �CC to Data Memory 1Note NoneMOV ��x Move immediate data to �CC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr J�mp �nconditionally � NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZ� [m] Skip if Data Memory is zero with data movement to �CC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZ� [m] Skip if increment Data Memory is zero with res�lt in �CC 1Note NoneSDZ� [m] Skip if decrement Data Memory is zero with res�lt in �CC 1Note NoneC�LL addr S�bro�tine call � NoneRET Ret�rn from s�bro�tine � NoneRET ��x Ret�rn from s�bro�tine and load immediate data to �CC � NoneRETI Ret�rn from interr�pt � NoneTable Read OperationT�BRD [m] Read table (specific page) to TBLH and Data Memory �Note NoneT�BRDC [m] Read table (c�rrent pa�e) to TBLH and Data Memory �Note NoneT�BRDL [m] Read table (last pa�e) to TBLH and Data Memory �Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdo� Timer 1 TO� PDFCLR WDT1 Pre-clear Watchdo� Timer 1 TO� PDFCLR WDT� Pre-clear Watchdo� Timer 1 TO� PDFSW�P [m] Swap nibbles of Data Memory 1Note NoneSW�P� [m] Swap nibbles of Data Memory with res�lt in �CC 1 NoneH�LT Enter power down mode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

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8-pin DIP (300mil) Outline Dimensions

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Min. Nom. Max.� — 0.�36 BSC —B — 0.154 BSC —C 0.01� — 0.0�0C′ — 0.1�3 BSC —D — — 0.06�E — 0.050 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°


Min. Nom. Max.� —F 6.00 BSC —B — 3.�0 BSC —C 0.31 — 0.51C′ — 4.�0 BSC —D — — 1.�5E — 1.�� BSC —F 0.10 — 0.�5G 0.40 — 1.��H 0.10 — 0.�5α 0° — 8°

Rev. 1.50 1�0 ��st �� 01� Rev. 1.50 1�1 ��st �� 01�



10-pin MSOP Outline Dimensions

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Min. Nom. Max.� — — 0.043

�1 0.000 — 0.006�� 0.030 0.033 0.03�B 0.00� — 0.013C 0.003 — 0.00�D — 0.118 BSC —E — 0.1�3 BSC —

E1 — 0.118 BSC —e — 0.0�0 BSC —L 0.016 0.0�4 0.031

L1 — 0.03� BSC —y — 0.004 —θ 0° — 8°


Min. Nom. Max.� — — 1.10

�1 0.00 — 0.15 �� 0.�5 0.85 0.�5 B 0.1� — 0.33 C 0.08 — 0.�3 D — 3.00 BSC —E — 4.�0 BSC —

E1 — 3.00 BSC —e — 0.50 BSC —L 0.40 0.60 0.80

L1 — 0.�5 BSC —y — 0.10 —θ 0° — 8°

Rev. 1.50 1�0 ��st �� 01� Rev. 1.50 1�1 ��st �� 01�



16-pin NSOP (150mil) Outline Dimensions

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Min. Nom. Max.� — 0.�36 BSC —B — 0.154 BSC —C 0.01� — 0.0�0 C' — 0.3�0 BSC —D — — 0.06� E — 0.050 BSC —F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° ― 8°


Min. Nom. Max.� — 6 BSC —B — 3.� BSC —C 0.31 — 0.51 C' — �.� BSC —D — — 1.�5 E — 1.�� BSC —F 0.10 — 0.�5 G 0.40 — 1.�� H 0.10 — 0.�5 α 0° ― 8°

Rev. 1.50 1�� st �� 01� Rev. 1.50 PB ��st �� 01�



Copyri�ht© �01� by HOLTEK SEMICONDUCTOR INC.

The information appearin� in this Data Sheet is believed to be acc�rate at the time of p�blication. However� Holtek ass�mes no responsibility arisin� from the �se of the specifications described. The applications mentioned herein are used solely for the p�rpose of ill�stration and Holtek makes no warranty or representation that s�ch applications will be s�itable witho�t f�rther modification� nor recommends the �se of its prod�cts for application that may present a risk to h�man life d�e to malf�nction or otherwise. Holtek's prod�cts are not a�thorized for �se as critical components in life s�pport devices or systems. Holtek reserves the ri�ht to alter its products without prior notification. For the most up-to-date information, please visit o�r web site at http://www.holtek.com.tw.

Documents

Cost-Effective A/D Flash MCU with EEPROM - Home - · PDF fileCost-Effective A/D Flash MCU with EEPROM Pin Descriptions With the exception of the power pins, all pins on these devices