Counter Design Xilinx

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    1:XILINX

    ~ - -

    ApplicationNoteCounter Examples

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    l:XILINX

    IntroductionBinary CountersJohnson CountersLinear feedback Shift Register CountersUp/Down Counters . .Heterodyne Counters

    Counter ExamplesTable of Contents

    2-992-1002-1072-1142-1172-119

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    l:XILINX

    INTRODUCTIONHistorically, designers used multiple 74-series TTLdevices to implement various digital counters. However,in application specific intergrated circuit (ASIC) designsthe overall performance and effective utilization of acounter depends on the type of counter used and uponthe architecture of the ASIC device employed. Theflexible array architecture found in the Xilinx Logic CellArray (LCA) provides the designer with numerousoptions when implementing counters. Implementing adesign on "uncommitted" silicon is different from beingforced into an inflexible, fixed architecture. Accordingly,a designer can optimize a counter to meet his specificapplication needs. Tailoring a counter for an applicationreduces the amount of wasted silicon resourcesassociated with fixed-architecture logic devices.Within a Logic Cell Array, a designer can implementvarious counter types, including Binary counters (2n possible states) Johnson counters (2n possible states) Linear Feedback Shift Registers(2n-1 possible states) Up/Down counters (typically binary)

    Counter Examples

    may include parallel load of data, clock enable,synchronous or asynchronous SET or RESET,UP/DOWN control, or others. Synchronous binarycounters are widely-used in digital design but theircomplexity can degrade their overall speed andeffectiveness. The extra routing and logic required toimplement a wide toggle lookahead-carry function, forexample, quickly consumes the resources available inany logic device (a toggle lookahead-carry should not beconfused with the lookahead-carry used in arithmeticlogic). For speed, ease of routing, and glitch-freedecoding, Johnson counters are often the best solutionfor applications of modulo ten or less. If a non-binary,pseudorandom counting sequence is acceptable,Linear Feedback Shift Register (LFSR) counters canbest implement counts above modulo 32.The purpose of this application note is to help thedesigner choose which counter to use for specificapplications in the XC2064 and XC2018 Logic CellArrays (LCAs). Another goal is to help the designer startthinking about alternatives to 7400-series counters.There are various means of attacking the same counterapplication. A designer should use a specific type ofcounter to fill a specific application-not because it is theonly counter type available but because it is the bestcounter for the specific application. The LCA gives the

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    Counter Examplescounters are less resource-efficient for modulos muchhigher than 12 (six registers). However, extremely highperformance Johnson counters can operate at speedsnear the overall toggle frequency of the LCA since thecounter logic and routing is simple.Since each Configurable Logic Block (CLB) within theXC2064 and XC2018 Logic Cell Arrays has a single flipflop or storage element, there is a direct relationbetween flip-flop efficiency and CLB efficiency. Theseterms are practically synonymous when referring to thecounter bits required to implement a counter. Sincesome designs require additional logic beyond the logicassociated with the flip-flop inside a CLB, some forms ofcounters require more CLBs than flip-flops.BINARY COUNTERSOverviewThis section addresses the design and associatedtopics regarding binary ripple, ripple-carry, andlookahead-carry counters. The performance of a binarycounter increases with the amount of lookahead-carry

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    performed at each counter stage. Simple ripplecounters have no lookahead-carry and are the lowestperfomance binary counter. Higher-performance binarycounters require additional silicon resources to decodeand propagate the carry signals. The ripple-carry andlookahead-carry counters require partial or full decodingof all of the previous counter bits. This requires extralogic and routing resources for the carry signals but buysincreased performance.Binary counters operate differently depending on theamount of lookahead carry. Simple ripple countersoperate asynchronously since they do not generatecarry signals, whereas ripple-carry and lookahead-carrycounters are synchronous. Typically synchronousdesign is safer since it is more immune to glitches.Ripple CountersIn simple binary ripple counters, as shown in Figure 2,carry signals are not generated. The output of eachcounter stage asynchronously clocks the next counterstage. The resource requirements to implement a ripplecounter are low-only one CLB per counter bitregardless of counter length. The routing for a binary

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    BINARYCOUNTERS " , ' "2N STATES (EXPONENTIAL) ' "14

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    ripple counter is also simple. The penalty for thissimplicity is lower performance. Each counter bitdegrades the overall performance by a CLB delay time.The overall counter clock period must be greater than orequal to the total delay of all the CLBs used toimplement the counter, as shown in Equation 1.Ripple Counter = N (Clock to Output Delay [1JClock PeriodwhereNClock to Output

    0010023 2

    = number of ripple counter flip-flops=Tcko for K-clock input=Tcco for C-clock input= Tcio for logic clock input

    CLOCKH

    RESETDIR

    E:XILINXBinary ripple counters are primarily used only inapplications that require optimal device utilizationwithout regard to performance. The increased siliconutilization is gained by eliminating carry signals.However, the flip-flops within a binary ripple counter areasynchronously toggled in operation. There aresynchronous forms of this counter that have betterperformance and require the same resources. This istrue because of the flexible array-type architecture ofthe LCA and because of the capability of a single CLB.An example is shown in Figure 3. This synchronousbinary ripple-carry counter still requires only one CLBper bit. Since the ripple-carry includes only the previouscounter stage, resource requirements are minimal. Itssynchronous design affords more reliable operation.

    Figure 2. Binary ripple counters are simple to implement and can be cascaded to nearly any desired length.Their disadvantage stems from their asynchronous operation and their degraded performance with eachadditional counter bit. They are not recommended for most designs because of their asynchronous operation.

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    Counter ExamplesAlthough the single-bit ripple-carry counter requires fewresources, it still suffers from lower performance, muchlike the standard ripple counter. It also exhibits lowerpeformance with each additional CLB or flip-flop.Ripple-Carry CountersThe design shown in Figure 3 is just one example of abinary ripple-carry counter. Ripple-counters have beenused by designers for quite some time. In the past,designers typically implemented large binary ripple-carrycounters with conventional 74-series logic devices.Designers tended to cascade the ripple-carry output ofone 4-bit counter segment with the enable of the next 4-bit counter segment to build larger counters. Counterimplementations within an LCA do not lend themselvesto the "one size fits all" approach of the 74-seriesdevices, since the architectures are different. However,some of the general ideas still apply.Table 1 shows the wide variety of possible binary ripplecarry counters to eight bits in length. Larger ripple-carrycounters are possible but there are far too manypermutations to mention them all. The counters shownin the table consist of smaller counter segments, eachwith its own terminal count and clock enable. Largercounters can be built by cascading these segmentstogether. The terminal count of one segment feeds theclock enable of the next segment and so on. Thecascaded connection of the terminal count to clockenable is called a ripple-carry.By cascading various counter segment macros togetherin the proper order, a designer can construct counterswith various performances and control inputs. The tableindicates the counter size in bits and in total modulo.

    TTL devices. A designer unfamiliar with the capability ofthe LCA might choose a similar implementation usingtwo of the 74-161 counter macros available within theXAClTM Development System. However, a direct onefor-one substitution is wasteful. It would require sixteenCLBs to implement the two 74-161 equivalent circuits.The Xilinx 74-161 macro contains the same functionalityas a 74-161 device. Typically however, not all of theresources of a 74-161 are used in a design. This is thecase in Figure 4a. Some of the CLB capability has beenwasted on circuitry which will not be used for the design(Note: The Xilinx FutureNet Schematic Capture Libraryand Conversion Package reduces the macros to theirprimitive gate levels and then frees any unusedresources).A more rational approach uses only the required amountof circuitry to implement the design. For example, it issimpler and more resource efficient to build the eight-bitcounter with the generic counter macros available withinXACT. Table 1 shows some of the possible macrocombinations used to build an eight-bit counter.An equivalent counter built with two CBBC-rd countermacros and one C4BC-rd counter macro is shown inFigure 4b. The eight-bit counter is built with two 3-bitpieces and a single 2-bit piece. This implementationwas chosen over using two 4-bit pieces since the formerhas superior performance. The 4-bit pieces each havetwo ripple-carry levels each. Therefore the eight-bitcounter implemented with 4-bit pieces will have fourripple-carry delay levels overall. A similar implementationbased on the two 3-bit pieces, and a 2-bit piece only hasthree ripple-carry delay levels, and therefore has higherperformance.

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    CI)

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    COUNTER SIZE AVAILABLE RIPPLESELECTIONS LEVELS2 21 1 22 23 24 25 26 1 271 (Modulo) CE TC8 (4) X X 1FT C4B - X 1

    C4B 1FT (8) X - 1C8B X X 1

    FT C4B FT - - 1FT C8B - X 1

    C8B FT (16) X - 1C4B 1 C4B X X 2

    FT C8B FT - - 1FT C4B C4B - X 2I (32)C4B C4B FT X - 2

    C8B C4B X X 2FT C4B C4B FT - - 2FT C8B C4B - X 2

    C8B C4B FT (64) X - 2C8B caB X X 2

    C4B I C4B C4B X X 3FT C8B C4B FT - - 2FT caB C8B - X 2FT C4B C4B C4B - X 3

    CLKENAORCE&RESET

    CLBs334445546556677a6897

    t:XILINX

    CLKENA&PARENA

    CLBs344556667778899109101110

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    I\ )I.....o

    0010023 4A

    CLKENA

    CLOCKRESETDIR

    0010023 4B

    +5

    ENABLE

    CLOCKCLEAR

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    CET 74-161CEPC

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    TC 1 4 04-07LO~ ~ 74-161 ~EP 16CLBsC

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    Figure 4a. An eight-bit counter with reset built with two 74-161 TTL devices. Notice that not all of the deviceconnections are used to implement the function required. A direct 74-series SUbstitution proves wasteful.Use only the logic required to implement the required function.

    L______________________________________________________________J __________________________________________________________________________________________________ --------MACROC8BC-RD MACROC8BC-RD MACROC4BC-RD

    Figure 4b. A better implementation of an eight-bit ripple-carry counter based on various macros from the XACT DevelopmentSystem. When designing with an LCA, an engineer can tailor his logic so that the LCA performs the required function with theminimum amount of logic.

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    N.....oU1

    0010023 5A

    CLOCK

    0010023 58

    CLOCKH ~RESETDIR a( RESET

    Figure Sa. The asynchronous design p ractices of 74-series TTL devices are discouraged. An asynchronous design is lessreliable and risk ier since it is unforgiving to unknown design conditions.

    0 0 0

    R R R

    Figure 5b. Synchronous design provides more relable operation.

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