Crystal-less™ PCIe Clock Generator Familyww1.microchip.com/downloads/en/DeviceDoc/Discera_DSC55X_PCIe... · PCIe Trend • PCIe initiated by Intel / PCISIG in 2001 -3GIO • Evolved

Crystal-less™ PCIe Clock Generator Family

Discera Confidential

PCIe Trend

• PCIe initiated by Intel / PCISIG in 2001 -3GIO

• Evolved to become an industry standard – Allows common IP design for transmit and receive among IC vendors

– Enabled proliferation into broad range of markets Other?

Consumer (Smart TV, Bluray,…)

2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Solid State Storage

PC / Graphics

Server / Workstation

Storage (SAN,NAS,DAS,…)

Networking (Routers,Switches,infrastructure, CPE,…)

Embedded (MFP, DVR, POS, STB, other Industrial & Medical, …)

PCISIG spec release << Gen.1 Gen.2 Gen.3 Gen.4 >>

Throughput per lane 2.5 Gbit/s 5 Gbit/s 8 Gbit/s 16 Gbit/s

Serial Reference Clock 100MHz 100MHz 100MHz ??

Discera Confidential 2

* Outputs maybe configured for other than 100MHz PCIe clocks, please check with factory for a suitable configuration

Crystal-lessTM Clock Generator Overview


Part Number

# of outputs

Highlights Specs Package Type

DSC556-03 2 • Industry Standard footprint • Widely used in CPE and Consumer applications • Drop-in compatible with DSC557-03

Gen.1 16-TSSOP 14-QFN

DSC557-03 2 • Industry Standard footprint, • widely used in Networking, CPE, Storage and Consumer applications • Drop-in compatible with DSC556-03

Gen.1 Gen.2 Gen.3

16-TSSOP 14-QFN

DSC557-04 3 • Widely used in Embedded and CPE applications • Two of the outputs are synchronous

Gen.1 Gen.2 Gen.3

20-QFN

DSC557-05 4 • Widely used in Networking, Enterprise Storage and Embedded applications • Two banks with two synchronous outputs per bank

Gen.1 Gen.2 Gen.3

20-QFN

DSC558-05 4

• Widely used in Networking and Embedded applications • Two banks with two synchronous outputs per bank

o First bank with two synchronous PCIe outputs o Second bank includes one PCIe clock and a 60MHz LVCMOS clock

Gen.1 Gen.2 Gen.3

20-QFN

Two Outputs crystal-less™ PCIe Clock Gen. • 16 TSSOP (DSC557-03, DSC556-03)

– Drop in replacement for quick wins

– Drops into IDT, Pericom, OnSemi & Cypress

• IDT: ICS557-03 (gen.1), IDT5V41065 (Gen.2) , IDT5V41235 (Gen.3)

• Pericom: PI6C557-03

• OnSemi: NB3N5573

• Cypress: CY24293

– In Production now (2 weeks leadtime)

• 14 QFN (DSC557-03, DSC556-03)

– Off the shelf Discera pinout - 100MHz only

• For multiple frequencies, refer to DSC20xx

– Small form factor for space limited apps • 70% space saving over 16 TSSOP

– 14 QFN, 3.2mm x 2.5 mm package outline

– In Production now (2 weeks leadtime)

First in the World Crystal-less™ PCIe Clock Generator Discera Confidential 4

Flexible configurations • Outputs can be configured to support beyond HCSL

– LVPECL and LVDS output format for FPGA and legacy interface

• Product is available in 100ppm or 50ppm options

– PCIe specifications calls for 300ppm

– PCIe clock generators generally use a 50ppm crystal

• Multiple temp ranges cover multitude of applications

DSC557-03

Packing

T: Tape & Reel

F I 0

Package

F: 14 QFN

S: 16-TSSOP

Temp Range

E:-20°C to 70°C

I: -40°C to 85°C

L: -40°C to 105°C

Stability

0: ±100ppm

1: ±50ppm

T

Output Format, Clk0+/-

1: LVCMOS

2: LVPECL

3: LVDS

4: HCSL

4 4 -

Output Format, Clk1+/-

1: LVCMOS

2: LVPECL

3: LVDS

4: HCSL

DSC557-03

Level Translator

LVPECL or LVDS format


Standard Pinout • DSC557-03, 16 TSSOP

– DROP IN replacement for OnSemi, IDT, Pericom, and Cypress

– BOM reduction; eliminates 1 Crystal, 3 caps, and 1 resistor

IDT557-03

+/-1% Accuracy First in the World Crystal-less™ PCIe Clock Generator


Competitive Landscape

1. Gen.2 Lower Integration Band: 10kHz < F < 1.5MHz

2. Gen.2 Upper Integration Band: 1.5MHz < F < Nyquist (50MHz)

3. Gen.3 PLL band: 2-4 MHz, CDR = 10MHz

4. Certain components on the PCIe link require LVPECL or LVDS interface instead of HCSL; Discera supports any of the listed formats.

• N/A = Data not specified in vendor’s datasheet

Parameter Discera DSC557-03

IDT ICS557-03, IDT5V41065 , IDT5V41235

Pericom PI6C557-03

On Semi NB3N3002

PCISIG SPECS

Current Consumption, mA 60 85 65 135

Phase Jitter (Gen.1), pS 8.5 28 N/A N/A 86 ps (max)

Phase Jitter (Gen.2)1, pS 0.5 0.7 N/A N/A 3 ps (max)

Phase Jitter (Gen.2)2, pS 1.8 1.8 N/A N/A 3.1 ps (max)

Phase Jitter (Gen.3)3, pS 0.15 0.48 N/A N/A 1pS (max)

External Crystal NO yes yes yes

Multiple Output Format Support4 HCSL, LVPECL,LVDS, CMOS HCSL HCSL HCSL

VDD range, V 2.25-3.6 3.12-3.46 3.0-3.6 3.0-3.6


DSC557-05 • Generates 4 PCIe clock outputs

– Two banks of two synchronous PCIe clocks per bank • Bank 0: CLK0 and CLK3

• Bank1: CLK1 and CLK2

• Compliant to PCI-SIG, Gen.1, Gen.2 and Gen.3 specs.

• Factory configurable output format – Eliminates level translators

• Saves BOM and board space – Eliminates external crystal component

– Eliminates tuning caps and resistor and bypass caps

• All benefits of MEMS applicable

• 5.0mm x 3.2mm, 20QFN package

• Sampling now

Four Outputs Crystal-less™ PCIe Clock Gen.

+/-1% Accuracy


Competitive Landscape Spec DSC557-05 ICS557-05 IDT5V41066 / 5V41236

PCIe support Gen 1/Gen 2/Gen 3 Gen 1 Gen 2 / Gen.3

External components

• • •2 supply decoupling caps •

• XTAL • XTAL tuning capacitors • 2 supply decoupling caps • Current steering resistor

•XTAL • XTAL tuning capacitors • 2 supply decoupling caps • CS resistor required

Operating voltage (V) 2.5/3.3 3.3 3.3

Operating current (mA) 120 (at VDD =3.3V)) 105 115

Space occupation (mm2) 16 55 55

Output format availability HCSL/LVDS/LVPECL/CMOS HCSL/LVDS HCSL/LVDS


DSC557-04 • Generates 3 PCIe clock outputs

– One bank of two synchronous PCIe clocks • Bank1: CLK1 and CLK2

• Compliant to PCI-SIG, Gen.1, Gen.2 and Gen.3 specs

• Factory configurable output format – Eliminates level translators

• Saves BOM and board space

– Eliminates external crystal component

– Eliminates tuning caps, bypass caps and tuning resistor

• All benefits of MEMS applicable

• 5.0mm x 3.2mm, 20QFN package

• Sampling now

Three Outputs Crystal-less™ PCIe Clock Gen.

+/-1% Accuracy


Applications Examples



Multi-Function Product Security / Surveillance

100MHz HCSL

100MHz HCSL

ARM

Processor

Video Monitor

Storage, SATA

Memory

DSC557-03

Ethernet

100MHz HCSL

PowerPC Processor

LAN

Print Engine controller

SATA controller

USB

Memory

Scan Engine controller

100MHz HCSL

100MHz HCSL

100MHz HCSL

48MHz Xtal

DSC557-05

25MHz Xtal



IP/ Home Gateway

38000

25MHz Xtal

ARM

network Processor

10/100 PHY

SATA cont.

USB

Memory

MoCA

PCIe WLAN

DSC557-04

100MHz HCSL

100MHz LVDS

100MHz LVDS

SAN Processor Unit

60MHz LVCMOS

MIPS network

Processor

Channel Controller

Memory

Cache Controller

RAID Controller

ASIC

DSC558-05

100MHz HCSL

100MHz LVPECL

PCIe



Clock Gen. + Oscillator solution

• Single device generates two PCIe clocks

• Single oscillator for peripheral clocks

Wireless AP

Gigabit PHY

Power PC Processor

PCIe Radio 1

66.667MHz CMOS

100MHz HCSL

DSC55x-05

100MHz HCSL

25MHz Xtal

Wireless AP

Gigabit PHY

Power PC Processor

PCIe Radio 1

66.667MHz CMOS

100MHz HCSL

DSC557-03

DSC10xx

100MHz HCSL

25MHz Xtal

Single Device Clock Gen. solution

• Single device generates all necessary clocks



Clock Gen. + Oscillator solution

• Mixed output format PCIe

– One HCSL, One LVDS

• Cross Selling with DSC2311 Clock Generator

VoIP Gateway

40MHz CMOS

ARM

network Processor

WiFi Controller

Gigabit PHY

USB

Memory

1 Port WLAN

FPGA

DSC557-03

100MHz HCSL

25MHz CMOSl

100MHz LVDS

1 Port WLAN DSC2311

VoIP Gateway

40MHz LVCMOS

ARM

network Processor

WiFi Controller

Gigabit PHY

USB

Memory

1 Port WLAN

FPGA

DSC55x-05

100MHz HCSL

25MHz LVCMOS

100MHz LVDS

1 Port WLAN

Single device clock gen. solution

• Single device generates all necessary clocks


Benefits of MEMS


Discera MEMS is PureSilicon™ Timing

• > 95% of old technologies have been replaced by silicon MEMS equivalents: – Applicable in automobiles, mobile phones, printers, projectors, and TV’s

• Discera is the first contributor to that change in timing space

MEMS Gyroscope

MEMS Microphone MEMS Printer Heads

MEMS Projectors and TV

Discera MEMS Timing


Discera’s Goal

from rocks….. to silicon

From mechanically cut crystals… …to reliable semiconductors


MEMS oscillators drop into standard oscillator footprints and offer advantages in performance, reliability, pricing, and time-to-market

Benefits of MEMS over Quartz

Quartz Crystal in Metal+Ceramic Package

MEMS in Plastic Package

MEMS in Chip Scale Package

Performance: Stability & Jitter

• Up to 10ppm stability across full temperature range

• Temperature grades up to 125C (vs. 85C) • Less than 0.5 ps phase noise jitter

Faster Time to Market

• 2 weeks production lead time vs.. 8-16 weeks for crystal

• Engineering prototypes programmable in 1 sec with full production performance

Cost Effective

• Semiconductor supply chain, without mechanical handling steps of crystal

• On CMOS pricing trend, scaling with chip geometry in Global, TSMC processes

Higher Reliability

• Full AEC-Q100, JEDEC qualification • 1.2 FIT reliability rates vs. 20 FIT for crystal • 50 000 G shock and 70 G vibration tolerance

(vs 200 G shock, 10 G vibration)


Size Advantage

MEMS meets your need for smaller components at lower cost

Man

ufa

ctu

rin

g C

ost

2.5 x 2.0 3.2 x 2.5 5.0 x 3.2 7.0 x 5.0 2.0 x 1.6 1.6 x 1.2

Quartz in Ceramic

MEMS in Plastic


Better Frequency Stability

Much tighter frequency stability across temperature

-20

-10

0

10

20

30

40

50

60

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Fre

qu

en

cy S

tab

ility

(P

PM

)

Temperature ( C)

Quartz 1

Quartz 2

Quartz 3

Discera


Best in Class Reliability

Discera MEMS Oscillators

Quartz Oscillators

Improvement over Quartz

Test Condition

MECHANICAL SHOCK

50,000G 100G 500 x MIL-STD-883; Method 2002

VIBRATION 70G 15G 4.6 x MIL-STD-883; Method 2007

FIT (Failure in Time)

1.2 29 24 x Confidence level = 90%

MTBF 1822MHr 90MHr 24 x Confidence level = 90%

DPPM < 10 100 10 x Over Production Lifetime


Appendix


Guidelines on PCIe implementation


PCISIG guidelines on PCIe clocks


Reference: PCISIG Clocks have no phase relationship

• Clock 0 and Clock 1 have no phase (skew) relationship requirements -

– Meaning: cross points of Clock0 and Clock1 can be skewed by any degree from each other

– Therefore, polarity of pins (8,9) and pins (10,11) does NOT matter

– Therefore, Clock 0 trace length and Clock 1 trace length do NOT have to be the same.

PCIe clock 0 = Clk0+ and Clk0-

PCIe clock 1 = Clk1+ and Clk1-


Reference: PCISIG Use same trace geometry as other differential pair

• All PCIe devices and connectors must get a PCIe clock to operate

• Clock 0 and Clock 1 can have same geometries as other differential traces on the board such as data or other types of differential clock; e.g. DOT clock, CPU clock, PCIe data lines, …. – Less burden on board designers – Similar trace width as other diff signals – Similar trace spacing between true(+) and complement(-)

as other diff signals – Similar trace thickness and dielectric as other diff signals


Layout Recommendations

• Distance between true and complement (S):

– S = 3*D minimum

– D is the thickness of the dielectric below trace layer

• Keep S constant along the entire route of the traces of the differential pair

• Distance between adjacent differential pairs (A)

– A= 2*S minimum

• Traces in the differential pair should be equal in length and width

– Length of true(+) = Length of complement (-)

– Width of true (+) = Width of complement (-)

– Minimizes skew and optimizes energy cancellation

Dielectric (D)

+ - + - S S A

PCB cross section


Routing Differential Clocks Highlights

Aggressor

• Ideally, true (+) and complement (-) signal paths should be matched.

• Same length • Same variations on corners and vias

•Shield from nearby aggressors on the same layer •Use ground traces for shielding

•Couples signals to ground instead of deterministic noise •Shields from cross talk

•Minimizes Skew • Better cross point stability • Lower emission

+ - + -

•VDD •Other clock •Active data signal


Inquire about Evaluation Boards

Two outputs PCIe clock generator

Power Supply connection

50 Ohms connectors

High impedance direct probe

30

Spread Spectrum Brief


Performance Impact of Spread Spectrum

A. Clock gain (Energy) peaks on center frequency

a) 100Mhz for PCIe

b) Receiver multiplies clock core frequency; >1GHz (10x100MHz)

Gain (dB)

Frequency (hz)

A.

100MHz

a)

No Spread

Gain (dB)

Frequency (hz) 100MHz

a)

99.75MHz

b)

-0.5% Spread

B.

B. Spread Spectrum adds controlled jitter

a) 0.5% down spread (Standard Spec) Shifts center frequency down by 0.25MHz

b) Receiver performance is degraded by > 2.5Mhz (10x.25MHz)


Differential Signals Cancel out Emission

• Differential signals – Composed of a true and a complementary pair

– True and complementary signals are 180° out of phase

– Data is clocked on the cross point– see ‘trigger’ in fig.1

– Adding signals at any point in time results in zero common mode energy – See fig.1 (a+/a-; b+/b-; c+/c-; d+/d-)

– Fig.2 shows energy emission for signals are not true differential • adding e+ to e- does not result in zero and causes radiation to peak.

True (Clk0+)

Compliment (Clk0-)

a+

a-

b+

b-

c+

c-

d+

d-

Trigger

e+

e-

Fig.1 Fig.2

Common Mode Energy a++a- = 0 b++b- = 0 c++c- = 0 d++d- = 0

e++e- >>0


DSC557-04

• PCIe Gen 1, Gen 2, and Gen 3 compliant

• Factory configurable output format:

• HCSL, LVPECL, LVDS, LVCMOS

• Wide Operating Temp. Range • Including 70, 85, 105 °C Options

• Wide Supply Voltage Range: 2.25 to 3.6 V

• Low Supply Current: as low as 42 mA

• Industry’s Highest Reliability • 1.2 FIT rate- (20x better than quartz based clocks) • Solid State Storage

• Storage Area Networks • Passive Optical Networks • Ethernet • Industrial and Medical • Consumer Electronics

Features

Sample Applications

• 2 weeks Production Leadtime

• Gen 1, Gen2 and Gen3 Compliant • Easy design porting

• No need to qual different device • Excellent Immunity to Shock and Vibration

• Supports high operating temperature (up to 105ºC)

Benefits


DSC557-05

• PCIe Gen 1, Gen 2, and Gen 3 compliant

• Factory configurable output format:

• HCSL, LVPECL, LVDS, LVCMOS

• Wide Operating Temp. Range • Including 70, 85, 105 °C Options

• Wide Supply Voltage Range: 2.25 to 3.6 V

• Low Supply Current: as low as 42 mA

• Industry’s Highest Reliability • 1.2 FIT rate- (20x better than quartz based clocks) • Solid State Storage

• Storage Area Networks • Passive Optical Networks • Ethernet • Industrial and Medical • Consumer Electronics

Features

Sample Applications

• 2 weeks Production Leadtime

• Gen 1, Gen2 and Gen3 Compliant • Easy design porting

• No need to qual different device • Excellent Immunity to Shock and Vibration

• Supports high operating temperature (up to 105ºC)

Benefits


Documents

Crystal-less™ PCIe Clock Generator Familyww1.microchip.com/downloads/en/DeviceDoc/Discera_DSC55X_PCIe... · PCIe Trend • PCIe initiated by Intel / PCISIG in 2001 -3GIO • Evolved