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CS 152 Computer Architecture
and Engineering
Lecture 18: Multithreading
Krste AsanovicElectrical Engineering and Computer Sciences
University of California, Berkeley
http://www.eecs.berkeley.edu/~krstehttp://inst.cs.berkeley.edu/~cs152
4/15/2008 2
CS152-Spring!08
Last Time: Vector Computers
• Vectors provide efficient execution of data-parallel loop codes
• Vector ISA provides compact encoding of machine parallelism
• ISAs scale to more lanes without changing binary code
• Vector registers provide fast temporary storage to reduce memorybandwidth demands, & simplify dependence checking between vectorinstructions
• Scatter/gather, masking, compress/expand operations increase set ofvectorizable loops
• Requires extensive compiler analysis (or programmer annotation) tobe certain that loops can be vectorized
• Full “long” vector support still only in supercomputers (NEC SX8R,Cray X1E); microprocessors have limited “short” vector operations
– Intel x86 MMX/SSE/AVX
– IBM/Motorola PowerPC VMX/Altivec
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Vector Conditional Execution
Problem: Want to vectorize loops with conditional code:for (i=0; i<N; i++)
if (A[i]>0) then
A[i] = B[i];
Solution: Add vector mask (or flag) registers– vector version of predicate registers, 1 bit per element
…and maskable vector instructions– vector operation becomes NOP at elements where mask bit is clear
Code example:
CVM # Turn on all elements
LV vA, rA # Load entire A vector
SGTVS.D vA, F0 # Set bits in mask register where A>0
LV vA, rB # Load B vector into A under mask
SV vA, rA # Store A back to memory under mask
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Masked Vector Instructions
C[4]
C[5]
C[1]
Write data port
A[7] B[7]
M[3]=0
M[4]=1
M[5]=1
M[6]=0
M[2]=0
M[1]=1
M[0]=0
M[7]=1
Density-Time Implementation
– scan mask vector and only executeelements with non-zero masks
C[1]
C[2]
C[0]
A[3] B[3]
A[4] B[4]
A[5] B[5]
A[6] B[6]
M[3]=0
M[4]=1
M[5]=1
M[6]=0
M[2]=0
M[1]=1
M[0]=0
Write data portWrite Enable
A[7] B[7]M[7]=1
Simple Implementation– execute all N operations, turn off result
writeback according to mask
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Compress/Expand Operations
• Compress packs non-masked elements from one vector registercontiguously at start of destination vector register
– population count of mask vector gives packed vector length
• Expand performs inverse operation
M[3]=0
M[4]=1
M[5]=1
M[6]=0
M[2]=0
M[1]=1
M[0]=0
M[7]=1
A[3]
A[4]
A[5]
A[6]
A[7]
A[0]
A[1]
A[2]
M[3]=0
M[4]=1
M[5]=1
M[6]=0
M[2]=0
M[1]=1
M[0]=0
M[7]=1
B[3]
A[4]
A[5]
B[6]
A[7]
B[0]
A[1]
B[2]
Expand
A[7]
A[1]
A[4]
A[5]
Compress
A[7]
A[1]
A[4]
A[5]
Used for density-time conditionals and also for generalselection operations
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Vector Reductions
Problem: Loop-carried dependence on reduction variables
sum = 0;
for (i=0; i<N; i++)
sum += A[i]; # Loop-carried dependence on sum
Solution: Re-associate operations if possible, use binary tree to performreduction
# Rearrange as:
sum[0:VL-1] = 0 # Vector of VL partial sums
for(i=0; i<N; i+=VL) # Stripmine VL-sized chunks
sum[0:VL-1] += A[i:i+VL-1]; # Vector sum
# Now have VL partial sums in one vector register
do {
VL = VL/2; # Halve vector length
sum[0:VL-1] += sum[VL:2*VL-1] # Halve no. of partials
} while (VL>1)
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Multimedia Extensions (aka SIMD extensions)
• Very short vectors added to existing ISAs for microprocessors
• Use existing 64-bit registers split into 2x32b or 4x16b or 8x8b
– This concept first used on Lincoln Labs TX-2 computer in 1957, with 36b datapathsplit into 2x18b or 4x9b
– Newer designs have 128-bit registers (PowerPC Altivec, Intel SSE2/3/4)
• Single instruction operates on all elements within register
16b 16b 16b 16b
32b 32b
64b
8b 8b 8b 8b 8b 8b 8b 8b
16b 16b 16b 16b
16b 16b 16b 16b
16b 16b 16b 16b
+ + + +4x16b adds
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Multimedia Extensions versus Vectors
• Limited instruction set:– no vector length control
– no strided load/store or scatter/gather
– unit-stride loads must be aligned to 64/128-bit boundary
• Limited vector register length:– requires superscalar dispatch to keep multiply/add/load units busy
– loop unrolling to hide latencies increases register pressure
• Trend towards fuller vector support inmicroprocessors
– Better support for misaligned memory accesses, compilers
– Support of double-precision (64-bit floating-point)
– New Intel AVX spec (announced April 2008), 256b vector registers(expandable up to 1024b)
Multithreading
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Multithreading
• Difficult to continue to extract instruction-levelparallelism (ILP) or data-level parallelism (DLP) froma single thread
• Many workloads can make use of thread-levelparallelism (TLP)
– TLP from multiprogramming (run independentsequential jobs)
– TLP from multithreaded applications (run one jobfaster using parallel threads)
• Multithreading uses TLP to improve utilization of asingle processor
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Pipeline Hazards
• Each instruction may depend on the next
LW r1, 0(r2)
LW r5, 12(r1)
ADDI r5, r5, #12
SW 12(r1), r5
F D X M W
t0 t1 t2 t3 t4 t5 t6 t7 t8
F D X M WD D D
F D X M WD D DF F F
F DD D DF F F
t9 t10 t11 t12 t13 t14
What can be done to cope with this?
– interlocks (slow)
– or bypassing (needs hardware, doesn’t help allhazards)
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Multithreading
How can we guarantee no dependencies betweeninstructions in a pipeline?
-- One way is to interleave execution of instructionsfrom different program threads on same pipeline
F D X M W
t0 t1 t2 t3 t4 t5 t6 t7 t8
T1: LW r1, 0(r2)
T2: ADD r7, r1, r4
T3: XORI r5, r4, #12
T4: SW 0(r7), r5
T1: LW r5, 12(r1)
t9
F D X M W
F D X M W
F D X M W
F D X M W
Interleave 4 threads, T1-T4, on non-bypassed 5-stage pipe
Prior instruction ina thread alwayscompletes write-back before nextinstruction insame thread readsregister file
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CDC 6600 Peripheral Processors(Cray, 1964)
• First multithreaded hardware
• 10 “virtual” I/O processors
• Fixed interleave on simple pipeline
• Pipeline has 100ns cycle time
• Each virtual processor executes one instruction every 1000ns
• Accumulator-based instruction set to reduce processor state
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Simple Multithreaded Pipeline
• Have to carry thread select down pipeline to ensure correct state bits
read/written at each pipe stage
• Appears to software (including OS) as multiple, albeit slower, CPUs
+1
2 Thread
select
PC1
PC1
PC1
PC1
I$ IRGPR1GPR1GPR1GPR1
X
Y
2
D$
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Multithreading Costs
• Each thread requires its own user state– PC
– GPRs
• Also, needs its own system state– virtual memory page table base register
– exception handling registers
• Other costs?– Additional cache/TLB conflicts from competing threads
– Or larger cache/TLB capacity
– More OS overhead to schedule more threads
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Thread Scheduling Policies
• Fixed interleave (CDC 6600 PPUs, 1964)
– Each of N threads executes one instruction every N cycles
– If thread not ready to go in its slot, insert pipeline bubble
• Software-controlled interleave (TI ASC PPUs, 1971)
– OS allocates S pipeline slots amongst N threads
– Hardware performs fixed interleave over S slots, executing whicheverthread is in that slot
• Hardware-controlled thread scheduling (HEP, 1982)
– Hardware keeps track of which threads are ready to go
– Picks next thread to execute based on hardware priority scheme
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Denelcor HEP(Burton Smith, 1982)
First commercial machine to use hardware threading in main CPU
– 120 threads per processor
– 10 MHz clock rate
– Up to 8 processors
– precursor to Tera MTA (Multithreaded Architecture)
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Tera MTA (1990-97)
• Up to 256 processors
• Up to 128 active threads per processor
• Processors and memory modules populate a sparse3D torus interconnection fabric
• Flat, shared main memory– No data cache
– Sustains one main memory access per cycle per processor
• GaAs logic in prototype, 1KW/processor @ 260MHz– CMOS version, MTA-2, 50W/processor
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MTA Pipeline
A
W
C
W
M
Inst Fetch
Me
mo
ry P
oo
lRetry Pool
Interconnection Network
Wri
te P
oo
lW
Memory pipeline
Issue Pool• Every cycle, oneVLIW instruction fromone active thread islaunched into pipeline
• Instruction pipeline is21 cycles long
• Memory operationsincur ~150 cycles oflatency
Assuming a single thread issues oneinstruction every 21 cycles, and clockrate is 260 MHz…
What is single-thread performance?
Effective single-thread issue rateis 260/21 = 12.4 MIPS
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CS152 Administrivia
• Make sure to get updated lab5 descriptions
• Quiz results on Thursday
• Tilera multicore chip talk tomorrow (4/16) by AnantAgarwal (MIT/Tilera), 3108 Etcheverry, 2:30pm-4pm
– Tilera chip has 64 cores on one chip
– Each core is a 3-issue VLIW
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Coarse-Grain Multithreading
Tera MTA designed for supercomputing applicationswith large data sets and low locality
– No data cache
– Many parallel threads needed to hide large memory latency
Other applications are more cache friendly
– Few pipeline bubbles when cache getting hits
– Just add a few threads to hide occasional cache misslatencies
– Swap threads on cache misses
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MIT Alewife (1990)
• Modified SPARC chips– register windows hold different thread
contexts
• Up to four threads per node
• Thread switch on local cache miss
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IBM PowerPC RS64-IV (2000)
• Commercial coarse-grain multithreading CPU
• Based on PowerPC with quad-issue in-order five-stage pipeline
• Each physical CPU supports two virtual CPUs
• On L2 cache miss, pipeline is flushed and executionswitches to second thread
– short pipeline minimizes flush penalty (4 cycles), smallcompared to memory access latency
– flush pipeline to simplify exception handling
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Simultaneous Multithreading (SMT)for OoO Superscalars
• Techniques presented so far have all been “vertical”multithreading where each pipeline stage works onone thread at a time
• SMT uses fine-grain control already present insidean OoO superscalar to allow instructions frommultiple threads to enter execution on same clockcycle. Gives better utilization of machine resources.
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For most apps, most execution unitslie idle in an OoO superscalar
From: Tullsen, Eggers, and Levy,
“Simultaneous Multithreading:Maximizing On-chip Parallelism”,ISCA 1995.
For an 8-way
superscalar.
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Superscalar Machine Efficiency
Issue width
Time
Completely idle cycle
(vertical waste)
Instruction
issue
Partially filled cycle,
i.e., IPC < 4
(horizontal waste)
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Vertical Multithreading
• What is the effect of cycle-by-cycle interleaving?– removes vertical waste, but leaves some horizontal waste
Issue width
Time
Second thread interleaved
cycle-by-cycle
Instruction
issue
Partially filled cycle,
i.e., IPC < 4
(horizontal waste)
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Chip Multiprocessing (CMP)
• What is the effect of splitting into multiple processors?– reduces horizontal waste,
– leaves some vertical waste, and
– puts upper limit on peak throughput of each thread.
Issue width
Time
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Ideal Superscalar Multithreading[Tullsen, Eggers, Levy, UW, 1995]
• Interleave multiple threads to multiple issue slots withno restrictions
Issue width
Time
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O-o-O Simultaneous Multithreading[Tullsen, Eggers, Emer, Levy, Stamm, Lo, DEC/UW, 1996]
• Add multiple contexts and fetch engines and allow
instructions fetched from different threads to issue
simultaneously
• Utilize wide out-of-order superscalar processor issue
queue to find instructions to issue from multiple threads
• OOO instruction window already has most of the
circuitry required to schedule from multiple threads
• Any single thread can utilize whole machine
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IBM Power 4
Single-threaded predecessor to
Power 5. 8 execution units in
out-of-order engine, each may
issue an instruction each cycle.
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Power 4
Power 5
2 fetch (PC),2 initial decodes
2 commits(architectedregister sets)
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Power 5 data flow ...
Why only 2 threads? With 4, one of the sharedresources (physical registers, cache, memorybandwidth) would be prone to bottleneck
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Changes in Power 5 to support SMT• Increased associativity of L1 instruction cache and
the instruction address translation buffers
• Added per thread load and store queues
• Increased size of the L2 (1.92 vs. 1.44 MB) and L3caches
• Added separate instruction prefetch and buffering perthread
• Increased the number of virtual registers from 152 to240
• Increased the size of several issue queues
• The Power5 core is about 24% larger than thePower4 core because of the addition of SMT support
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Pentium-4 Hyperthreading (2002)
• First commercial SMT design (2-way SMT)– Hyperthreading == SMT
• Logical processors share nearly all resources of thephysical processor
– Caches, execution units, branch predictors
• Die area overhead of hyperthreading ~ 5%
• When one logical processor is stalled, the other canmake progress
– No logical processor can use all entries in queues when two threadsare active
• Processor running only one active software thread runsat approximately same speed with or withouthyperthreading
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SMT adaptation to parallelism type
For regions with high thread levelparallelism (TLP) entire machinewidth is shared by all threads
Issue width
Time
Issue width
Time
For regions with low thread levelparallelism (TLP) entire machinewidth is available for instruction levelparallelism (ILP)
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Initial Performance of SMT
• Pentium 4 Extreme SMT yields 1.01 speedup forSPECint_rate benchmark and 1.07 for SPECfp_rate
– Pentium 4 is dual threaded SMT
– SPECRate requires that each SPEC benchmark be run against avendor-selected number of copies of the same benchmark
• Running on Pentium 4 each of 26 SPEC benchmarkspaired with every other (262 runs) speed-ups from 0.90to 1.58; average was 1.20
• Power 5, 8-processor server 1.23 faster forSPECint_rate with SMT, 1.16 faster for SPECfp_rate
• Power 5 running 2 copies of each app speedupbetween 0.89 and 1.41
– Most gained some
– Fl.Pt. apps had most cache conflicts and least gains
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Power 5 thread performance ...
Relative priorityof each threadcontrollable inhardware.
For balancedoperation, boththreads runslower than ifthey “owned”the machine.
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Icount Choosing Policy
Why does this enhance throughput?
Fetch from thread with the least instructions in flight.
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Summary: Multithreaded Categories
Tim
e (p
roce
ssor
cyc
le) Superscalar Fine-Grained Coarse-Grained Multiprocessing
Simultaneous
Multithreading
Thread 1
Thread 2
Thread 3
Thread 4
Thread 5
Idle slot
4/15/2008 41
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Acknowledgements
• These slides contain material developed andcopyright by:
– Arvind (MIT)
– Krste Asanovic (MIT/UCB)
– Joel Emer (Intel/MIT)
– James Hoe (CMU)
– John Kubiatowicz (UCB)
– David Patterson (UCB)
• MIT material derived from course 6.823
• UCB material derived from course CS252