CSCE 212Chapter 5

The Processor: Datapath and Control

Instructor: Jason D. Bakos

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Goal

• Design a CPU that implements the following instructions:– lw, sw– add, sub, and, or, slt– beq, j

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Datapath

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Instruction Fetch Datapaths

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Register File and ALU

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BEQ Datapath

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Load, Store, and R-type Datapath

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Combined Datapaths

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ALU Control

• ALU performs function based on 4-bit ALU_operation input• Add a lookup table that instructs ALU to perform:

– add (for LW, SW), or– subtract (for BEQ), or– perform operation as dictated by R-type function code

Instruction opcode ALUOp InstructionFunct field

Desired ALU action

ALU control input

LW 00 add 0010

SW 00 add 0010

BEQ 01 subtract 0110

R-type 10 add 100000 add 0010

R-type 10 sub 100010 subract 0110

R-type 10 and 100100 and 0000

R-type 10 or 100101 or 0001

R-type 10 slt 101010 set on less than 0111

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MIPS Datapath

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MIPS Datapath with Control

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MIPS Datapath with Jump

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Single-Cycle

• This is a single-cycle implementation• Each instruction is executed within one clock cycle

– Must be set for worst-case delay (LW)

Instruction class

Functional units used

Instruction fetch

Register read ALU

Memory access

Register write

R-type X X X X

LW X X X X X

SW X X X X

BEQ X X X

J X

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Multicycle Implementation

• Break instruction execution into a sequence of steps– Adjust cycle time to be long enough to perform one basic operation

• fetch, register read, ALU, memory access, register write

– Must add registers to carry computed values from one cycle to next– Still can perform independent operations in parallel, i.e.:

• fetch instruction and compute next PC address• read registers and compute branch address

– Allows us to re-use ALU

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Multicycle MIPS Implementation

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Multicycle Control

• Instruction fetch– Information available: PC– Performed for all instructions– RTL:

• IR <= Memory[PC];• PC <= PC + 4;

• Instruction decode and register fetch– Information available: PC, instruction– Performed for all instructions– RTL:

• A <= Reg[IR[25:21]];• B <= Reg[IR[20:16]];• ALUOut <= PC + (sign-extend(IR[15:0]) << 2);

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Multicycle Control

• Execution, memory address computation, or branch completion– Information available: PC, instruction, (rs), (rt), (ALUOut)

– Memory reference:• ALUOut <= A + sign-extend(IR[15:0]);

– Arithmetic-logical instruction (R-type):• ALUOut <= A op B;

– Branch:• if (A == B) PC <= ALUOut;

– Jump:• PC <= {PC[31:28], IR[25:0], “00”};

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Multicycle Control

• Memory access or R-type completion step– Information available: PC, instruction, (rs), (rt), (ALUOut)

– Load:• MDR <= Memory[ALUOut];

– Store:• Memory[ALUOut] <= B;

– Arithmetic-logical instruction (R-type):• Reg[IR[15:11]] <= ALUOut;

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Multicycle Control

• Memory read completion step– Information available: PC, instruction, (rs), (rt), (ALUOut),

(MDR)

– Load:• Reg[IR[20:16]] <= MDR;

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Multicycle Control

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Adding Datapaths and Control

• How to add these instructions:

– addi rt, rs, imm

– bgtz rs, target

– bgtzal rs, target

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Exceptions and Interrupts

• Events other than branches or jumps that change the normal flow of instruction execution– Examples:

• I/O device request (external, interrupt)• System call (internal, exception)• Arithmetic overflow (internal, exception)• Invalid instruction (internal, exception)• Hardware malfunction (internal or external, exception or interrupt)

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Interrupts and Exceptions

• What to do?– Execute code in response

to event (handler)• Save PC (EPC reg,)• Record cause (Cause reg.)• Set new PC (4)

– Return from handler• Restore PC• Enable e/i (shift Status reg.)

• Determining type of exception– Use vectored exceptions

• Infer type from address

– Use polled exceptions• Use Cause register• This is what MIPS does

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Example Implementation

• Example:– Use polled approach– All exceptions and interrupts jump to single handler at address

8000 0180– The cause is recorded in the cause register– The address of affected instruction is stored in EPC

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Example Implementation

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Example Implementation