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N ew York Institute ofTechnology Engineering and C om puterSciences CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

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Page 1: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660

CSCI-660

Introduction to VLSI Design

Khurram Kazi

Page 2: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 2

Course Outline

Overview of ASIC design flow VHDL targeted for Synthesis Synthesis

Constraining and Optimizing Design Area and Timing reports

Verification Self Checking Design Verification Concepts Behavioral modeling for Test Benches in VHDL SystemC

Verilog for Synthesis Gate Level Verification

Page 3: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 3

Recommended Books + useful links

1. HDL Programming Fundamentals; VHDL and Verilog, Nazeih, B. Botros, Da Vinci Engineering Press, 2006, ISBN: 1-58450-855-8

2. The Designer's Guide to VHDL (2nd edition), ISBN 978-1-55860-674-6, Publisher: Morgan Kaufman, May 2001

3. Verilog HDL, Samir Palnitkar, 2nd Edition, SunSoft Press; A Prentice Hall Title, 2003, ISBN: 0-13-044911-3

4. Verification Methodology Manual for SystemVerilog (Hardcover), by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale, Springer; 1 edition (September 28, 2005), ISBN-10: 0387255389

5. Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®, Himanshu Bhatnagar, Kluwer Academic Publishers, 2nd Edition, ISBN: 0-7923-7644-7

http://ece.gmu.edu/courses/ECE545/index.htmThis webpage has tons of useful information!!Go over the ModelSim content as we will be using it as the simulator

Page 4: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 4

Tools used in the courseMentor Graphics ModelSim

VHDL simulatorVerilog simulatorSystem Verilog simulator

SynopsysSynthesis toolStatic Timing Analysis

Remote access to our tools is available Please send an email to Mike [email protected] for remote access account

Page 5: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 5

Grading Policy

Homework /Short Quizzes 30% 1 Midterm Test 30% Final Project 40% Final Projects will be customized to your field of

specialization, may it be in Data Networking, Cryptography, Specialized Arithmetic Operations, DSP, Computer Architecture etc.

Oral and written communication skills will be stressed in this course and taken into account for the final grade

Page 6: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 6

Do’s and Don’ts for the Final Project

DO NOT use any off the shelf general purpose microprocessor or any other circuit taken from the publicly available information base. I will know if you did!!

Come up with your own functional idea and Implement it. Be creative! Have a system’s perspective and see how your design fits in the system.

By mid semester have a good idea of your project

Team of 2 students working on the same project is allowed. Each team member’s task within the project should

be explicitly defined.

Page 7: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 7

Teamwork Encouraged: How much collaboration is acceptable

Since time will be short, I would encourage you to help out your fellow students with the “Usage of the Tools” but not the Design. Informing me of the help received is strongly encouraged, i.e. give credit where credit is due!!

Helping fellow students with Tools usage and class participation will be rewarded in the final grade.

Page 8: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 8

Where to Start in the ASIC Process!

Begin with ASIC (Application Specific Integrated Circuit) Specification

Most likely by the time you are done with the design the Final Spec. will be quite different than the original ideas

Based on performance and functional requirements define operating frequencies, I/O pad types, operating conditions, verification and test requirements to ensure error free design and manufacturability of it

Page 9: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 9

Implication of the Designs we work on; keep few things in mind!

During the design process we always make trade-offs

Trade-offs can be based on time to market, cost implications, complexity, environmental considerations etc.

Ethics: Keep in mind the implications of what you are designing, how it impacts the society!!

Digital designs inherently deal with Implementing approximate solutions Power consumption considerations: Making the

Designs Green; Environmental friendly!! Cost/performance trade-offs

Page 10: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 10

Implication of the Designs we work on; keep few things in mind!

Few bad approximations lead to

Example: Failure of Patriot Missile (1991 Feb. 25) Source http://www.math.psu.edu/dna/455.f96/disasters.html American Patriot Missile battery in Dharan, Saudi Arabia, failed to

intercept incoming Iraqi Scud missile The Scud struck an American Army barracks, killing 28

Cause, per GAO/IMTEC-92-26 report: “software problem” (inaccurate calculation of the time since boot)

Specifics of the problem: time in tenths of second as measured by the system’s internal clock was multiplied by 1/10 to get the time in seconds Internal registers were 24 bits wide 1/10 = 0.0001 1001 1001 1001 1001 100 (chopped to 24 b) Error @ 0.1100 1100 ´ 2 –23 @ 9.5 ´ 10 –8 Error in 100-hr operation period @ 9.5 ´ 10 –8 ´ 100 ´ 60 ´ 60 ´ 10 = 0.34 s

Distance traveled by Scud = (0.34 s) ´ (1676 m/s) @ 570 m, this put the Scud outside the Patriot’s “range gate”. Ironically, the fact that the bad time calculation had been improved in some (but not all) code parts contributed to the problem, since it meant that inaccuracies did not cancel out

Page 11: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 11

Implication of the Designs we work on; keep few things in mind!

Few bad approximations lead to

Example: Explosion of Ariane Rocket (1996 June 4) Source http://www.math.psu.edu/dna/455.f96/disasters.html Unmanned Ariane 5 rocket launched by the European Space

Agency veered off its flight path, broke up, and exploded only 30 seconds after lift-off (altitude of 3700 m). The $500 million rocket (with cargo) was on its 1st voyage after a decade of development costing $7 billion

Cause: “software error in the inertial reference system” Specifics of the problem: a 64 bit floating point number

relating to the horizontal velocity of the rocket was being converted to a 16 bit signed integer

An SRI* software exception arose during conversion because the 64-bit floating point number had a value greater than what could be represented by a 16-bit signed integer (max 32 767)

Page 12: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 12

Overview of some of the steps in an ASIC design flow

Chip Specification

Chip Architecture

RTL CodeDevelopment

Verification Environment/Code Development

Blocks Integration -> ASIC

Testability CircuitInsertion (JTAG & Scan)

Block LevelSynthesis

ASIC level Verification (selfcheckingreference models)

HardwareFlow

VerificationFlow

I/O Pads Insertion

Floor Plan

Place and Route

Vendor defined Processingfor design Handoff

Gate levelVerification,Functional

Vectors, andtestability

vectors (Usingpre and thenPost layout

timingsimulation)

RTL code implies synthesizable HDL code

Page 13: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 13

RTL Block Synthesis*

Write RTL HDLCode

SimulateOK

Synthesize RTLCode to Gates

ConstraintsMet?

Gate LevelTesting

OK?

HDL

No

Yes

Gate LevelNetlist

No

Yes

No

Yes

Proceed withBackend

Processing

*Simplified design flow

Page 14: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 14

Insert Test Structure (Internal Scan and JTAG)*

*Simplified design flow

Chip level Netlist

Insert InternalScan

ConstraintsMet?

No

Yes

Proceed withBackend

Processing

Insert JTAG Scan(boundary scan)

Re-Optimize

Note that we will not cover JTAG or insertion of the boundary scan in this class

Page 15: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 15

Insert Test Structure (Internal Scan and JTAG)*

*Simplified design flow

Chip level Netlist

Insert InternalScan

ConstraintsMet?

No

Yes

Proceed withBackend

Processing

Insert JTAG Scan(boundary scan)

Re-Optimize

JTAGController

Note that we will not cover JTAG or insertion of the boundary scan in this class

Page 16: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 16

Insert I/O Pads*

*Simplified design flow

Insert I/O Pads

ConstraintsMet?

No

Yes

Proceed withBackend

Processing

Re-Optimize

JTAGController

Page 17: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 17

ASIC Floorplan*

*Simplified design flow

ASIC netlist

ConstraintsMet?

No

Yes Proceed withPlace and Route

Re-Optimize

JTAG Controller

SERDES

BufferRAM

DataPath

QueueManager

Scheduler

ASIC Core

Floorplan Design

Back AnnotationRC’s Timing,

Physical Hierarchy

Page 18: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 18

Getting ASIC Ready for Handoff*

*Simplified design flow

ASIC netlist

ATPG

Vector Formating

Vector Simulation

Gate LevelSimulation and or

Static timing analysis

Tape Out

Continue simulationwhile waiting for

Prototypes to comeback. Prepare test

boards, take avacation. TestingASIC is a task by

itself!

Page 19: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 19

Brief History of VHDL

VHDL is a language used for designing and simulating digital hardware. It has been adopted by the electronics industry worldwide. Another Language that is also widely used is VerilogVHDL is an acronym for VHSIC (Very High

Speed Integrated Circuit) Hardware Description

Language VHDL originally was used for specifications Subsequently was used for simulating designs Finally its scope evolved into its usage for

synthesizing digital designs

Page 20: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 20

Levels of Abstraction

Slide taken from K.Gaj lectures at GMU

Algorithmic level

Register Transfer Level

Logic (gate) level

Circuit (transistor) level

Physical (layout) level

Level of description

most suitable for synthesis

Page 21: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 21

Register Transfer Logic (RTL)

Slide taken from K.Gaj lectures at GMU

Combinational Logic

Combinational Logic

Registers

Page 22: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 22

Levels at which VHDL can be used

Slide taken from K.Gaj lectures at GMU

VHDL for Simulation

VHDL for Synthesis

VHDL for Specification

Page 23: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 23

Typical HDL Design Environment

Testbench (GeneratorIn C or HDL)

Testbench (AnalyzerIn C or HDL)

HDL Design

(VHDL or Verilog

Reference Model( In C or Functional HDL)

HDL (Hardware Description Language) can typically be either VHDL or Verilog

Page 24: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 24

Overview of VHDL

Library and Library Declarations Entity DeclarationArchitectureConfiguration

Page 25: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 25

Overview of VHDL

Package (typically compiled into the destination library) contains commonly used declarationsConstants maybe defined hereEnumerated data types (Red, Green, Blue)Combinatorial functions (performing a

decode function; returns single value)Procedures (can return multiple values)Component declarations

Page 26: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 26

Overview of VHDL: Example of Library Declaration

LIBRARY library_name; --commentsUSE library_name.package_name.package_parts; -- VHDL is case

-- insesitiveTypically there are three different libraries used in a design1) ieee.std_logic_1164 (from the ieee library)2) standard (from the std library)3) work (work library) std_logic_1164: Specifies the STD_LOGIC (8 levels) and the

STD_ULOGIC (9 levels) multi-values logic systems std: It is a resource library (data types, text i/o, etc.) work: This is where the design is saved

Library ieee; -- A semi-colon (;) indicates the end of a statement or a declaration

USE ieee.std_logic_1164.all; -- double dash indicates a comment.

Library std;USE std.standard.all;

Library work;USE work.all;

Page 27: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 27

Overview of VHDL: Entity

EntityDefines the component name, its inputs and

outputs (I/Os) and related declarations. Can use same Entity for different architecture

to study various design trade offs.Use std_logic and std_logic_vector(n downto 0):

they are synthesis friendly.Avoid enumerated type of I/Os. Avoid using port type buffer or bidir (unless you have

to)

Page 28: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 28

Overview of VHDL: Syntax of an Entity

1. ENTITY entity_name ISPORT (

port_name : signal_mode signal type;port_name : signal_mode signal type;……….);

END entity_name;

2. ENTITY nand_gate ISPORT ( a: IN std_logic; b: IN std_logic; x: OUT std_logic);

END nand_gate;or3. ENTITY FiveInput_nand_gate IS

PORT ( a: IN std_logic_vector (4 downto 0); x: OUT std_logic);

END FiveInput_nand_gate;

Page 29: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 29

Overview of VHDL: Architecture

ArchitectureDefines the functionality of the designNormally consists of processes and concurrent

signal assignmentsSynchronous and/or combinatorial logic can be

inferred from the way functionality is defined in the Processes.

Avoid nested loopsAvoid generate statements with large indices Always think hardware when developing code! One way of looking at is how would you implement the digital

design on the breadboard; mimic the same thought process in writing VHDL code

Page 30: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 30

Overview of VHDL: Syntax of an Architecture

ARCHITECTURE architecture_name OF entity_name IS[declarations]

BEGIN(code)

END architecture_name;

ARCHITECTURE myarch OF nand_gate ISBEGIN

x <= a NAND b;END myarch;

Page 31: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 31

Overview of VHDL: Basic Components of an

Architecture

Primarily Architecture consists of Process Concurrent Statements

Code in VHDL is inherently concurrent (parallel) All processes and concurrent statements are evaluated in parallel (i.e.

at the same time) Code inside the process is executed sequentially

The code execution is based on sensitivity list (signals that act as triggers in the execution of the respective process

Process can describe Asynchronous (combinatorial logic) Synchronous (clocked logic)

Concurrent Statements Typically combinatorial logic is implemented using concurrent

statements

Page 32: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 32

Separation of Combinatorial and Sequential Logic

Encoder

Data1

Data2

Clk

Reset_n

Q

Library IEEE;use IEEE.std_logic_1164;entity Sample1;port (Data1, Data2, Clk : std_logic; Q : out std_logic);end Sample1;

architecture Conceptual of Sample1 issignal data: std_logic_vector (3 downto 0);begin

combinatorial : process (Data1, Data2) begin DATA <= Encoder (Data1, Data2);end process combinatorial;

Sequential : process (clk, Reset_n) begin if (Reset_n = ‘0’) the Q <= ‘0’; else if (clk’event and clk = ‘1’) then Q <= DATA; end if; end if;end process Sequential;

end Conceptual;

Signals within the sensitivity list

Page 33: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 33

Case statement SynthesisD

COUT1

Library IEEE;use IEEE.std_logic_1164;

entity UsingCase;port (A, B, C : in std_logic; SEL : in std_logic_vector (2:0); Out1 : out std_logic);end UsingCase;

architecture Conceptual of UsingCase isbegin

CaseStat : process (A, B, C, D, SEL) begin

case SEL is when “00” => OUT1 <= A; when “01” => OUT1 <= B; when “10” => OUT1 <= C; when “11” => OUT1 <= D;

end process CaseStat;

end Conceptual;

SEL[1:0]

11

10

Using of Case statement to infer a MUX

ACTUAL SYNTHESIS OF LOGIC IS TOOL ANDVENDOR’s LIBRARY DEPENDENT

B

A

01

00

Page 34: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 34

Synthesis of “if – then – elsif” statement

D

C

OUT1

Library IEEE;use IEEE.std_logic_1164;entity PriorityEncoding;port (A, B, C : in std_logic; SEL : in std_logic_vector (2:0); Out1 : out std_logic);end PriorityEncoding;

architecture Conceptual of PriorityEncoding is

begin

Encoding : process (A, B, C, D, SEL) begin if (SEL(2) = ‘1’) then Out1 <= A;elsif (SEL(1) = ‘1’) then Out1 <= B;elsif (SEL(0) = ‘1’) then Out1 <= C;else Out1 <= D;end if;end process Encoding;

end Conceptual;

SEL[2:0]SEL[0] = ‘1’

0

1

0

1B

SEL[1] = ‘1’0

1A

SEL[2] = ‘1’

If - then - elsif statements infer priority encoding“cascade of MUXs”.

ACTUAL SYNTHESIS OF LOGIC IS TOOL ANDVENDOR’s LIBRARY DEPENDENT

Page 35: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 35

Overview of VHDL

ConfigurationPrimarily used during the simulations

If there are multiple architectures for the same entity, the “configuration” can be used to instruct the simulator which architecture should be used during the simulation.

Page 36: CSCI 660 CSCI-660 Introduction to VLSI Design Khurram Kazi

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660 36

Some useful practices

Organize Your Design WorkspaceDefine naming convention (especially if

multiple designers are on the projectCompletely Specify Sensitivity ListsTry to separate combinatorial logic from

sequential logic