Slide 1

CSE 8383 - Advanced Computer Architecture Week-4 Week of Feb 2, 2004 engr.smu.edu/~rewini/8383 Slide 2 Contents Reservation Table Latency Analysis State Diagrams MAL and its bounds Delay Insertion Throughput Group Work Introduction to Multiprocessors Slide 3 Reservation Table A reservation table displays the time- space flow of data through the pipeline for one function evaluation A static pipeline is specified by a single reservation table A dynamic pipeline may be specified by multiple reservation tables Slide 4 Static Pipeline X X X X S1 S2 S3 S4 Time Slide 5 Dynamic Pipeline XXX XX XXX YY Y YYY S1 S2 S3 S1 S2 S3 Slide 6 Reservation Table (Cont.) The number of columns in a reservation table is called the evaluation time of a given function. The checkmarks in a row correspond to the time instants (cycles) that a particular stage will be used. Multiple checkmarks in a row repeated usage of the same stage in different cycles Slide 7 Reservation Table (Cont.) Contiguous checkmarks extended usage of a stage over more than one cycle Multiple checkmarks in one column multiple stages are used in parallel A dynamic pipeline may allow different initiations to follow a mix of reservation table Slide 8 Reservation Table 1234567 AXXX BXX CXX DX Slide 9 Latency Analysis The number of cycles between two initiations is the latency between them A latency of k two initiations are separated by k cycles Collision resource conflict between two initiations Latencies that cause collision forbidden latencies Slide 10 Collision with latency 2 & 5 in evaluating X X1X2X1X2 X1 X1X2 X1X2 X1X2 X1 S1 S2 S3 X1X2 X1X1 X2 X1 X2 S1 S2 S3 5 2 Slide 11 Latency Analysis (cont.) Latency Sequence a sequence of permissible latencies between successive initiations Latency Cycle a latency sequence that repeats the same subsequence (cycle) indefinitely Latency Sequence 1, 8 Latencies Cycle (1,8) 1, 8, 1, 8, 1, 8 Slide 12 Latency Analysis (cont.) Average Latency (of a latency cycle) sum of all latencies / number of latencies along the cycle Constant Cycle One latency value Objective Obtain the shortest average latency between initiations without causing collisions. Slide 13 Latency Cycle (1,8) 123456789101112131415161718192021 X1X1 X2X2 X1X1 X2X2 X1X1 X2X2 X3X3 X4X4 X3X3 X4X4 X3X3 X4X5X5 X6X6 X1X1 X2X2 X1X1 X2X2 X3X3 X4X4 X3X3 X4X4 X5X5 X6X6 X1X1 X2X2 X1X1 X2X2 X1X1 X2X2 X3X3 X4X4 X3X3 X4X4 X3X3 X4X4 X5X5 Average Latency = (1+8)/2 = 4.5 Slide 14 Latency Cycle (6) 123456789101112131415161718192021 X1X1 X1X1 X2X2 X1X1 X2X2 X3X3 X2X2 X3X3 X4X4 X3X3 X1X1 X1X1 X2X2 X2X2 X3X3 X3X3 X4X4 X1X1 X1X1 X1X1 X2X2 X2X2 X2X2 X3X3 X3X3 X3X3 X4X4 Average Latency = 6 Slide 15 Collision Vector C = (C m, C m-1, , C 2, C 1 ) C i = 1 if latency i causes collision (forbidden) C i = 0 if latency i is permissible C m = 1 (always) maximum forbidden latency Maximum forbidden latency: m