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1 | P a g e pnkondekar/resume/May2015
Curriculum Vitae
1) Name: Pravin Neminath Kondekar
2) Father’s Name Neminath Babaorao Kondekar
3) Present Postal Address A-203 Swami Sadan Apartments
Above Yes Bank, GPO Square,
Civil Lines, Nagpur-440 001
Telephone: (R) +91-712-2533915
4) Email: [email protected], [email protected]
5) Telephone a) Mobile (91-9425805445) b) Land Line (0761-2632236) c) Fax: (0761-2632524)
6) Nationality Indian
7) Date of Birth 10th
March 1961
8) Educational Qualifications
Degree
(Subjects)
Institution/School/ University
Year Remarks
SSC (X)
HSC (XII)
F.E. (first year
engineering)
B. E (E &T/C)
Electronics &
Telecommunication
M. Tech (EDT)
Electronic Design &
Technology
Ph. D (Electrical Engg)
Microelectronics/ Nano
electronic Devises
Nutan Vidya Mandir
Parbhani
Shri Shivaji Mahavidyalaya
Parbhani
Govt. College of
Engineering, Aurangabad
Marathwada University
Govt. College of Engineering
(CoEP) PUNE University
*CEDT, Indian Institute of
Science, IISc, Bangalore
Electrical Engineering
Department, Indian Institute
of Technology Mumbai, (IIT
Bombay)
March 1977
June
1979
June 1980
June
1983
Jan
1989
July
2003
Merit Scholarship PCM (87%) GATE Admission Test Score 96% in Electronic Engineering Received Excellent Grade (A+) for Project prototype Duration of Ph.D (Approx 3.Years, 3 months)
2 | P a g e pnkondekar/resume/May2015
9) List of all previous employment, (including present posting) in order of most recent first.
Sr No Employer’s Name Post held Length of Service (date) Nature of Work
From To
1
2
3
4
5
6
7
8
9
10
a) PDPM IIIT DM
Jabalpur
b) PDPM IIIT DM Jabalpur
Symbiosis Institute of Technology,
(Under Symbiosis International
University, Deemed to be University)
Pune
Korea Advanced Institute of Science
and Technology, Daejeon South
Korea (World Ranking ~ 50)
Dept. of Electronic Engineering
Konkuk University Seoul, South
Korea
PVPP College of Engineering,
Mumbai
Indian Institute of Technology
Mumbai
Shri Ramdeobaba Kamala Nehru
Engineering College, Nagpur
M.G.M’s College of Engineering,
Nanded
Jawaharlal Nehru College of
Engineering, Aurangabad
Morris Electronics Ltd. Pune
Professor
Asso Professor.
Dean/ Director
(Leave from S
Korea )
Asso.
Professor
Faculty
(Asst Prof)
Prof & In
charge principal
Research
Engineer
Asst. Professor
Lecturer and in
charge head
Lecturer and in
charge head
Product
development
engineer
July 2012
Jan 2010
Oct
2008
Oct 2006
Sept.
2003
July
2003
Oct 1999
Dec 1989
Aug 1987
Nov 1984
Aug 1983
Present
July 2012
Sept
2009
July
2009
Sept.
2006
Aug
2003
Nov
2001
July
2003
Nov
1989
July 1986
Oct 1984
PG & UG Teaching &
research and
curriculum
development and
Academic, Various
Administrative Duties,
Head Counseling
Services, Chairman
Placement
Establishing a new
Technical Institute
PG & UG Teaching &
research and
(Collaboration and
MoU with Indian
Institutes)
Same as above
Teaching &
Administration
& Lab Development
GE Company USA
Project Staff
Teaching and research
and Administration
(HoD)
Teaching and Lab
development and
related duties (HoD)
Teaching and Lab
development and
related duties
Replacement of
Alnico Magnet with
hard ferrite and
transformer soft-
ferrite core
characterization
3 | P a g e pnkondekar/resume/May2015
10) a. Thesis (M.Tech/Ph.D) Supervision (at South Korea)
b. Thesis Ph. D Supervision (Currently at IIITDM Jabalpur)
c. Thesis M. Tech. Supervision (Currently at IIITDM Jabalpur)
11. Membership of Professional Bodies: IEEE, ISTE (Indian Society for Technical Education-Life Member)
Scholarship Record: National Merit Scholarship (Std. X to Graduation B.E. (Aug 1978~June 1983)
13. Ph.D. Title: Simulation Studies of Super-junction Power MOSFET, Supervisors: Prof Mahesh Patil, Dept. of
EE, IIT Bombay (June 2003)
M.Tech. Project Title: Multiple Output Switch Mode Power Pack i.e. SMPS with specifications 5V, 5A. +12V,
2A and –12V, 2A. (74 Watts) Supervisor: Prof K. Gopakumar, CEDT, IISc, Bangalore (Jan 1989)
S No Name Year of Completion Title of Thesis Co-guides (if any)
1
Anil Kavala
(M.Tech/PhD)
June 2009 KAIST
Daejeon,
A low power liner pseudo
differential OTA for UHF
Application (Completed)
2
Sun Yang
(M.Tech/PhD)
June 2009 KAIST
Daejeon, S. Korea
RF Filter design Prof Lee
Sang Guk
KAIST
S.no Name Course/Semester Research Title
1. Ms. Sangeeta Singh Ph.D (3.5 Years) Steep Sub-threshold nano -devices (Thesis Writing )
2. Alok Naugarhiya Ph.D (4 Years) Power MOSFET Super-junction (Thesis submitted )
3 Sumit Kale Ph.D (3 Years) Schottky (Ongoing)
4 Shashank Dubey Ph.D ( 2.5 Years) Stress analysis for Fin FETs (Ongoing)
5 Kaushal Nigam Ph.D (1.5 Years ) Tunnel FETs and Their Performance (Ongoing)
6 Bhaskar Awdiya Ph.D (1.0 Years) Circuit Implementation of Steep SS TFET (Ongoing)
1 Apurba Chakraborty M.Tech Driving Current Improvement Analysis of Tunnel FET. (Completed)
2 Manish Yadav M.Tech Comparative analysis of Finfet. (Completed)
3 Pankaj Yadav M.Tech Trigate Organic FET (Completed)
4 Deep Aghari M.Tech Organic FET performance using different materials (Completed)
5 Pankaj Jha M.Tech Performance Estimation of Gate-Inside Junctionless Transistor (GIJLT)- A Novel Device Structure (Completed)
6 Ishu Agrawal M.Tech Performance Analysis of Double Gate Tunnel FET (Completed)
7 Ankit Dixit M.Tech Performance Enhancement of Lateral I-MOS Using Simulation and Characteristics (Completed)
8 Pankaj Wakhradkar M.Tech Super Junction SiC Power Devices (Completed)
9 Rai Narendra Suresh M.Tech (IV)
High Electron Mobility Transistor Study & Application (Ongoing)
10 Hemant Kumar Bhardwaj M.Tech (IV)
Study of Process Variations on Strained Fin FETs (Completed)
11 Shashank Kumar Banchhor M.Tech (IV)
Schottkey-TunnelFET Modeling (Completed)
4 | P a g e pnkondekar/resume/May2015
12. Publication (Separate list at the end)
14. Short-term Course/Workshop/Seminars Organized
1) Successfully organized a National level conference on recent trends in electronic circuit design,
UTKARSH’97 at RKN Engineering College for which I worked as Chairman.
2) Actively involved in the organization of International Conference on VLSI-Technology VSDT 2001
at IIT Mumbai
3) “TCAD tools for Semiconductor Device and Circuit Simulation with hands on training” A 3 days
Workshop opens for all interested students and faculty. Experts from Industry and reputed institutes
like IITB were arranged. 40 participants from all around have taken the benefit of this workshop
4) “Research trends in nanofabrication with TCAD simulation with hand on training” WON 2013, 25th
to 27th
May, Workshop on Nanofabrication
15. Arranged Distinguished Lectures at IIITDM Jabalpur
a)“Building India where dreams come true – journey to an exciting professional career” by Padmshree Prof.
Deepak Phatak of IIT Mumbai (Open for all and attended by more than 150 participants)
b)“Multi-disciplinary Research Opportunities in Nanotechnology” by Prof. V.Ramgopal Rao, Bhatnagar Awardee,
from IIT Mumbai, attended by approx. 80 PG/UG students
16. Administrative Experience
Member Board of Governors, IIITDM Jabalpur, From Dec-2014 onward….. Head of Dept. ECE, IIITDM from Jan 2010 to July 2012 and Aug 2014 onwards….
Transparency Officer , IIITDM Jabalpur from Jan 2014 (Under RTI Act-2005)
Head Counseling Services , IIITDM Jabalpur from June 2011 onward…
Chairman, Placement Cell, IIITDM Jabalpur from May 2011~ Aug 2013
Chairman Internship Board, IIITDM Jabalpur from April 2011 ~ Aug 2013
Member of CRC- Curriculum Review Committee, IIITDM 2010-till today
Convener PG Admission (M.Tech./Ph.D) committee IIITDM May 2010, and May 2015
Member Recruitment committee (2010) for technical staff at IIITDM Jabalpur.
Member of Institute Advisory Group for General Administration of IIITDM (IAG-GA Member 2010~)
Dean, Faculty of Engineering, Symbiosis International University, Pune Dec 2008 to Nov 2009
Director, SIT Symbiosis Institute of Technology, Lavale, Pune Oct 2008 to Sept. 2009 (New Institute)
Member IT advisory committee/ Member Purchase Committee, Symbiosis Society, SIU Pune
Member of International Admission Committee for PG in South Korea (KAIST and Konkuk University)
Worked as HoD for Electronic Design Technology at RKN College of Engineering Nagpur.
Member Moderation Committee in Nagpur University during 1990-1998
No of Papers Published
Single Author
No of Papers Published
Jointly
No of Papers in Seminar, Workshop
International
Journal/Proceedings
(18)
International
Journal/Proceedings
(20)
International Seminars
(4)
National Journal/Proceedings
(1)
National Journal/Proceedings
(0) National Seminars
(2)
5 | P a g e pnkondekar/resume/May2015
17. Awards and Recognition
Biography is published in the America’s Marquis Who’s Who of the World 2006
National Merit Scholarship from SSC onward for Higher Education
18. Teaching Experience, New Courses and Labs (Development)
Title Level (UG/PG) Number of Times
Developed by you or not
1. a) Solid State Device Physics b) Analog CMOS-IC Design 2. Engineering Literacy (Lab) 3. Noise reduction techniques in electronic equipments. 4. Reliability of electronic equipment.
1 .Electronic Devices &Circuit Design (Fundamental of Electronic Devices )(+Lab) 2. CMOS VLSI design (+Lab) 3. Solid Sate Electronic Devices 4. Electronic devices and circuit 5. Design of electronic circuits (+Lab) 6. Digital circuit and logic design 7. Circuit theory (+Lab) 8. Linear Integrated Circuits (+Lab) 9. Electronic Instrumentation and Measurements 10. Electronic and Electrical components and Materials 11. Basic Electrical Engineering
PG UG (I year) UG (III Year) UG (III Year
UG(II year) PG UG UG UG UG UG UG UG UG UG
4 4 2 3 3
7 3 4 10 6 5 8 4 4 3 6
Developed by Me for IIITDM Developed by Team lead by me at IIITDM Developed by me based on CEDT ( First time in Nagpur University) Developed by me based on CEDT ( First time in Nagpur University)
Existing ( Modified by me to add design approach at IIITDM) Existing (Modified by me at KAIST S.Korea) ) Existing (At KAIST) Existing (At KAIST and INDIA) Exisiting at Konkuk University S. Korea Existing (At KAIST and INDIA Exisiting at Konkuk University S. Korea Existing Existing Existing (modified by me ) Existing
6 | P a g e pnkondekar/resume/May2015
19. Books Authored/Planned
Planning to publish a book on
1) “Engineering Literacy” a Noval New Subject/Concept, which, we have introduced for the First Year of
Engineering at our Institute based on the collection of most commonsense oriented and essential knowledge for
all engineers across all disciplines which includes Lab Demonstrations. e.g. Earthing connection in Domestic
wiring, Specifications of energy saving gadgets, along with all Computer related etc.
2) A student friendly book on “Electronic Devices and Circuit Design” is almost ready
20. Countries Visited
Participated in many International conferences to present my work at Dallas, USA, Singapore, Bangkok
Thailand, Hong Kong, Malaysia, Australia, South Korea, Spain, and Egypt
21. Project (Sponsered)
22. Professional Experience
Publicity Chair, and Member of Advisory committee, for the First IEEE Sponsored International Conference on
“Control, Automation, Robotics and Embedded System” CARE-2013 at IIITDM Jabalpur in Dec 2013
Period Sponsoring Organization Title of Project Amount of Grant
Co-Investigators
(if any)
Aug 1983~
Oct 1984
Morris Electronics Ltd. Pune
Replacement of Alnico Magnet with hard ferrite and transformer soft-ferrite core characterization (funded project)
Rs 8 Lac
Oct 2006~ Dec 2009
Ministry of Information Through Information and Communication University (KAIST) Govt of Korea
RF Semiconductor Device Modeling and Characterization (as initial funding)
US $ 25000/-
Dec 2013 Mar. 2014
INUP(Indian Nano-electronic User Program) IITB Short-term Projcet
Sub-threshold characteristics investigation of fabricated Vertical IMOS & TCAD validation and modeling using device physics
---------------
9th Sept. 2014~2018 (Submitted)
DST (Dept. of Science and Technology) Govt. of India through SERB
Investigation of Emerging Nano-electronic Devices & Nano-electro-mechanical Devices & Systems (NEMS) as High Sensitivity Chemical/Bio-Sensors.
Rs 1.37 Cr Under Review
Dr Neeraj Jaiswal IIITDM J
May. 2015~2020 (5 Years )
DeitY Govt of India Special Manpower Development Program for VLSI (SMDP) (funded project)
Hardware & Software Support (~Rs 65 Lacs)
Dr Jawar Singh
7 | P a g e pnkondekar/resume/May2015
Worked as Center In-charge for conducting various competitive examinations/written test for a) Indian Railway
Recruitment Board (10 times) b) Maharashtra State Electricity Board Recruitment of Junior Engineers c) State
Bank of India Recruitment of officers, at RKN Engineering College, Nagpur
Invited Speaker on topic “Electronic Product Design from EMI/EMC considerations” International Design
workshop at IIITDM, DEW 2010
Chair the session on Device Modeling at IEEE ICM’2010, 18~24 Dec 2010 (International Conference on
Microelectronics), Cario, Egypt.
Steering Committee Member for “International Design Workshop on leading edge theories and practices in
design” Oct 2010 at IIIT DM Jabalpur
Invited by AUK the Discrete Semiconductor Devices Manufacturing Company Iksan South Korea for presenting
talk on Super-junction Power MOSFET on 4th Sept 2007.
Invited by National Security Research Institute of South Korea to present a talk on EMI/EMC reduction
techniques for PCB design.
Chaired the session and also to present my work on Power devices in IEEE Tencon 2004 held at Ching Mai,
Thailand.
Chaired Session at IEEE CIMSim 2013 at Seoul, South Korea
Worked as Observer for JEE (Mains) April 2012 and April 2014, appointed by CBSC New Delhi
Department of electronic engineering, Konkuk University, Seoul, invited me for presenting seminar on the
“CMOS VLSI- the current trend & technology
Conducted and organized the Minimum competition vocational courses teacher training program (3
months duration) funded by Maharashtra Govt. through DTE (Continuously for 2 Years at RKN Engg
College Nagpur)
23. Institute Building Activities
As Prof & Head ECE Established A Micro/Nano Computational Lab (June 2010) and already Simulation tools
such as Synopsis and Cadence and Silvaco tools are procured and already 10 Masters + 5, PhD students working
on Project of Finfets and MOS device Simulation and Characterization at IIIT DM Jabalpur
As Guest House In charge for the newly constructed on campus 38 room, recently, I will be leading the
committee to formulate and procure the Furniture for the entire Guset House including Entrance, Lobby
conference room Kitchen etc. We have taken almost 6 meetings and about finalize the tender document for the
furniture with great look and quality and durability
As a Transparency officer (TO): I appealed all my faculty colleagues to upload their information and a brief CV
and their link for the course/research website to the main website. 2) Also requested the institute administration
time to time the Senate & BoG meetings minutes without delay in accordance with Suo-moto disclosure and also
took immense efforts to reduce the number of RTI applications.
The Institute authority decided to root all the tender draft documents before uploading/publishing through TO.
Which has tremendously increased my workload? But that exercise has resulted in a great amount of cost saving,
in addition to providing equal opportunity and motivation to the guanine vendors/service provider to Institute.
As Head Counseling Services, June 2011, at IIITDMJ, We have developed strong team of 70 students,
who will work as counselor and student guides who are 24/7 ready to help to all those students who are
8 | P a g e pnkondekar/resume/May2015
under stress, feeling homesick, frustrated due to their academic performance, or their personal problems
including financial one! Since our Institute is fully residential this team of counselors proved to be very
useful for suffering students and these teams taking rounds of meetings gives very useful and
constructive feedback/suggestion to institute management for various policies. I have aggressively
convinced the institute authorities not to create stressful/negative environment for student just by
suggesting few changes in the prevailing rules and their faulty implementation
All these have resulted in creating a positive campus environment. A program of Academic Mentorship
for the academically week students under faculty mentorship is now being proposed
As Member of the Student Gymkhana, IIITDMJ, Election Reform, helped identifying the limitations
of the system and helped in successful conduction of a series of meeting with UG/PG students, for
convincing the new reforms, committee’s recommendation were implemented from Jan 2012 and all
student community and faculty appreciated the improvement in culture on campus and resulted a very
successful conduction of events “ABHIKALPAN-2012” and “TARANG-2012” without any
controversies among student representatives delete this line
As Chairman Placement Cell, IIITDMJ, from May 2011~ Aug 2013, changed the policy for campus
placement for students, which resulted in offering dream job choice to academically excellent students; I
was personally involved in designing the “Placement Brochure-2011” for the institute, which resulted in
an excellent quality Brochure which was appreciated a lot. I managed to have a Most Active Placement
Cell office in term of student interaction and IIITDM Students appreciated a lot, the efforts and struggle
made by placement cell for providing good opportunities
o Visited Many Industries in Banglaore, Delhi, Pune, Hydrabad, Mumbai, and successfully
conducted meeting with HR personnel, presenting our Institute Strengths. This is the first time,
that corporate world started recognizing the presence our Institute and many of the excellent
companies empanelment process is successfully achieved
o Successfully Managed to convince the public sector company BEL (Bharat Electronics Limited)
Who suddenly cancelled their (well in advance) announced visit to institute for recruitment. I
personally visited the Head quarter at Bangalore and somehow could convince them about the
feelings of the students eagerly waiting for this opportunity. Finally on the last day of the term in
May 2012 BEL visited IIITDM and happy recruited 13 students in one go of ECE and ME
disciplines. This effort was appreciated by all ( All these 13 students Joined BEL)
23. Other Contributions
Actively involved in getting MoU between IIT Bombay and KAIST-ICU (Information and Communication
University, Daejeon South Korea), IIT Bombay’s Director, Ashok Mishra signed the General MoU on 27th July
2007.
Research Member faculty of IREC “Intelligent Radio Engineering Centre” Funded by the centre of excellence of
Ministry of Science, Ministry of Information and Communication Korea , School of Engineering, Information
and communication University, Daejeon
Advisor for identifying institutes of potential from India for recruiting research engineers for ETRI (Electronic
and Telecom Research Institute, Daejeon South Korea) Oct 2006 to Jan 2008
After completion of M.Tech (Electronic design and technology) from CEDT, IISc Bangalore, in Jan. 1989, I
joined as Assistant Professor in Shri Ramdeobaba Kamala Nehru Engineering College in Dec.1989. Here, I was
9 | P a g e pnkondekar/resume/May2015
instrumental in development of PCB Lab. Facilities along with Prototype Development Lab for converting the
project work in to a prototype product.
As a Guest house in charge at IIITDMJ, I have formulated the policy for the allotment priority, and effective
maintenance and cleanliness where the guest of the institute will enjoy their stay and wish to visit again.
Received very good response & Evaluation from students for teaching and the 155 (Korean) students registered
my “Electric Circuit Analysis” at UG level which is record in itself
24. Details of Experience of Organizing Events:
Sr.
No. Name of the Event Place held
Duration
Position held
From To
1.
“WON” A 3 Days Workshop on
nanofabrication and Nano electronics
http://won2013.iiitdmj.ac.in/
PDPM IIITDM
Jabalpur
25th
May
2013
27th
May
2013
Convener
2. Workshop for Hands on training on Circuit
Simulation CEDENCE
PDPM IIITDM
Jabalpur
17th
Feb
2012
18th
Feb
2012
Coordinator
3. Distinguished Lecture by Padma Shri (Prof.)
D. B. Phatak (IIT Bombay)
PDPM IIITDM
Jabalpur
9th
Jan
2012
-- Organizer
4.
Distinguished Lecture by Shanti Swarup
Bhatnagar Awardee, Prof. Ramgopal Rao
(IIT Bomaby)
PDPM IIITDM
Jabalpur
27th
Dec
2011
-- Organizer
5. International Design Workshop on leading
edge theories and practices in design
PDPM IIITDM
Jabalpur
Oct
2010
Steering
Committee
member
6.
The Fourth Indo-Japan Joint seminar on
micro/nano manufacturing”, Sponsored by
Ministry of Science and Technology, Govt.
of India and Japan’s Society for Promotion of
Science (JSPS)
Symbiosis Institute
of Technology, Pune
8th
March
2009
11th
March
2009
Coordinator
7.
IEEE- International Conference on
Control,Automation, Robotic & Embedded
Systems
PDPM IIITDM
Jabalpur
16th
Dec
2013
18th
Dec
2013
Committee
Member
Publicity
8. IEEE- International Conference on VLSI-
Technology VSDT 2001 IIT Bombay
Dec
2001 3 Days
Member
Organizing
Committee
9. National level conference on recent trends in
electronic circuit design, UTKARSH’97
RKN Engineering
College Nagpur
10th
Oct
1997
3 Days Chairman
25. Experience of Working with International Bodies / International Exposure:
Sr.
No.
Name of the International
Bodies Place Purpose
Duration Position held
From To
1.
ETRI (Electronic
Telecommunication
Research Institute)
Taejon,
South
Korea
Identifying institute of
potential from India for
recruiting research
enneers for ETRI
Aug
2006
July
2008
Advisor
10 | P a g e pnkondekar/resume/May2015
26. Referees:
1. Prof. Mahesh B. Patil [email protected]
Prof in Electrical Engineering IIT Mumbai. Powai Mumbai 400076
Office: +91-22-25767447
2. Prof. Juzer Vasi, [email protected]
Prof in Electrical Engineering, IIT Mumbai. Powai Mumbai 400076
Office: +91-22-25767408
Mobile No: 91 9323799233
3. Prof K. Gopakumar [email protected]
Prof. and Chairman, DESE, (Dept. for Electronic Systems Engineering)
Former CEDT, C.V Raman Avenue, Malleshwaram
Indian Institute of Science, Bangalore 560012
Mobile 09448227853
4. Prof. Ashok Misra [email protected]
Chairman-India, Intellectual Ventures, Bangaluru
Former Director, IITB Mumbai.
Office: +91 9820222322
Reference: From Konkuk-University All from, Department of Electronics Engineering, Konkuk-
University. 1 Hwang dong, Gwanjin gu, Seoul-143-701. South Korea (Dept. Fax: +82-2-3437-5235)
1. Prof. Cho Yong-Beom, Contact: 011-410-1423 [email protected]
2. Prof. Kim Yong-Beom, Contact: 010-5210-0436 [email protected]
Date:
Place: Prof. Kondekar Pravin N.
11 | P a g e pnkondekar/resume/May2015
Appendix; I
List of Publications
Refereed Journal:
1) Pravin N. Kondekar Oh Hwan Sool “Analysis of the breakdown voltage, the on resistance, and the
charge compensation of super-junction power MOSFET”, Journal of Korean Physical Society, vol.44,
no.6, pp. 1565~1570, June 2004. (SCI, IF 2.31)
2) Pravin N. Kondekar, Oh Hwan Sool “Study of the degradation of the breakdown voltage of a super-
junction power MOSFET due to charge imbalance”, Journal of Korean Physical Society, vol.48, no.4,
pp.624~630 April 2006. (SCI, IF 2.31 )
3) Mohit Gupta, Nitesh Gaur, Puneet Kumar, Sangeeta Singh, Neeraj K. Jaiswal, P.N. Kondekar, Tailoring
the electronic properties of a Z-shaped graphene field effect transistor via B/N doping, Physics Letters A,
Available online 30 December 2014.(SCI, IF-1.7)
4) S. Singh, P. Pal, P. N. Kondekar, Charge-plasma-based super-steep negative capacitance junctionless
tunnel field effect transistor: design and performance’’, IET Electronics Letters, vol. 50 (25), pp. 1963-
1965, 2014. (SCI IF-1.05)
5) S. Singh and P.N. Kondekar “Dopingless Super-steep Impact Ionization MOS (Doping less-IMOS) Based
on Work-function Engineering”, Electronics letter, vol. 50, issue 12, pp 888-889, Institute of engineering
and technology (SCI IF-1.05)
6) S. Kale and P. N. Kondekar, Ambipolar leakage reduction in Ge n-channel schottky barrier MOSFET’’,
IETE Journal of research. (Accepted). (SCI IF-0.7)
7) A.Naugarhiya and P.N.Kondekar, “High permittivity material selection for design of
optimum Hk VDMOS”, Super-lattices and Microstructures, vol. 83, pp. 310-321, July 2015. (SCI, IF-
2.097)
8) A.Naugarhiya, Shashank Dubey and P.N.Kondekar,”Novel strained superjunction VDMOS” Superlattices
Microstruct, vol.85, pp.461--468, September 2015, Elsevier. (SCI IF-2.097)
9) S. Singh and P.N. Kondekar, “Dopingless Impact Ionization MOS-A remedy For Complex Process Flow”,
Journal of Semiconductor, IOP, 2015.(Accepted) (SCI)
10) Apurba Chakraborty, P.N. Kondekar,” Driving Current Improvement by Layer in P-Channel Tunnel Field
Efect Transistor” Journal of Electron Devices, Vol. 15, 2012, pp. 1282-1284. (Open-Access)
11) Ankit Dixit, Sangeeta Singh, P. N. Kondekar “Ultra Thin Impact Ionization MOSFET (UTIMOS)- For
Reduced Operating Voltages” Journal of Electron Devices, Vol. 19, 2014, pp. 1663-1669 (Open-Access)
Communicated Journals
12) A. Naugarhiya, Shashank Dubey and P.N. Kondekar, “Novel Strained Superjunction VDMOS”
communicated in Superlattices Microstructure. (Submitted Revision).
12 | P a g e pnkondekar/resume/May2015
13) A. Naugarhiya, P.N. Kondekar and P.Wakhradkar, Modeling and Device Simulation of Anisotropic 4H-
SiC Superjunction Devices, communicated with revision in IEEE Trans. Electron Devices. (Submitted
Revision).
14) P.N.Kondekar, “Analysis of dynamic charge imbalance in super-junction power MOSFET: using theory
of novel voltage sustaining layer”, Submitted for review to IEEE Transaction on Electron Devices.
15) P.N.Kondekar, “Analysis of High Voltage Super-junction Drift layer for Power MOSFET”, Submitted
for review to Elsevier, Solid State Electronics.
16) A. Naugarhiya and P.N. Kondekar, A Novel Charge-Termination process Model for Vertical Trench p-
pillar Superjunction Power MOSFET, in International Journal of Electronics, Taylor and Francis.
17) A. Naugarhiya and P.N. Kondekar, “Optimized Analytical Model for Robust Design of Vertical
Superjunction Power MOSFET”, in International Journal of Electronics Letter, Taylor and Francis.
18) S. Kale and P. N. Kondekar, “Suppression of ambipolar leakage current in schottky barrier MOSFET
using gate engineering,” communicated in Electronics letter.
19) Kaushal Nigam and P. N. Kondekar,“Doping-Less Vertical Tunnel Field Effect Transistor Based on
Work Function Engineering”, communicated in Electron device letter.
20) S. Singh, P. Pal and P. N. Kondekar “Charge Plasma based Super-Steep Negative Capacitance
Junctionless Tunnel Field Effect Transistor: Performance Estimation”, communicated in Semiconductor
Science and technology, IOP.
21) H. Bardwaj S. Dubey and P. N. Kondekar “Process Dependent Variability analysis of Source Drain
Stressor p-FINFET”, communicated in IEEE Trans. Electron Devices.
22) S. Dubey and P. N. Kondekar,“Comparative Analysis of Strained and Unstrained Inverter”,
Microelectronics, Elsevier.
Refereed Conferences (Blind reviewed and indexed at IEEE explorer):
1) Pravin N. Kondekar “Simulation study of charge imbalance in super-junction power MOSFET”, Proc.
IEEE EDSSC’05, pp. 551-555 Hong Kong, Dec 2005.
2) Pravin N. Kondekar et. al.,“Simulation, characterization, and modeling of on state charge imbalance in
super-junction power MOSFET:CoolMOSTM
”, Proc. ICPE’04. pp.II-283~II-285, Busan, South Korea.
3) Pravin N. Kondekar, “The effect of static charge imbalance on forward blocking voltage of super-
junction power MOSFET” Proc. IEEE-TENCON’04, vol. C, pp.209~212, Chiang Mai, Thailand.
4) P.N.Kondekar, M.B. Patil and C.D Parikh, “Analysis of breakdown voltage and on resistance of
superjunction power MOSFET: CoolMOSTM
using theory of novel voltage sustaining layer”,
Proc.PESC’02, vol.4, pp.1769-1778, June 2002, Cairns, Australia. Full Travel Grant was received from
CSIR-Delhi.
13 | P a g e pnkondekar/resume/May2015
5) P.N.Kondekar, M.B. Patil and C.D Parikh “Analysis and design of superjunction power MOSFET:
CoolMOSTM
for improved on resistance and breakdown voltage using theory of novel voltage sustaining
layer”, Proc.MIEL’02, pp.209-212, May 2002, Nis, Yugoslavia.
6) P.N.Kondekar, M.B. Patil and C.D Parikh, “Break down voltage and on resistance of superjunction
MOSFET: CoolMOSTM”
, Proc. IWPSD’01, vol.1 pp. 440-443, 2001, IIT New Delhi.
7) P.N.Kondekar, M.B. Patil and C.D Parikh, “Analytical design methodology of a novel drift-layer for
superjunction power MOSFET:CoolMOSTM”
Proc. IWPSD’01, vol.2, pp.1304-1306, 2001, IIT, New
Delhi.
8) P. N. Kondekar “EMC-considerations in electronic product design and technology”, National
Conference on Recent Trends in Electronic Product Design and Technology, SAS-Mohali, Chandighar
in April 1995.
9) P. N. Kondekar, “Static off state and conduction state charge imbalance in the Super-junction power
MOSFET: CoolMOS”, Proc. IEEE-TENCON-2003, Bangalore. India.
10) Pravin N. Kondekar, et.al “The effect of static charge imbalance on the on state behavior of the
superjunction power MOSFET: CoolMOSTM
”, IEEE- Proc. PEDS’2003, pp.77-80, Nov. 2003,
Singapore. (SCIE)
11) Kondekar P N. “Analytical modeling and simulation studies of high voltage super-junction drift layer
for power MOSFET” 22nd International Conference on Microelectronics (ICM 2010)
12) P.N.Kondekar, “Simulation studies of superjunction power MOSFET: CoolMOSTM”
, Proc. IWPSD’03
(CD), 2003, IIT Madras
13) P.N Kondekar, “Analytical Design and Simulation Studies of Super-junction Power MOSFET” IEEE
(International Symposium on Industrial Electronics) ISIE’07, pp. 503~508, June 4-7, Vigo, Spain
14) Rohit Kondekar, Pravin Kondekar, Deepak Pathak “Technology enabled assessment environment” pp.
54-60, Proc. IASTED International Conference on Technology for Education, Dec 2011, Dallas, USA
15) Anil Kavala, Kondekar P. N, and Yang Sun, “A low voltage, low power linear pseudo Differential
OTA for ultra-high frequency applications”, IEEE, International workshop on Antenna Technology,
2009.
16) Anil Kavala, Kondekar P. N “A low voltage, low power linear pseudo differential OTA for UHF
applications,” Page No. 21~24, Proceeding ISWPC'09, 4th international conference on Wireless
pervasive computing ISBN: 978-1-4244-4299-7.
17) Olim Hidayov, Hakimjon Zaynuddinov, Hyung Chul Park, Kondekar Pravin, Sang-Gug Lee, “Method
of Computing Spectral Factors in Piecewise-Quadratic Bases and its Application in Problems of Digital
Signal Processing,” Systems, Signals and Image Processing, 2008. IWSSIP 2008. 15th International
Conference
18) Apurba chakraborty , P.N. Kondekar and Manish kumar Yadav
, “Drive Current Boosting and Low
Sub-Threshold Swing Obtained by Layer in Double-Gate Tunnel FET “, Proc. of
ESciNano 2012,
Malaysia.
14 | P a g e pnkondekar/resume/May2015
19) Y.Manish, P.N. Kondekar, Jawar Singh, Apurba chakraborty “Optimized parasitic resistance
performance of Multi-Fin device” International conference on research methodologies in electron
device and circuits (EDC 2012), Amsterdam, Netherland.
20) Deep K. Agrahari, Pravin N Kondekar, Pankaj Yadav, Jawar Singh, “ High Performance Organic Filed
Effect Transistor with Tri-Gate” IEEE, 4th International Conference on Intelligent Systems, Modelling
and Simulation (ISMS-2013) pp.627-630, Jan 2013 Bangkok
21) Deep Kumar, Pankaj Yadav, P.N. Kondekar and Jawar Singh, ,”Analysis and Comparison of Organic
Field Effect Transistor with Different Dielectric Insulators,” IEEE, 4th International Conference on
Intelligent Systems, Modelling and Simulation (ISMS-2013) Jan 2013 Bangkok
22) Pankaj Kumar, Chitrkant Sahu, P. N. Kondekar, Jawar Singh “Characteristics of Gate Inside Junction
less Transistor with Channel Length and Doping Concentration” 978-1-4673-2523-3/13/$31.00 ©2013
IEEE IEEE International conference on Electronic devices and solid-state circuits (EDSSC’2013)
June 2013, presented at Hong Kong
23) P.S.Yadav, P. N. Kondekar, Jawar Singh, Deep. K Agrahari, “Structural analysis of optimized low
voltage organic field effect transistor based on Pentacene” Nirma University International Conference
on Engineering (NUiCONE-2012) Dec 12 presented.
24) Pankaj Yadav, P.N. Kondekar,Jawar Singh, and, Deep Kumar,”High performance pentacene-based
organic transistor with HfO2-Al2O3 as dielectrics,” pp. 769 ~772, International Conference of
ICMENS-2012.
25) Chitrakant Sahu, Jawar Singh, P N Kondekar, “Investigation of Ultra-thin BOX junction-less
Transistor at Channel length 20 nm”, IEEE International conference on Electronic devices and solid-
state circuits (EDSSC’2013) June 2013, presented at Hong Kong, 978-1-4673-2523-3/13/$31.00 ©2013
IEEE
26) Pankaj. Kumar, P. N. Kondekar, Sangeeta Singh, and Ishu Agarwal, “Characteristic and Sensitivity of
Gate Inside Junctionless Transistor (GI-JLT),” in 20th IEEE International Conference on Electronics,
Circuits, and Systems (ICECS-2013), PP 56~5, December 8-11 2013, Abu Dhabi, UAE
27) P. Kumar, C. Sahu, A. Shrivastava, P. N. Kondekar, and J. Singh, “Characteristics of gate inside
junctionless transistor with channel length and doping concentration,” IEEE International conference on
Electron Devices and Solid-State and Circuits (EDSSC13), Hong Kong, Polytechnic University, 2013
28) Pankaj Kumar, Sangeeta Singh, P.N. Kondekar, and Ankit Dixit, “Digital and analog performance of
gate inside p-type junction-less transistor (GI-JLT),” in CIMSim2013, IEEE, 5th
International
Conference on Computational Intelligence, Modeling and Simulation (CIMSim2013), Seoul, Korea, Sep.
2013.
29) Ishu Agrawal, P.N Kondekar and Sumit Kale, “Performance analysis of tunnel FET,” IEEE
International Conference on Circuit, Control and Communication (C-CUBE 2013), at Bangalore, ISBN:
978-1-4799-1598-9, ST-pp 3 December 2013
30) Alok Naugarhiya, P.N. Kondekar “Electrical Characteristics Comparison between Process and Device
Structures of Super Junction VDMOS”, pp 1~4, IEEE International Conference On Control,
Automation, Robotics and Embedded System, Dec 16~18, CARE-2013
15 | P a g e pnkondekar/resume/May2015
31) Sachin Agrawal, Sunil Pandey, Jawar Singh, and P.N.Kondekar,”An Efficient RF Energy Harvester
with tuned Matching Circuit”, Volume 382, pp 138-145, July 2013. 17th International Symposium on
VLSI Design and Test, MNIT Jaipur, India.
32) Sunil Pandey, Sachin Agrawal, Jawar Singh, and P.N.Kondekar,”A Low-Power and compact CMOS
based CDTA and its Application”, July 2013, 17th International Symposium on VLSI Design and Test,
MNIT Jaipur, India
33) Ankit Dixit, S Singh, P N Kondekar, Pankaj Kumar “Performance analysis of Lateral Impact Ionization
MOS(LIMOS)” IEEE conference Techsym 2014, IIT Kharaghpur, India.
34) Sangeeta Singh, Ankit Dixit, P. N. Kondekar, “Transient Analysis of Lateral Impact Ionization
MOSFET (LIMOS)” The International Conference on Convergence of Technology, 2014 Pune
35) Ishu Agrawal, P.N Kondekar,“Drain improvement using spacer and charge plasma concept in T-FET
,” The 18th IEEE International Symposium on Consumer Electronics (ISCE-2014), June-2014 South
Korea
36) Ishu Agrawal, P.N Kondekar “Performance analysis of tunnel field effect transistor using charge
plasma concept” 10th
IEEE International Conference on Electronic Devices and Solid State Circuits”
(EDSSC-2014), June 2014 China.
37) Sumit Kale, P N kondekar, “Impact of Underlap Engineering on the Performance of DG SB-MOSFET
with Si3N4 Spacer Layer”, 10th
IEEE International Conference on Electronic Devices and Solid State
Circuits” (EDSSC-2014), June 2014 China.
38) P. Kumar, S. Singh and P. N. Kondekar, “Transient Analysis & Performance Estimation of Gate Inside
Junctionless Transistor (GI-JLT),” in 24th GLSVLSI 2014, pp 235-236, Houston, Texas, May 21-23
2014, USA.
39) Sumit Kale, P.N. kondekar,“Performance Study of HfO2 Gate & Spacer Dielectric Dopant Segregated
Schottky Barrier SOI MOSFET, 4th IEEE International Conference on Advances in Computing and
Communications (ACC-2014), 27-29 August 2014, Cochin, Kerala, INDIA.
40) Sangeeta Singh, Pankaj Kumar P.N. Kondekar, “Transient Performance Analysis of Gate Inside
Junctionless Transistor (GI-JLT)” in ICEBEA 2014 International Conference on Electronics,
Biomedical Engineering and Applications, Dubai UAE.
41) Kondekar, P.N., Naugarhiya, A., “AC and Transient Analysis of SJ VDMOS” ICEBEA 2014 Dubai.
Articles and Blogs
My Blog Published on 1st May 2014, wordpress.com pnkondekar.wordpress.com received appreciation from
faculties of Institute/university of repute
Date:
Place: Prof. Kondekar Pravin N.