CY8CPLC20 Powerline Communication Solution

PRELIMINARY CY8CPLC20

Powerline Communication Solution

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 001-48325 Rev** Revised September 18, 2008

Features■ Powerline Communication Solution

❐ Integrated Powerline Modem PHY❐ 2400 bps Frequency Shift Keying Modulation❐ Powerline Optimized Network Protocol❐ Integrates Data Link, Transport, and Network Layers❐ Supports Bidirectional Half Duplex Communication❐ CRC Error Detection to Minimize Data Loss❐ I2C™ Enabled Powerline Application Layer❐ Supports I2C Frequencies of 50, 100, and 400 KHz❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC

Coupling Circuits❐ Reference Designs comply with CENELEC

EN50065-1:2001 and FCC Part 15■ Powerful Harvard Architecture Processor

❐ M8C Processor Speeds to 24 MHz❐ Two 8x8 Multiply, 32-Bit Accumulate

■ Programmable System Resources (PSoC Blocks)❐ 12 Rail-to-Rail Analog PSoC Blocks provide:

• Up to 14-Bit ADCs• Up to 9-Bit DACs• Programmable Gain Amplifiers• Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks provide:• 8 to 32-Bit Timers, Counters, and PWMs• CRC and PRS Modules• Up to four Full Duplex UARTs

• Multiple SPI™ Masters or Slaves• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks■ Flexible On-Chip Memory

❐ 32K Bytes Flash Program Storage 50,000 Erase/Write Cy-cles

❐ 2K Bytes SRAM Data Storage❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations❐ 25 mA Sink on all GPIO❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO❐ Up to 12 Analog Inputs on GPIO❐ Configurable Interrupt on all GPIO

■ Additional System Resources❐ I2C™ Slave, Master, and Multi-Master to 400 kHz❐ Watchdog and Sleep Timers❐ User-Configurable Low Voltage Detection❐ Integrated Supervisory Circuit❐ On-Chip Precision Voltage Reference

■ Complete Development Tools❐ Free Development Software (PSoC Designer™)❐ Full featured, In-Circuit Emulator and Programmer❐ Full Speed Emulation❐ Complex Breakpoint Structure❐ 128K Bytes Trace Memory❐ Complex Events❐ C Compilers, Assembler, and Linker

Logic Block Diagram

CY8

CPL

C20

Powerline Network Protocol

Physical Layer FSK Modem

AC/DC Powerline Coupling Circuit(110V/240V AC, 12V/24V AC/DC etc.)

Powerline


Powerline Transceiver Packet

Programmable System Resources

Digital and Analog Peripherals

PSoC Core

Additional System Resources

MAC, Decimator, I2C, SPI, UART etc.

PLC Core

Powerline Bridge Layer

Embedded Application

[+] Feedback

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Document Number: 001-48325 Rev** Page 2 of 45

PLC Functional OverviewThe CY8CPLC20 is an integrated Powerline Communication(PLC) solution with the Powerline Modem PHY, Network ProtocolStack, and Powerline Bridge (PLB) Application Layer running onthe same chip. This provides a complete solution to implementrobust communication between different nodes on a Powerline.

Robust Communication using Cypress’s PLC SolutionPowerlines are available everywhere in the world and are awidely available communication medium for PLC technology.The pervasiveness of Powerlines also makes it difficult to predictthe characteristics and operation of PLC products. Because ofthe variable quality of Powerline around the world, implementingrobust communication over Powerline has been an engineeringchallenge for years. The Cypress PLC solution enables secureand reliable communication over Powerline. Cypress PLCfeatures that enable robust communication over Powerlineinclude:

■ Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage Powerlines.

■ Powerline optimized network protocol that supports bidirec-tional communication with acknowledgement based signaling. In case of data packet loss due to bursty noise on the Powerline, the transmitter has the capability to retransmit data.

■ The Powerline Network Protocol also supports 4-bit CRC for error detection and data packet retransmission.

■ A Carrier Sense Multiple Access (CSMA) scheme is built into the network protocol; it minimizes collisions between packet transmissions on the Powerline and supports multiple masters and reliable communication on a bigger network.

Powerline Modem PHYFigure 1. CY8CPLC20: Physical Layer FSK Modem

The physical layer of Cypress PLC solution is implemented usingan FSK modem that enables half duplex communication on any

high voltage and low voltage Powerline. This modem supportsraw data rates up to 2400 bps. A block diagram is shown inFigure 2.

Figure 2. Physical Layer FSK Modem

Transmitter SectionDigital data from the network layer is serialized by the digitaltransmitter and fed as input to the modulator. The modulatordivides the local oscillator frequency by a definite factordepending on whether the input data is high level logic ‘1’ or lowlevel logic ‘0’. It then generates a square wave at 133.3 kHz(Logic ‘0’) or 131.8 kHz (Logic ‘1’), which is fed to the Program-mable Gain Amplifier. This enables tunable amplification of thesignal depending on the noise in the channel.

Receiver SectionThe incoming FSK signal from the Powerline is input to a highFrequency (HF) Band Pass Filter that filters out-of-bandfrequency components and outputs filtered signal within thedesired spectrum of 125 kHz to 140 kHz for further demodu-lation. The Mixer block multiplies the filtered FSK signals with alocally generated signal to produce heterodyned frequencies.The Intermediate Frequency (IF) Band Pass Filters furtherremove out-of-band noise as required for further demodulation.This signal is fed to the correlator which produces a DCcomponent (consisting of Logic ‘1’ and ‘0’) and a higherfrequency component. The output of the correlator is fed to a Low Pass FIlter (LPF) thatoutputs only the demodulated digital data at 2400 baud and

CY8

CPL

C20







PSoC Core



PLC Core



Network Protocol

Coupling Circuit

HF Band Pass Filter

Hysteresis Comparator

Digital Receiver

IF Band Pass Filter

Low Pass Filter

Mixer

Correlator

Pow

erlin

e M

odem

PH

Y

Modulator

Local Oscillator

Logic ‘1’ or Logic ‘0’

Programmable Gain Amplifier

Square Wave at 133.3KHz/

130.4KHz

Digital Transmitter

Tran

smitt

er

Rec

eive

r

Local Oscillator

[+] Feedback




suppresses all other higher frequency components generated inthe correlation process. The output of the LPF is digitized by thehysteresis comparator. This eliminates the effects of correlatordelay and false logic triggers due to noise. The Digital Receiverdeserializes this data and outputs to the Network Layer for inter-pretation.

Coupling Circuit Reference DesignThe coupling circuit couples low voltage signals fromCY8CPLC20 to the Powerline. The topology of this circuit isdetermined by the voltage on the Powerline and designconstraints mandated by Powerline usage regulations.Cypress provides reference designs for a range of Powerlinevoltages such as 110V/240V AC and 12V/24V AC/DC. The 110VAC and 240V AC designs are compliant to the followingPowerline usage regulations:

■ FCC part 15 for North America

■ EN50065-1:2001

Network ProtocolCypress’s Powerline optimized Network Protocol performs thefunctions of the data link, network and transport layers in anISO/OSI Equivalent Model.

Figure 3. CY8CPLC20: Powerline Network Protocol

The network protocol implemented on the CY8CPLC20 chipsupports the following features:

■ Bidirectional half duplex communication

■ Master and slave and peer-to-peer network of powerline nodes

■ Multiple masters on powerline network

■ Variable length command set (8-bit or 16-bit commands)

■ 8-bit logical addressing supports up to 250 Powerline nodes

■ 16-bit extended logical addressing supports up to 65530 Powerline nodes

■ 64-bit physical addressing supports up to 264 Powerline nodes

■ Individual, broadcast or group mode addressing

■ Carrier Sense Multiple Access (CSMA)

■ Band-In-Use Signalling (BIU)

■ Full control over transmission parameters ❐ Acknowledged❐ Unacknowledged❐ Repeated transmit❐ Sequence numbering

Carrier Sense Multiple Access (CSMA)and Timing Parameters

■ Carrier Sense Multiple Access (CSMA): The protocol provides the random selection of a period between 85 and 115 ms (out of 7 possible values in this range) in which the band in use detector must indicate that the line is not in use, before attempting a transmission

■ Band-In-Use (BIU): A Band-In-Use detector, as defined under CENELEC EN 50065-1, is active whenever a signal that exceeds 86 dBuVrms anywhere in the range 131.5 KHz to 133.5 KHz is present for atleast 4 ms.

■ Throughput: Each unit of data (symbol) consists of 10 bits since each character requires one start and one stop bit and 8 bits of data. At 2400 baud, this gives a throughput of 240 bytes/sec.

240 bytes/sec = 133.3 ms/32 byte packet = 4.167 ms/byteThis corresponds to 7.5 packets/sec assuming back to backtransmission

Powerline Transceiver PacketThe Powerline Network Protocol defines a Powerline Trans-ceiver (PLT) packet structure, which is used for data transferbetween nodes across the Powerline. This is generated by theApplication Layer. Packet formation and data transmissionacross the powerline network is implemented internally inCY8CPLC20. A PLT packet (32 bytes) is apportioned into a variable lengthheader (minimum 6 bytes to maximum 21 bytes), variable lengthpayload (minimum 0 bytes to maximum 25 bytes) and a CRCbyte.When the header is at its maximum length of 21 bytes, thepayload is restricted to a maximum of 10 bytes per packet.This packet is then transmitted by the Powerline Modem PHYand the coupling circuit across the powerline.The format of the PLT packet is shown in Table 1 on page 4.

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PSoC Core



PLC Core



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Table 1. Powerline Transceiver (PLT) Packet Structure

Packet HeaderThe Packet Header comprises the first six bytes of the packetwhen 1-byte logical addressing is used. When 8-byte physicaladdressing is used, the source and destination addresses eachconsist of eight bytes. In this case, the header can consist of amaximum of 21 bytes. Unused fields marked RESVD are forfuture expansion and are transmitted as bit 0. Table 2 describesthe PLT Packet Header fields in detail.Table 2. Powerline Transceiver (PLT) Packet Header

PayloadThe packet payload has a length of 0 to 25 bytes. Payloadcontent is user defined and available through the PLT ApplicationProgramming Interface (API) calls.

Packet CRCThe last byte of the packet is an 8-Bit CRC value used to checkpacket data integrity. This CRC calculation includes the headerand payload portions of the packet and is in addition to thePowerline Packet Header CRC.

Powerline Bridge LayerThe Powerline Bridge (PLB) Layer enables a host system tocommunicate with the CY8CPLC20 through serial PLBmessages. This layer translates these messages into PLTPacket as defined by the Powerline Network Protocol. The PLBlayer can also be used to split the custom application betweenthe CY8CPLC20 and the external host microcontroller.

Figure 4. CY8CPLC20: PLB Layer

A powerline node interfaced via I2C/SPI/UART to a host systemis defined as a local node. A node at the opposite end of thePowerline is defined as a remote node.

Byte Offset Bit Offset7 6 5 4 3 2 1 0

0x00 SA Type

DA Type Ext Add

r

Ext Cmd

Service

Type

Response

RESVD

0x01 Destination Address (8-bit Logical, 16-bit Extended Logical or 64-bit

Physical)0x02 Source Address

(8-bit Logical, 16-bit Extended Logical or 64-bit Physical)

0x03 Command (Up to 2 Bytes)0x04 RESVD Payload Length

0x05 Seq Num Powerline Packet Header CRC

0x06-0x1F Payload (0 to 25 Bytes)

Powerline Transceiver Packet CRC

Field Name

No. of Bits Tag Description

SA Type

1 Source Address

Type

0 - Logical Addressing1- Physical Addressing

DA Type

2 Destination Address

Type

00 - Single Node Logical01 - Group Logical10 - SIngle Node Physical11 - Invalid

Ext Addr

1 Extended Addresses

0 - Extended Addressing not set1 - Single Node Extended Logical

Ext Cmd

1 Extended Commands

0 - Extended Command not set1 - Extended Command Set

Service Type

1 0 - Unacknowledged Messaging1 - Acknowledged Messaging

Seq Num

4 Sequence Number

Four bit Unique Identifier for each packet between source and destination

Header CRC

4 Four bit CRC Value. This enables the receiver to suspend receiving the rest of the packet if its header is corrupted

CY8

CPL

C20







PSoC Core



PLC Core



I2C/SPI/UART

PowerlineSerial Bridge Driver

PSoCTM/External

µC

[+] Feedback




Figure 5. Local and Remote Nodes on a Powerline

PLB Driver APIThe Powerline Bridge Driver API provides application devel-opers simple means of communicating with a CY8CPLC20. APIfunction calls configure the CY8CPLC20, read status and config-uration information, and transmit data to remote power-linenodes.The API calls can be made from a host microcontrollerover I2C to CY8CPLC20 to operate on both local and remotenodes.

PLB MessagesPLB messages are generated by the PLB API calls and areclassified into two types based on which Powerline node they aredesignated to - local node or remote node.A knowledge of the I2C message format used in the PowerlineBridge Application is not necessary for application development.Cypress’s Powerline Bridge Driver API calls alone are sufficientto communicate reliably with a CY8CPLC20 on the powerlinenetwork.

Local PLB MessagesThese are messages sent over the serial I2C bus to the local PLBthat act solely on the attached local PLB device. No transmis-sions are sent over the powerline to a remote PLB device whenexecuting local transceiver commands. Refer to Table 3 for theI2C packet format of PLB messages intended only for the localnode. The field details are the same as described in Table 2 forPLT packet header.Remote PLB Messages

■ These are messages sent over the serial I2C bus to the local PLB which then initiates transmission over the powerline to a

remote PLB node. These I2C packets carry additional infor-mation to be included in a powerline transmission to a remote node: Destination address (8-bit logical, 16-bit extended logical, or 64-bit physical)

■ Transmission retries

■ Payload (0 to 3 Bytes)

■ Payload lengthTable 3. Local PLB Message Format

CY8

CPL

C20



AC/DC Powerline Coupling Circuit(110V AC, 240V AC, 24V DC etc.)

Powerline





PSoC Core


MAC, Decimator, I2C etc.

PLC Core



CY8C

PLC20



AC/DC Powerline Coupling Circuit(110V AC, 240V AC, 24V DC etc.)

Powerline





PSoC Core


MAC, Decimator, I2C etc.

PLC Core



I2C/SPI/UART Packet


PSoCTM/External

µC I2C/SPI/UART Packet


PSoCTM/External

µC

Local Node Remote Node


0x00 7-Bit I2C Slave Address Read/Write

0x01 PLB Message Length0x02 Resv

dCommand

TypeResvd

Local Cmd

Ext Cmd

0x03 Command ID (or MSB of Extended Command ID)0x04 Command Data (or LSB of Extended Command

ID)0x05 Command Data (0 to 10 Bytes)

0x04 + Data Length

PLB CRC Byte

[+] Feedback




Variable header and payload definitions enable flexibility in application development. Refer to Table 4 for the I2C packet format of aPLB message intended for a remote node. The field details are the same as described in Table 2 on page 4 for PLT packet headerTable 4. Remote PLB Message Format

PSoC CoreThe CY8CPLC20 is based on the Cypress PSoC® family. The PSoC family consists of many Mixed-Signal Array with On-ChipController devices. These devices are designed to replace multiple traditional MCU-based system components with one, low costsingle-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable intercon-nects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individualapplication. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range ofconvenient pinouts and packages.The PSoC architecture, as shown in Figure 6 on page 7, is comprised of four main areas: PSoC Core, Digital System, Analog System,and System Resources. Configurable global busing enables all the device resources to be combined into a complete custom system.The CY8CPLC20 family can have up to eight IO ports that connect to the global digital and analog interconnects, providing access to16 digital blocks and 12 analog blocks.The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurableGPIO (General Purpose IO).


0x00 7-Bit I2C Slave Address Read/Write0x01 PLB Message Length0x02 Resvd Command Type Addressing Types Service Type Resvd

Local Cmd Ext Cmd Destination Source ACK Service0x03 Command ID0x04 Transmission Attempts (Retries)0x05 Resvd Payload Length0x06 Destination Address (8-bit Logical, 16-bit Extended Logical or 64-bit Physical)0x07 Additional Space for Physical Address Data or Payload0x08 Payload (0 to 3 Bytes).....

0x07+Data Length

PLB CRC Byte

[+] Feedback




Figure 6. PSoC Core

The M8C CPU core is a powerful processor with speeds up to 24MHz, providing a four MIPS 8-bit Harvard architecture micropro-cessor. The CPU utilizes an interrupt controller with 25 vectors,to simplify programming of real time embedded events. Programexecution is timed and protected using the included Sleep andWatch Dog Timers (WDT).Memory encompasses 32 KB of Flash for program storage, 2 KBof SRAM for data storage, and up to 2 KB of EEPROM emulatedusing the Flash. Program Flash uses four protection levels onblocks of 64 bytes, allowing customized software IP protection.The PSoC device incorporates flexible internal clock generators,including a 24 MHz IMO (internal main oscillator) accurate to 2.5percent over temperature and voltage. The 24 MHz IMO can alsobe doubled to 48 MHz for use by the digital system. A low power32 kHz ILO (internal low speed oscillator) is provided for theSleep timer and WDT. If crystal accuracy is desired, the ECO(32.768 kHz external crystal oscillator) is available for use as aReal Time Clock (RTC) and can optionally generate acrystal-accurate 24 MHz system clock using a PLL. The clocks,together with programmable clock dividers (as a System

Resource), provide the flexibility to integrate almost any timingrequirement into the PSoC device.PSoC GPIOs provide connection to the CPU, digital, and analogresources of the device. Each pin’s drive mode may be selectedfrom eight options, allowing great flexibility in external inter-facing. Every pin also has the capability to generate a systeminterrupt on high level, low level, and change from last read.

Programmable System ResourcesFigure 7. CY8CPLC20: Programmable System Resources

The Digital SystemThe Digital System is composed of 16 digital PSoC blocks. Eachblock is an 8-bit resource that can be used alone or combinedwith other blocks to form 8, 16, 24, and 32-bit peripherals, whichare called user module references. Digital peripheral configura-tions include:

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to four)

■ SPI master and slave (up to four each)

■ I2C slave and multi-master (1 available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 4)

■ Pseudo Random Sequence Generators (8 to 32 bit)The digital blocks can be connected to any GPIO through aseries of global buses that can route any signal to any pin. Thebuses also enable for signal multiplexing and for performing logicoperations. This configurability frees your designs from theconstraints of a fixed peripheral controller.

DIGITAL SYSTEM

SRAM2K

InterruptController

Sleep andWatchdog

Multiple Clock Sources(Includes IMO, ILO, PLL, and ECO)

Global Digital InterconnectGlobal Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM Flash 32K

DigitalBlockArray

TwoMultiply

Accums.

SwitchModePump

InternalVoltage

Ref.

DigitalClocks

POR and LVD

System ResetsDecimator

SYSTEM RESOURCES

ANALOG SYSTEM

AnalogBlockArray

AnalogRef.

AnalogInput

Muxing

I C2

Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 AnalogDrivers

SYSTEM BUS

CY8

CPL

C20







PSoC Core



PLC Core



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Digital blocks are provided in rows of four, where the number ofblocks varies by PSoC device family. This enables you theoptimum choice of system resources for your application.

Figure 8. Digital System Block Diagram

The Analog SystemThe Analog System is composed of 12 configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible and canbe customized to support specific application requirements.Some of the more common PSoC analog functions (mostavailable as user modules) are listed below.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to 93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 40 mA drive as a Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF dialer

■ Modulators

■ Correlators

■ Peak detectors

■ Many other topologies possibleAnalog blocks are provided in columns of three, which includesone CT (Continuous Time) and two SC (Switched Capacitor)blocks, as shown in Figure 9.

DIGITAL SYSTEM

To System BusDigital ClocksFrom Core

Digital PSoC Block Array

To AnalogSystem

8

Row

Inpu

tC

onfig

urat

ion R

ow O

utputC

onfiguration

88

8

Row 1

DBB10 DBB11 DCB12 DCB13

Row

Inpu

tC

onfig

urat

ion 4

4R

ow O

utputC

onfiguration

Row

Inpu

tC

onfig

urat

ion R

ow O

utputC

onfiguration

Row 2


4

4

Row 0


4

4

Row

Inpu

tC

onfig

urat

ion R

ow O

utputC

onfiguration

Row 3


4

4

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]Global DigitalInterconnect

Port 7

Port 6

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

[+] Feedback




Figure 9. Analog System Block Diagram Additional System ResourcesFigure 10. CY8CPLC20: Additional System Resources

System Resources, some of which have been previously listed,provide additional capability useful to complete systems.Resources include a multiplier, decimator, switch mode pump,low voltage detection, and power on reset. The following state-ments describe the merits of each system resource.

■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers.

■ Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters.

■ The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts signals the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

ACB00 ACB01

Block Array

Array Input Configuration

ACI1[1:0] ACI2[1:0]

ACB02 ACB03

ASC12 ASD13

ASD22 ASC23ASD20

ACI0[1:0] ACI3[1:0]

P0[6]

P0[4]

P0[2]

P0[0]

P2[2]

P2[0]

P2[6]

P2[4]R

efIn

AGN

DIn

P0[7]

P0[5]

P0[3]

P0[1]

P2[3]

P2[1]

ReferenceGenerators

AGNDInRefInBandgap

RefHiRefLoAGND

ASD11

ASC21

ASC10

Interface toDigital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Reference

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CPL

C20







PSoC Core



PLC Core



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System Resources provide additional capability useful tocomplete systems. Additional resources include low voltagedetection and power on reset. The following statements describethe merits of each system resource:

■ The I2C slave or SPI master-slave module provides 50, 100, and 400 kHz communication over two wires. SPI communi-cation over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock).

■ LVD interrupts signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor.

■ An internal 1.8V reference provides an absolute reference for capacitive sensing.

■ The 5V maximum input, 3V fixed output, low dropout regulator (LDO) provides regulation for IOs. A register controlled bypass mode enables the user to disable the LDO.

Development ToolsPSoC DesignerTM is a Microsoft® Windows-based, integrateddevelopment environment for the ProgrammableSystem-on-Chip (PSoC) devices. The PSoC Designer IDE andapplication runs on Windows NT 4.0, Windows 2000, WindowsMillennium (Me), or Windows XP. (See Figure 11.)PSoC Designer helps the customer to select an operating config-uration for the PSoC, write application code that uses the PSoC,and debug the application. This system provides designdatabase management by project, an integrated debugger withIn-Circuit Emulator, in-system programming support, and theCYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compilerdeveloped specifically for the devices in the family.

Figure 11. PSoC Designer Subsystems

PSoC Designer Software SubsystemsDevice Editor

The Device Editor subsystem allows the user to select differentonboard analog and digital components called user modulesusing the PSoC blocks. Examples of user modules are ADCs,DACs, amplifiers, and filters.

The device editor also supports easy development of multipleconfigurations and dynamic reconfiguration. Dynamic configu-ration allows for changing configurations at run time.PSoC Designer sets up power-on initialization tables for selectedPSoC block configurations and creates source code for an appli-cation framework. The framework contains software to operatethe selected components. If the project uses more than oneoperating configuration, contains routines to switch betweendifferent sets of PSoC block configurations at run time. PSoCDesigner can print out a configuration sheet for a given projectconfiguration for use during application programming inconjunction with the device data sheet. When the framework isgenerated, the user can add application-specific code to fleshout the framework. It is also possible to change the selectedcomponents and regenerate the framework.

Com

man

ds Results

PSoCDesigner

CoreEngine

PSoCConfiguration

Sheet

ManufacturingInformation

File

DeviceDatabase

ImportableDesign

Database

DeviceProgrammer

Graphical DesignerInterface

ContextSensitive

Help

EmulationPod

In-CircuitEmulator

ProjectDatabase

ApplicationDatabase

UserModulesLibrary

PSoCDesigner

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Design BrowserThe Design Browser allows users to select and import precon-figured designs into the user’s project. Users can easily browsea catalog of preconfigured designs to facilitate time-to-design.Examples provided in the tools include a 300-baud modem, LINBus master and slave, fan controller, and magnetic card reader.

Application EditorIn the Application Editor you can edit your C language andAssembly language source code. You can also assemble,compile, link, and build.

AssemblerThe macro assembler allows the assembly code to mergeseamlessly with C code. The link libraries automatically useabsolute addressing or are compiled in relative mode, and linkedwith other software modules to get absolute addressing.

C Language CompilerA C language compiler is available that supports Cypress’ PSoCfamily devices. Even if you have never worked in the C languagebefore, the product quickly allows you to create complete Cprograms for the PSoC family devices.The embedded, optimizing C compiler provides all the featuresof C tailored to the PSoC architecture. It comes complete withembedded libraries providing port and bus operations, standardkeypad and display support, and extended math functionality.

DebuggerThe PSoC Designer Debugger subsystem provides hardwarein-circuit emulation, allowing the designer to test the program ina physical system while providing an internal view of the PSoCdevice. Debugger commands allow the designer to read andprogram and read and write data memory, read and write IOregisters, read and write CPU registers, set and clear break-points, and provide program run, halt, and step control. Thedebugger also allows the designer to create a trace buffer ofregisters and memory locations of interest.

Online Help SystemThe online help system displays online, context-sensitive helpfor the user. Designed for procedural and quick reference, eachfunctional subsystem has its own context-sensitive help. Thissystem also provides tutorials and links to FAQs and an OnlineSupport Forum to aid the designer in getting started.

Hardware ToolsIn-Circuit EmulatorA low cost, high functionality ICE (In-Circuit Emulator) isavailable for development support. This hardware has thecapability to program single devices.The emulator consists of a base unit that connects to the PC byway of the USB port. The base unit is universal and will operatewith all PSoC devices. Emulation pods for each device family areavailable separately. The emulation pod takes the place of the

PSoC device in the target board and performs full speed (24MHz) operation.

Designing with User ModulesThe development process for the PSoC device differs from thatof a traditional fixed function microprocessor. The configurableanalog and digital hardware blocks give the PSoC architecture aunique flexibility that pays dividends in managing specificationchange during development and by lowering inventory costs.These configurable resources, called PSoC Blocks, have theability to implement a wide variety of user-selectable functions.Each block has several registers that determine its function andconnectivity to other blocks, multiplexers, buses, and to the IOpins. Iterative development cycles permit you to adapt thehardware and the software. This substantially lowers the risk ofhaving to select a different part to meet the final design require-ments.To speed the development process, the PSoC Designer IDEprovides a library of prebuilt, pretested hardware peripheralfunctions, called “User Modules.” User modules make selectingand implementing peripheral devices simple, and come inanalog, digital, and mixed signal varieties. The standard usermodule library contains over 50 common peripherals such asADCs, DACs timers, counters, UARTs, and other not-socommon peripherals such as DTMF Generators and Bi-Quadanalog filter sections.Each user module establishes the basic register settings thatimplement the selected function. It also provides parameters thatallow you to tailor its precise configuration to your particularapplication. For example, a Pulse Width Modulator user moduleconfigures one or more digital PSoC blocks, one for each 8 bitsof resolution. The user module parameters permit you toestablish the pulse width and duty cycle. User modules alsoprovide tested software to cut your development time. The usermodule application programming interface (API) provideshigh-level functions to control and respond to hardware eventsat run-time. The API also provides optional interrupt serviceroutines to adapt as needed.The API functions are documented in user module data sheetsthat are viewed directly in the PSoC Designer IDE. These datasheets explain the internal operation of the user module andprovide performance specifications. Each data sheet describesthe use of each user module parameter and documents thesetting of each register controlled by the user module. The development process starts when you open a new projectand bring up the Device Editor, a graphical user interface (GUI)for configuring the hardware. Pick the user modules you need foryour project and map them onto the PSoC blocks withpoint-and-click simplicity. Next, build signal chains by intercon-necting user modules to each other and the IO pins. At this stage,you also configure the clock source connections and enterparameter values directly or by selecting values from drop-downmenus. When you are ready to test the hardware configurationor move on to developing code for the project, you perform the“Generate Application” step. This causes PSoC Designer togenerate source code that automatically configures the device toyour specification and provides the high-level user module APIfunctions.

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Figure 12. User Module and Source Code Development Flows

The next step is to write your main program, and anysub-routines using PSoC Designer’s Application Editorsubsystem. The Application Editor includes a Project Managerthat enables to open the project source code files (including allgenerated code files) from a hierarchal view. The source codeeditor provides syntax coloring and advanced edit features forboth C and assembly language. File search capabilities includesimple string searches and recursive “grep-style” patterns. Asingle mouse click invokes the Build Manager. It employs aprofessional-strength “makefile” system to automatically analyzeall file dependencies and run the compiler and assembler asnecessary. Project-level options control optimization strategiesused by the compiler and linker. Syntax errors are displayed in aconsole window. Double clicking the error message takes youdirectly to the offending line of source code. When all is correct,the linker builds a HEX file image suitable for programming.The last step in the development process takes place inside thePSoC Designer’s Debugger subsystem. The Debuggerdownloads the HEX image to the In-Circuit Emulator (ICE) whereit runs at full speed. Debugger capabilities rival those of systemscosting many times more. In addition to traditional single-step,run-to-breakpoint and watch-variable features, the Debuggerprovides a large trace buffer and allows you define complexbreakpoint events that include monitoring address and data busvalues, memory locations, and external signals.

PLC User ModulesThe CY8CPLC20 has the Powerline Transceiver (PLT) usermodule in PSoC Designer, which enables data communicationover Powerline at a baud rate 2400 bps. This UM also exposesall the APIs from the network protocol for ease of applicationdevelopment. The UM when instantiated provides the user withthree implementation mods:

■ FSK Modem only: This mode enables the user to use the raw FSK modem and build any network protocol or application with the help of the APIs generated by the modem PHY.

■ FSK Modem + Network Stack: This mode allows the user to use the Cypress network protocol for PLC and build any appli-cation with the APIs provided by the network protocol.

■ FSK Modem + Network Stack + Powerline Bridge Client: This allows the user to interface the CY8CPLC20 with any other microcontroller or PSoC. Users can also split the application between the PLC chip and the external micro. If the external micro is a PSoC, then another UM called the PLB Master (PLBm) is available on all PSoC devices to interface it with the PLC device.

Figure 13 shows starting window for the PLT user module withthe three implementation modes from which the user can choosefrom.

Figure 13. PLT User Module

1. Pin Information

D eb u g g er

In te rfa c eto IC E

Ap p lica t io n E d ito r

D e v ice E d ito r

P ro je c tM a n a g e r

S o u rc eC o d eE d ito r

S to ra g eIn s p e c to r

U s e rM o d u le

S e le c t io n

P la c e m e n ta n d

P a ra m e te r-iz a t io n

G e n e ra teAp p lic a tio n

B u ildA ll

E ve n t &B re a k p o in t

M a n a g e r

B u ildM a n a g e r

S o u rc eC o d e

G e n e ra to r

CY8CPLC20 or CY8CLED16P01

Physical Layer

FSK Modem

Custom Networking Protocol


Physical Layer

FSK Modem

Custom Application


CY8CPLC20 or CY8CLED16P01Physical Layer

FSK Modem


Powerline Bridge

Custom Application

PSoC

Powerline Bridge Master

Custom Application

FSK ModemCustom Network Protocol and host application using Cypress FSK Modem

FSK Modem + Network StackIntegrated PLC interface and host application using Cypress Network Protocol and FSK Modem

FSK Modem + Network Stack + Powerline Bridge ClientIntegrated Cypress PLC solution with external host microcontroller


Physical Layer

FSK Modem

Custom Networking Protocol


Physical Layer

FSK Modem

Custom Application


CY8CPLC20 or CY8CLED16P01Physical Layer

FSK Modem


Powerline Bridge

Custom Application

PSoC

Powerline Bridge Master

Custom Application

FSK ModemCustom Network Protocol and host application using Cypress FSK Modem

FSK Modem + Network StackIntegrated PLC interface and host application using Cypress Network Protocol and FSK Modem

FSK Modem + Network Stack + Powerline Bridge ClientIntegrated Cypress PLC solution with external host microcontroller

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Pin InformationThe CY8CPLC20 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every portpin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

28-Pin Part Pinout

Table 5. 28-Pin Part Pinout (SSOP)[1]

Pin No.

Type Pin Name Description Figure 14. CY8CPLC20 28-Pin PLC Device

Digital Analog1 IO I P0[7] Analog column mux input.2 IO IO P0[5] Analog column mux input and

column output.3 IO IO P0[3] Analog column mux input and

column output.4 IO I P0[1] Analog column mux input.5 IO P2[7]6 IO P2[5]7 IO I P2[3] Direct switched capacitor block

input.8 IO I P2[1] Direct switched capacitor block

input.9 Power SMP Switch Mode Pump (SMP)

connection to external compo-nents required.

10 IO P1[7] I2C Serial Clock (SCL).11 IO P1[5] I2C Serial Data (SDA).12 IO P1[3]13 IO P1[1] Crystal (XTALin), ISSP-SCLK*.14 Power Vss Ground connection.15 IO P1[0] Crystal (XTALout),

ISSP-SDATA*.16 IO P1[2]17 IO P1[4] Optional External Clock Input

(EXTCLK).18 IO P1[6] 19 Input XRES Active high external reset with

internal pull down.20 IO I P2[0] Direct switched capacitor block


input.22 IO P2[4] External Analog Ground

(AGND).23 IO P2[6] External Voltage Reference

(VREF).24 IO I P0[0] Analog column mux input.25 IO IO P0[2] Analog column mux input and


column output.27 IO I P0[6] Analog column mux input.28 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

A, I, P0[7] A, IO, P0[5] A, IO, P0[3]

A, I, P0[1]P2[7]P2[5]

A, I, P2[3]A, I, P2[1]

SMPI2C SCL, P1[7]I2C SDA, P1[5]

P1[3]I2C SCL, XTALin, P1[1]

Vss

VddP0[6], A, IP0[4], A, IOP0[2], A, IOP0[0], A, IP2[6], External VREFP2[4], External AGND

P2[2], A, IP2[0], A, IXRESP1[6]P1[4], EXTCLK

P1[2]P1[0], XTALout, I2C SDA

SSOP

123456789

1011121314

2827262524232221201918171615

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48-Pin Part PinoutTable 6. 48-Pin Part Pinout (QFN )[2][1]

Pin No.

Type Pin Name Description Figure 15. CY8CPLC20 48-Pin PLC Device

Digital Analog1 IO I P2[3] Direct switched capacitor block


input.3 IO P4[7]4 IO P4[5]5 IO P4[3]6 IO P4[1]7 Power SMP Switch Mode Pump (SMP)

connection to external components required.

8 IO P3[7]9 IO P3[5]10 IO P3[3]11 IO P3[1]12 IO P5[3]13 IO P5[1]14 IO P1[7] I2C Serial Clock (SCL).15 IO P1[5] I2C Serial Data (SDA).16 IO P1[3]17 IO P1[1] Crystal (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK*.18 Power Vss Ground connection.19 IO P1[0] Crystal (XTALout), I2C Serial Data

(SDA), ISSP-SDATA*.20 IO P1[2]21 IO P1[4] Optional External Clock Input

(EXTCLK).22 IO P1[6]23 IO P5[0]24 IO P5[2]25 IO P3[0]26 IO P3[2]27 IO P3[4]28 IO P3[6]29 Input XRES Active high external reset with

internal pull down.30 IO P4[0]31 IO P4[2]32 IO P4[4]33 IO P4[6]34 IO I P2[0] Direct switched capacitor block


input.36 IO P2[4] External Analog Ground (AGND).37 IO P2[6] External Voltage Reference (VREF).38 IO I P0[0] Analog column mux input.39 IO IO P0[2] Analog column mux input and


column output.41 IO I P0[6] Analog column mux input.42 Power Vdd Supply voltage.43 IO I P0[7] Analog column mux input.44 IO IO P0[5] Analog column mux input and


column output.46 IO I P0[1] Analog column mux input.47 IO P2[7]48 IO P2[5]

LEGEND: A = Analog, I = Input, and O = Output.

QFN(Top View)

P2[5]

P2[7]

P0[1]

, A, I

P0[3]

, A, IO

P0[5]

, A, IO

P0[7]

, A, I

Vdd

P0[6]

, A, I

P0[4]

, A, IO

P0[2]

, A, IO

P0[0]

, A, I

P2[6]

, Exte

rnal

VREF

101112

A, I, P2[3]A, I, P2[1]

P4[7]P4[5]P4[3]P4[1]SMP

P3[7]P3[5]P3[3]P3[1]P5[3]

3534333231302928272625

3648 47 46 45 44 43 42 41 40 39 38 37

P2[2], A, IP2[0], A, IP4[6]P4[4]P4[2]P4[0]XRESP3[6]P3[4]P3[2]P3[0]

P2[4], External AGND123456789

13 14 15 16 17 18 19 20 21 22 23 24

P5[1]

I2C SC

L, P1

[7]I2

C SDA

, P1[

5]P1

[3] I2

C SCL

, XTA

Lin, P

1[1] Vss

I2C SD

A, XT

ALou

t, P1[

0]P1

[2]EX

TCLK

, P1[4

]P1

[6]P5

[0]P5

[2]

[+] Feedback




100-Pin Part Pinout (On-Chip Debug)The 100-pin TQFP part is for the CY8CPLC20-OCD On-Chip Debug PLCC device. Note that the OCD parts are only used for in-cir-cuit debugging. OCD parts are NOT available for production.

Table 7. 100-Pin OCD Part Pinout (TQFP)

Pin No. D

igita

l

Ana

log

Name Description Pin No. D

igita

l

Ana

log

Name Description

1 NC No internal connection. 51 NC No internal connection2 NC No internal connection. 52 IO P5[0]3 IO I P0[1] Analog column mux input 53 IO P5[2]4 IO P2[7] 54 IO P5[4]5 IO P2[5] 55 IO P5[6]6 IO I P2[3] Direct switched capacitor block input 56 IO P3[0]7 IO I P2[1] Direct switched capacitor block input 57 IO P3[2]8 IO P4[7] 58 IO P3[4]9 IO P4[5] 59 IO P3[6]10 IO P4[3] 60 HCLK OCD high speed clock output11 IO P4[1] 61 CCLK OCD CPU clock output12 OCDE OCD even data IO 62 Input XRES Active high pin reset with internal pull down13 OCDO OCD odd data output 63 IO P4[0]14 Power SMP Switch Mode Pump (SMP) connection to

required external components64 IO P4[2]

15 Power Vss Ground connection. 65 Power Vss Ground connection.16 IO P3[7] 66 IO P4[4]17 IO P3[5] 67 IO P4[6]18 IO P3[3] 68 IO I P2[0] Direct switched capacitor block input.19 IO P3[1] 69 IO I P2[2] Direct switched capacitor block input.20 IO P5[7] 70 IO P2[4] External Analog Ground (AGND) input.21 IO P5[5] 71 NC No internal connection.22 IO P5[3] 72 IO P2[6] External Voltage Reference (VREF) input.23 IO P5[1] 73 NC No internal connection.24 IO P1[7] I2C Serial Clock (SCL) 74 IO I P0[0] Analog column mux input.25 NC No internal connection. 75 NC No internal connection.26 NC No internal connection. 76 NC No internal connection.27 NC No internal connection. 77 IO IO P0[2] Analog column mux input and column output.28 IO P1[5] I2C Serial Data (SDA). 78 NC No internal connection.29 IO P1[3] IFMTEST IFMTEST 79 IO IO P0[4] Analog column mux input and column output,

VREF, VREF.30 IO P1[1]* Crystal (XTALin), I2C Serial Clock (SCL), TC

SCLKTC SCLK, TC SCLK.80 NC No internal connection.

31 NC No internal connection. 81 IO I P0[6] Analog column mux input.32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage.33 NC No internal connection. 83 Power Vdd Supply voltage.34 Power Vss Ground connection. 84 Power Vss Ground connection.35 NC No internal connection 85 Power Vss Ground connection.36 IO P7[7] 86 IO P6[0]37 IO P7[6] 87 IO P6[1]38 IO P7[5] 88 IO P6[2]39 IO P7[4] 89 IO P6[3]40 IO P7[3] 90 IO P6[4]41 IO P7[2] 91 IO P6[5]42 IO P7[1] 92 IO P6[6]43 IO P7[0] 93 IO P6[7]44 IO P1[0]* Crystal (XTALout), I2C Serial Data (SDA), TC

SDATA, TC SDATA94 NC No internal connection.

45 IO P1[2] VFMTESTVFMTEST 95 IO I P0[7] Analog column mux input.46 IO P1[4] Optional External Clock Input (EXTCLK) 96 NC No internal connection.47 IO P1[6] 97 IO IO P0[5] Analog column mux input and column output.48 NC No internal connection. 98 NC No internal connection.49 NC No internal connection. 99 IO IO P0[3] Analog column mux input and column output.

50 NC No internal connection. 100 NC No internal connection.

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test, TC/TM: Test.* ISSP pin which is not HiZ at POR.

Notes1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.2. The QFN package has a center pad that must be connected to ground (Vss).

[+] Feedback




Figure 16. CY8CPLC20-OCD

Not for Production

OCD TQFP

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

10111213141516171819202122232425

123456789

NCNC

AI, P0[1]P2[7]P2[5]

AI, P2[3]AI, P2[1]

P4[7]P4[5]P4[3]P4[1]

OCDEOCDO

SMPVss

P3[7]P3[5]P3[3]P3[1]P5[7]P5[5]P5[3]P5[1]

I2C SCL, P1[7]NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 5049

NC

Vss

P7[

3]

EXTC

LK, P

1[4]NC

I2C

SD

A, P

1[5]

P1[

3]XT

ALi

n, I2

C S

CL,

P1[

1] NC

Vdd NC

NC

P7[

7]P

7[6]

P7[

5]P

7[4]

P7[

2]P

7[1]

P7[

0]XT

ALo

ut, I

2C S

DA,

P1[

0]P

1[2]

P1[

6] NC

NC

NC

75747372717069686766656463626160595857565554535251

NCP0[0], AINCP2[6], External VREFNCP2[4], External AGNDP2[2], AIP2[0], AIP4[6]P4[4]VssP4[2]P4[0]XRESCCLKHCLKP3[6]P3[4]P3[2]P3[0]P5[6]P5[4]P5[2]P5[0]NC

NC

P0[

3], A

ION

CP

0[5]

, AIO

NC

P0[

7], A

IN

CP

6[7]

P6[

6]P

6[5]

P6[

4]P

6[3]

P6[

2]P

6[1]

P6[

0]V

ssV

ssV

ddV

ddP

0[6]

, AI

NC

P0[

4], A

ION

CP

0[2]

, AIO

NC

[+] Feedback




Register ReferenceThis chapter lists the registers of the CY8CPLC20 PLC device. For detailed register information, reference the PSoC Mixed-SignalArray Technical Reference Manual.

Register Conventions

Abbreviations UsedThe register conventions specific to this section are listed in thefollowing table.

Register Mapping TablesThe PSoC device has a total register address space of 512bytes. The register space is referred to as IO space and isdivided into two banks. The XOI bit in the Flag register (CPU_F)determines which bank the user is currently in. When the XOI bitis set the user is in Bank 1.Note In the following register mapping tables, blank fields arereserved and should not be accessed.

Convention DescriptionR Read register or bit(s)W Write register or bit(s)L Logical register or bit(s)C Clearable register or bit(s)# Access is bit specific

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Table 8. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr

(0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW DBB20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RWPRT0IE 01 RW DBB20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RWPRT0GS 02 RW DBB20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RWPRT0DM2 03 RW DBB20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RWPRT1DR 04 RW DBB21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RWPRT1IE 05 RW DBB21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RWPRT1GS 06 RW DBB21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RWPRT1DM2 07 RW DBB21CR0 47 # ASD11CR3 87 RW C7PRT2DR 08 RW DCB22DR0 48 # ASC12CR0 88 RW RDI3RI C8 RWPRT2IE 09 RW DCB22DR1 49 W ASC12CR1 89 RW RDI3SYN C9 RWPRT2GS 0A RW DCB22DR2 4A RW ASC12CR2 8A RW RDI3IS CA RWPRT2DM2 0B RW DCB22CR0 4B # ASC12CR3 8B RW RDI3LT0 CB RWPRT3DR 0C RW DCB23DR0 4C # ASD13CR0 8C RW RDI3LT1 CC RWPRT3IE 0D RW DCB23DR1 4D W ASD13CR1 8D RW RDI3RO0 CD RWPRT3GS 0E RW DCB23DR2 4E RW ASD13CR2 8E RW RDI3RO1 CE RWPRT3DM2 0F RW DCB23CR0 4F # ASD13CR3 8F RW CFPRT4DR 10 RW DBB30DR0 50 # ASD20CR0 90 RW CUR_PP D0 RWPRT4IE 11 RW DBB30DR1 51 W ASD20CR1 91 RW STK_PP D1 RWPRT4GS 12 RW DBB30DR2 52 RW ASD20CR2 92 RW D2PRT4DM2 13 RW DBB30CR0 53 # ASD20CR3 93 RW IDX_PP D3 RWPRT5DR 14 RW DBB31DR0 54 # ASC21CR0 94 RW MVR_PP D4 RWPRT5IE 15 RW DBB31DR1 55 W ASC21CR1 95 RW MVW_PP D5 RWPRT5GS 16 RW DBB31DR2 56 RW ASC21CR2 96 RW I2C_CFG D6 RWPRT5DM2 17 RW DBB31CR0 57 # ASC21CR3 97 RW I2C_SCR D7 #PRT6DR 18 RW DCB32DR0 58 # ASD22CR0 98 RW I2C_DR D8 RWPRT6IE 19 RW DCB32DR1 59 W ASD22CR1 99 RW I2C_MSCR D9 #PRT6GS 1A RW DCB32DR2 5A RW ASD22CR2 9A RW INT_CLR0 DA RWPRT6DM2 1B RW DCB32CR0 5B # ASD22CR3 9B RW INT_CLR1 DB RWPRT7DR 1C RW DCB33DR0 5C # ASC23CR0 9C RW INT_CLR2 DC RWPRT7IE 1D RW DCB33DR1 5D W ASC23CR1 9D RW INT_CLR3 DD RWPRT7GS 1E RW DCB33DR2 5E RW ASC23CR2 9E RW INT_MSK3 DE RWPRT7DM2 1F RW DCB33CR0 5F # ASC23CR3 9F RW INT_MSK2 DF RWDBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RWDBB00DR1 21 W 61 A1 INT_MSK1 E1 RWDBB00DR2 22 RW 62 A2 INT_VC E2 RCDBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 WDBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RCDBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RCDBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RWDBB01CR0 27 # 67 A7 DEC_CR1 E7 RWDCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 WDCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 WDCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA RDCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB RDCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RWDCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RWDCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RWDCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RWDBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3DBB11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RLDCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FADCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FBDCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FCDCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FDDCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #Blank fields are Reserved and should not be accessed. # Access is bit specific.

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Table 9. Register Map Bank 1 Table: Configuration Space Name Addr

(1,Hex) Access Name Addr(1,Hex) Access Name Addr

(1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0 00 RW DBB20FN 40 RW ASC10CR0 80 RW RDI2RI C0 RWPRT0DM1 01 RW DBB20IN 41 RW ASC10CR1 81 RW RDI2SYN C1 RWPRT0IC0 02 RW DBB20OU 42 RW ASC10CR2 82 RW RDI2IS C2 RWPRT0IC1 03 RW 43 ASC10CR3 83 RW RDI2LT0 C3 RWPRT1DM0 04 RW DBB21FN 44 RW ASD11CR0 84 RW RDI2LT1 C4 RWPRT1DM1 05 RW DBB21IN 45 RW ASD11CR1 85 RW RDI2RO0 C5 RWPRT1IC0 06 RW DBB21OU 46 RW ASD11CR2 86 RW RDI2RO1 C6 RWPRT1IC1 07 RW 47 ASD11CR3 87 RW C7PRT2DM0 08 RW DCB22FN 48 RW ASC12CR0 88 RW RDI3RI C8 RWPRT2DM1 09 RW DCB22IN 49 RW ASC12CR1 89 RW RDI3SYN C9 RWPRT2IC0 0A RW DCB22OU 4A RW ASC12CR2 8A RW RDI3IS CA RWPRT2IC1 0B RW 4B ASC12CR3 8B RW RDI3LT0 CB RWPRT3DM0 0C RW DCB23FN 4C RW ASD13CR0 8C RW RDI3LT1 CC RWPRT3DM1 0D RW DCB23IN 4D RW ASD13CR1 8D RW RDI3RO0 CD RWPRT3IC0 0E RW DCB23OU 4E RW ASD13CR2 8E RW RDI3RO1 CE RWPRT3IC1 0F RW 4F ASD13CR3 8F RW CFPRT4DM0 10 RW DBB30FN 50 RW ASD20CR0 90 RW GDI_O_IN D0 RWPRT4DM1 11 RW DBB30IN 51 RW ASD20CR1 91 RW GDI_E_IN D1 RWPRT4IC0 12 RW DBB30OU 52 RW ASD20CR2 92 RW GDI_O_OU D2 RWPRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RWPRT5DM0 14 RW DBB31FN 54 RW ASC21CR0 94 RW D4PRT5DM1 15 RW DBB31IN 55 RW ASC21CR1 95 RW D5PRT5IC0 16 RW DBB31OU 56 RW ASC21CR2 96 RW D6PRT5IC1 17 RW 57 ASC21CR3 97 RW D7PRT6DM0 18 RW DCB32FN 58 RW ASD22CR0 98 RW D8PRT6DM1 19 RW DCB32IN 59 RW ASD22CR1 99 RW D9PRT6IC0 1A RW DCB32OU 5A RW ASD22CR2 9A RW DAPRT6IC1 1B RW 5B ASD22CR3 9B RW DBPRT7DM0 1C RW DCB33FN 5C RW ASC23CR0 9C RW DCPRT7DM1 1D RW DCB33IN 5D RW ASC23CR1 9D RW OSC_GO_EN DD RWPRT7IC0 1E RW DCB33OU 5E RW ASC23CR2 9E RW OSC_CR4 DE RWPRT7IC1 1F RW 5F ASC23CR3 9F RW OSC_CR3 DF RWDBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RWDBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RWDBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RWDBB01FN 24 RW 64 A4 VLT_CMP E4 RDBB01IN 25 RW 65 A5 E5DBB01OU 26 RW AMD_CR1 66 RW A6 E6

27 ALT_CR0 67 RW A7 DEC_CR2 E7 RWDCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 WDCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 WDCB02OU 2A RW 6A AA BDG_TR EA RW

2B 6B AB ECO_TR EB WDCB03FN 2C RW TMP_DR0 6C RW AC ECDCB03IN 2D RW TMP_DR1 6D RW AD EDDCB03OU 2E RW TMP_DR2 6E RW AE EE

2F TMP_DR3 6F RW AF EFDBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

33 ACB00CR2 73 RW RDI0LT0 B3 RW F3DBB11FN 34 RW ACB01CR3 74 RW RDI0LT1 B4 RW F4DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

37 ACB01CR2 77 RW B7 CPU_F F7 RLDCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FLS_PR1 FA RW

3B ACB02CR2 7B RW RDI1LT0 BB RW FBDCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FCDCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FDDCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

3F ACB03CR2 7F RW BF CPU_SCR0 FF #Blank fields are Reserved and should not be accessed. # Access is bit specific.

[+] Feedback




Electrical SpecificationsThis chapter presents the DC and AC electrical specifications of the CY8CPLC20 PLC device. For the most up to date electricalspecifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.

Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.

Refer to Table 26 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

Figure 17. Voltage versus CPU Frequency Figure 18. IMO Frequency Trim Options

The following table lists the units of measure that are used in this chapter.

Table 10. Units of Measure

Symbol Unit of Measure Symbol Unit of MeasureoC degree Celsius μW microwattsdB decibels mA milli-amperefF femto farad ms milli-secondHz hertz mV milli-voltsKB 1024 bytes nA nanoampereKbit 1024 bits ns nanosecondkHz kilohertz nV nanovoltskΩ kilohm Ω ohm

MHz megahertz pA picoampereMΩ megaohm pF picofaradμA microampere pp peak-to-peakμF microfarad ppm parts per millionμH microhenry ps picosecondμs microsecond sps samples per secondμV microvolts s sigma: one standard deviation

μVrms microvolts root-mean-square V volts

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Vdd Voltage

5.25

4.75

3.00

93 kHz 12 MHz 24 MHzIMO Frequency

Vdd Voltage

3.60

6 MHz

SLIM

O M

ode

= 0

SLIMOMode=0

SLIMOMode=1

Valid

Operating

Region

SLIMOMode=1

SLIMOMode=0

[+] Feedback

http://www.cypress.com/psoc




Absolute Maximum Ratings

Operating Temperature

DC Electrical Characteristics

DC Chip-Level SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 11. Absolute Maximum Ratings

Symbol Description Min Typ Max Units NotesTSTG Storage Temperature -55 25 +100 oC Higher storage temperatures reduces

data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage tempera-tures above 65oC degrades reliability.

TA Ambient Temperature with Power Applied

-40 – +85 oC

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 VVIO DC Input Voltage Vss -

0.5– Vdd +

0.5V

VIOZ DC Voltage Applied to Tri-state Vss - 0.5

– Vdd + 0.5

V

IMIO Maximum Current into any Port Pin -25 – +50 mAIMAIO Maximum Current into any Port Pin

Configured as Analog Driver-50 – +50 mA

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.LU Latch-up Current – – 200 mA

Table 12. Operating Temperature

Symbol Description Min Typ Max Units NotesTA Ambient Temperature -40 – +85 oCTJ Junction Temperature -40 – +100 oC The temperature rise from ambient to

junction is package specific. See Thermal Impedances.The user must limit the power consumption to comply with this requirement.

Table 13. DC Chip-Level Specifications

Symbol Description Min Typ Max Units NotesVdd Supply Voltage 3.00 – 5.25 V See DC POR and LVD specifications,

Table 24.IDD Supply Current – 8 14 mA Conditions are 5.0V, TA = 25 oC, CPU

= 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

IDD3 Supply Current – 5 9 mA Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

[+] Feedback




DC General Purpose IO SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

IDDP Supply current when IMO = 6 MHz using SLIMO Mode.

– 2 3 mA Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.

ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Slow Oscillator Active.

– 3 10 μA Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.

ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Slow Oscillator Active.

– 4 25 μA Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC.

ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Slow Oscillator, and 32 kHz Crystal Oscillator Active.

– 4 12 μA Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC.

ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz Crystal Oscillator Active.

– 5 27 μA Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85 oC.

VREF Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vdd.

Table 14. DC GPIO SpecificationsSymbol Description Min Typ Max Units Notes

RPU Pull Up Resistor 4 5.6 8 kΩRPD Pull Down Resistor 4 5.6 8 kΩVOH High Output Level Vdd -

1.0– – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget.

VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget.

VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.VIH Input High Level 2.1 – V Vdd = 3.0 to 5.25.VH Input Hysterisis – 60 – mVIIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp =

25oC.COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp =

25oC.

Table 13. DC Chip-Level Specifications (continued)

Symbol Description Min Typ Max Units Notes

[+] Feedback




DC Operational Amplifier SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoCblocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at25°C and are for design guidance only.

Table 15. 5V DC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units Notes

VOSOA Input Offset Voltage (absolute value) Power = Low, Opamp Bias = HighPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

– 1.6 1.3 1.2

10 8 7.5

mV mV mV

––

TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/oCIEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25 oC. VCMOA Common Mode Voltage Range. All cases,

except highest.Power = High, Opamp Bias = High

0.0 – VddVdd - 0.5

VV0.5 –

CMRROA Common Mode Rejection Ratio 60 – – dBGOLOA Open Loop Gain 80 – – dBVOHIGHOA High Output Voltage Swing (internal signals) Vdd -

0.01– – V

VOLOWOA Low Output Voltage Swing (internal signals) – – 0.1 VISOA Supply Current (including associated AGND

buffer)Power = Low, Opamp Bias = LowPower = Low, Opamp Bias = HighPower = Medium, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = LowPower = High, Opamp Bias = High

––––––

150300600120024004600

200400800160032006400

μAμAμAμAμAμA

PSRROA Supply Voltage Rejection Ratio 67 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd.

Table 16. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units NotesVOSOA Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = HighPower = Medium, Opamp Bias = HighHigh Power is 5 Volts Only

––

1.65 1.32

10 8

mV mV

TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/oCIEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25 oC.VCMOA Common Mode Voltage Range 0 – Vdd VCMRROA Common Mode Rejection Ratio 60 – – dBGOLOA Open Loop Gain 80 – – dBVOHIGHOA High Output Voltage Swing (internal signals) Vdd -

0.01– – V

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DC Low Power Comparator SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parametersapply to 5V at 25°C and are for design guidance only.

DC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

VOLOWOA Low Output Voltage Swing (internal signals) – – .01 VISOA Supply Current (including associated AGND

buffer)Power = Low, Opamp Bias = LowPower = Low, Opamp Bias = HighPower = Medium, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = LowPower = High, Opamp Bias = High

––––––

15030060012002400–

20040080016003200–

μAμAμAμAμA

Not Allowed

PSRROA Supply Voltage Rejection Ratio 54 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd

Table 16. 3.3V DC Operational Amplifier Specifications (continued)


Table 17. DC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units Notes

VREFLPC Low Power Comparator (LPC) Reference Voltage Range

0.2 – Vdd - 1 V

ISLPC LPC Supply Current – 10 40 μAVOSLPC LPC Voltage Offset – 2.5 30 mV

Table 18. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesVOSOB Input Offset Voltage (Absolute Value) – 3 12 mVTCVOSOB

Average Input Offset Voltage Drift – +6 – μV/°C

VCMOB Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 VROUTOB Output Resistance

Power = LowPower = High

––

––

11

WW

VOHIGHOB

High Output Voltage Swing (Load = 32 ohms to Vdd/2)Power = LowPower = High

0.5 x Vdd + 1.30.5 x Vdd + 1.3

––

––

VV

VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2)Power = LowPower = High

––

––

0.5 x Vdd - 1.30.5 x Vdd - 1.3

VV

ISOB Supply Current Including Bias Cell (No Load)Power = LowPower = High

––

1.12.6

25

mAmA

PSRROB Supply Voltage Rejection Ratio 40 64 – dB

[+] Feedback




DC Switch Mode Pump SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 19. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesVOSOB Input Offset Voltage (Absolute Value) – 3 12 mVTCVOSOB Average Input Offset Voltage Drift – +6 – μV/°CVCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 VROUTOB Output Resistance

Power = LowPower = High

––

––

1010

WW

VOHIGHOB

High Output Voltage Swing (Load = 1k ohms to Vdd/2)Power = LowPower = High

0.5 x Vdd + 1.00.5 x Vdd + 1.0

––

––

VV

VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2)Power = LowPower = High

––

––

0.5 x Vdd - 1.00.5 x Vdd - 1.0

VV

ISOB Supply Current Including Bias Cell (No Load)Power = LowPower = High –

0.82.0

15

mAmA

PSRROB Supply Voltage Rejection Ratio 60 64 – dB

Table 20. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes[3]

VPUMP 5V 5V Output Voltage at Vdd from Pump

4.75 5.0 5.25 V Average, neglecting ripple. SMP trip voltage is set to 5.0V.

VPUMP 3V 3V Output Voltage at Vdd from Pump

3.00 3.25 3.60 V Average, neglecting ripple. SMP trip voltage is set to 3.25V.

IPUMP Available Output CurrentVBAT = 1.5V, VPUMP = 3.25VVBAT = 1.8V, VPUMP = 5.0V

85

––

––

mAmA

SMP trip voltage is set to 3.25V.SMP trip voltage is set to 5.0V.

VBAT5V Input Voltage Range from Battery 1.8 – 5.0 V SMP trip voltage is set to 5.0V.VBAT3V Input Voltage Range from Battery 1.0 – 3.3 V SMP trip voltage is set to 3.25V.VBATSTART Minimum Input Voltage from

Battery to Start Pump1.2 – – V 0oC ≤ TA ≤ 100. 1.25V at TA = -40oC.

ΔVPUMP_Line

Line Regulation (over VBAT range) – 5 – %VO VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27.

ΔVPUMP_Load

Load Regulation – 5 – %VO VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27.

ΔVPUMP_Ripple

Output Voltage Ripple (depends on capacitor/load)

– 100 – mVpp Load is 5 mA.

E3 Efficiency 35 50 – % Load is 5 mA. SMP trip voltage is set to 3.25V.FPUMP Switching Frequency – 1.4 – MHzDCPUMP Switching Duty Cycle – 50 – %

[+] Feedback




Figure 18. Basic Switch Mode Pump Circuit

DC Analog Reference SpecificationsTable 21 and Table 22 list guaranteed maximum and minimumspecifications for the voltage and temperature ranges: 4.75V to5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤85°C, respectively. Typical parameters apply to 5V and 3.3V at25°C and are for design guidance only.The guaranteed specifications are measured through the AnalogContinuous Time PSoC blocks. The power levels for AGND referto the power of the Analog Continuous Time PSoC block. Thepower levels for RefHi and RefLo refer to the Analog ReferenceControl register. The limits stated for AGND include the offseterror of the AGND buffer local to the Analog Continuous TimePSoC block. Reference control power is high.Note Avoid using P2[4] for digital signaling when using an analogresource that depends on the Analog Reference. Some couplingof the digital signal may appear on the AGND.

Battery

C1

D1

+PSoC

Vdd

Vss

SMPVBAT

VPUMP

L1

Table 21. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max UnitsVBG5 Bandgap Voltage Reference 5V 1.28 1.30 1.32 V– AGND = Vdd/2[4] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V– AGND = 2 x BandGap[4] 2.52 2.60 2.72 V– AGND = P2[4] (P2[4] = Vdd/2)[4] P2[4] - 0.013 P2[4] P2[4] + 0.013 V– AGND = BandGap[4] 1.27 1.3 1.34 V– AGND = 1.6 x BandGap[4] 2.03 2.08 2.13 V– AGND Block to Block Variation (AGND = Vdd/2)[4] -0.034 0.000 0.034 V– RefHi = Vdd/2 + BandGap Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V– RefHi = 3 x BandGap 3.75 3.9 4.05 V– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] =

1.3V)P2[4] + P2[6] - 0.058

P2[4] + P2[6] P2[4] + P2[6] + 0.058

V

– RefHi = 2 x BandGap 2.50 2.60 2.70 V– RefHi = 3.2 x BandGap 4.02 4.16 4.29 V– RefLo = Vdd/2 – BandGap Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231 V– RefLo = BandGap 1.20 1.30 1.40 V– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -

0.042P2[4] - P2[6] P2[4] - P2[6] +

0.042V

[+] Feedback




DC Analog PSoC Block SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 22. 3.3V DC Analog Reference Specifications

Symbol Description[4] Min Typ Max UnitsVBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V

– AGND = Vdd/2 Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V

– AGND = 2 x BandGap Not Allowed– AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009 V

– AGND = BandGap 1.27 1.30 1.34 V

– AGND = 1.6 x BandGap 2.03 2.08 2.13 V

– AGND Block to Block Variation (AGND = Vdd/2)a

-0.034 0.000 0.034 mV

– RefHi = Vdd/2 + BandGap Not Allowed– RefHi = 3 x BandGap Not Allowed– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] =

0.5V)P2[4] + P2[6] - 0.042

P2[4] + P2[6] P2[4] + P2[6] + 0.042

V

– RefHi = 2 x BandGap 2.50 2.60 2.70 V

– RefHi = 3.2 x BandGap Not Allowed– RefLo = Vdd/2 - BandGap Not Allowed– RefLo = BandGap Not Allowed– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] =

0.5V)P2[4] - P2[6] - 0.036

P2[4] - P2[6] P2[4] - P2[6] + 0.036

V

Table 23. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units NotesRCT Resistor Unit Value (Continuous Time) – 12.2 – kΩCSC Capacitor Unit Value (Switch Cap) – 80 – fF

Notes3. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 184. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V

[+] Feedback




DC POR, SMP, and LVD SpecificationsTable 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for designguidance only.

Table 24. DC POR, SMP, and LVD Specifications


VPPOR0RVPPOR1RVPPOR2R

Vdd Value for PPOR Trip (positive ramp)PORLEV[1:0] = 00B

PORLEV[1:0] = 01B

PORLEV[1:0] = 10B–

2.914.394.55

–VVV

VPPOR0VPPOR1VPPOR2

Vdd Value for PPOR Trip (negative ramp)PORLEV[1:0] = 00bPORLEV[1:0] = 01bPORLEV[1:0] = 10b

–2.824.394.55

–VVV

VPH0VPH1VPH2

PPOR HysteresisPORLEV[1:0] = 00bPORLEV[1:0] = 01bPORLEV[1:0] = 10b

–––

9200

–––

mVmVmV

VLVD0VLVD1VLVD2VLVD3VLVD4VLVD5VLVD6VLVD7

Vdd Value for LVD TripVM[2:0] = 000bVM[2:0] = 001bVM[2:0] = 010bVM[2:0] = 011bVM[2:0] = 100bVM[2:0] = 101bVM[2:0] = 110bVM[2:0] = 111b

2.862.963.073.924.394.554.634.72

2.923.023.134.004.484.644.734.81

2.98[5]

3.083.204.084.574.74[6]

4.824.91

V

VVVVVVV

VPUMP0VPUMP1VPUMP2VPUMP3VPUMP4VPUMP5VPUMP6VPUMP7

Vdd Value for SMP TripVM[2:0] = 000bVM[2:0] = 001bVM[2:0] = 010bVM[2:0] = 011bVM[2:0] = 100bVM[2:0] = 101bVM[2:0] = 110bVM[2:0] = 111b

2.963.033.184.114.554.634.724.90

3.023.103.254.194.644.734.825.00

3.083.163.324.284.744.824.915.10

VVVVVVVV

Notes5. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.6. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply

[+] Feedback




DC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

AC Electrical CharacteristicsAC Chip-Level SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.Note See the individual user module data sheets for information on maximum frequencies for user modules.

Table 25. DC Programming Specifications

Symbol Description Min Typ Max Units NotesIDDP Supply Current During Programming or Verify – 10 30 mAVILP Input Low Voltage During Programming or

Verify– – 0.8 V

VIHP Input High Voltage During Programming or Verify

2.2 – – V

IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify

– – 0.2 mA Driving internal pull-down resistor

IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify

– – 1.5 mA Driving internal pull-down resistor

VOLV Output Low Voltage During Programming or Verify

– – Vss + 0.75

V

VOHV Output High Voltage During Programming or Verify

Vdd - 1.0 – Vdd V

FlashENPB

Flash Endurance (per block) 50,000 – – – Erase/write cycles per block

FlashENT Flash Endurance (total)[7] 1,800,000

– – – Erase/write cycles

FlashDR Flash Data Retention 10 – – Years

Table 26. AC Chip-Level Specifications

Symbol Description Min Typ Max Units NotesFIMO24 Internal Main Oscillator Frequency for 24 MHz 23.4 24 24.68,9,10 MHz Trimmed for 5V or 3.3V

operation using factory trim values. See the figure on page 19. SLIMO Mode = 0.

FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.358, 9,10

MHz Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 1.

FCPU1 CPU Frequency (5V Nominal) 0.93 24 24.68,9 MHzFCPU2 CPU Frequency (3.3V Nominal) 0.93 12 12.39,10 MHzF48M Digital PSoC Block Frequency 0 48 49.28,9,11 MHz Refer to the AC Digital Block

Specifications below.F24M Digital PSoC Block Frequency 0 24 24.69, 11 MHzF32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHzF32K2 External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and

crystal dependent. 50% duty cycle.

[+] Feedback




FPLL PLL Frequency – 23.986 – MHz A multiple (x732) of crystal frequency.

Jitter24M2 24 MHz Period Jitter (PLL) – – 600 psTPLLSLEW PLL Lock Time 0.5 – 10 msTPLLSLEWLOW

PLL Lock Time for Low Gain Setting 0.5 – 50 ms

TOS External Crystal Oscillator Startup to 1% – 250 500 msTOSACC External Crystal Oscillator Startup to 100 ppm – 300 600 ms The crystal oscillator frequency

is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V £ Vdd £ 5.5V, -40 oC £ TA £ 85 oC.

Jitter32k 32 kHz Period Jitter – 100 nsTXRST External Reset Pulse Width 10 – – μsDC24M 24 MHz Duty Cycle 40 50 60 %Step24M 24 MHz Trim Step Size – 50 – kHzFout48M 48 MHz Output Frequency 46.8 48.0 49.2[8, 10] MHz Trimmed. Utilizing factory trim

values.Jitter24M1 24 MHz Period Jitter (IMO) – 600 psFMAX Maximum frequency of signal on row input or

row output.– – 12.3 MHz

TRAMP Supply Ramp Time 0 – – μs

Table 26. AC Chip-Level Specifications (continued)


Notes7. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2

blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

8. 4.75V < Vdd < 5.25V9. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.10. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation

at 3.3V.11. See the individual user module data sheets for information on maximum frequencies for user modules.

[+] Feedback




Figure 19. PLL Lock Timing Diagram

Figure 20. PLL Lock for Low Gain Setting Timing Diagram

Figure 21. External Crystal Oscillator Startup Timing Diagram

Figure 22. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 23. 32 kHz Period Jitter (ECO) Timing Diagram

24 MHz

FPLL

PLLEnable

TPLLSLEW

PLLGain 0

24 MHz

FPLL

PLLEnable

TPLLSLEWLOW

PLLGain 1

32 kHz

F32K2

32KSelect

TOS

Jitter24M1

F24M

Jitter32k

F32K2

[+] Feedback




AC General Purpose IO SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Figure 24. GPIO Timing Diagram

AC Operational Amplifier SpecificationsTable 28 and Table 29 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.Power = High and Opamp Bias = High is not supported at 3.3V.

Table 27. AC GPIO SpecificationsSymbol Description Min Typ Max Units Notes

FGPIO GPIO Operating Frequency 0 – 12.3 MHz Normal Strong ModeTRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

TFallFTFallS

TRiseFTRiseS

90%

10%

GPIOPin

OutputVoltage

Table 28. 5V AC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units Notes

TROA Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

–––

–––

3.90.720.62

μsμsμs

TSOA Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

–––

–––

5.90.920.72

μsμsμs

SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.151.76.5

–––

–––

V/μsV/μsV/μs

[+] Feedback




When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of upto 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.010.54.0

–––

–––

V/μsV/μsV/μs

BWOA Gain Bandwidth Product Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.753.15.4

–––

–––

MHzMHzMHz

ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High)

– 100 – nV/rt-Hz

Table 29. 3.3V AC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units Notes

TROA Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

––

––

3.920.72

μsμs

TSOA Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

––

––

5.410.72

μsμs

SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.312.7

––

––

V/μsV/μs

SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.241.8

––

––

V/μsV/μs

BWOA Gain Bandwidth Product Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.672.8

––

––

MHzMHz

ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High)

– 100 – nV/rt-Hz

Table 28. 5V AC Operational Amplifier Specifications (continued)


[+] Feedback




Figure 25. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At highfrequencies, increased power level reduces the noise spectrum level.

Figure 26. Typical Opamp Noise

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

00.010.11.010

10

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

nV/rtHz

PH_BHPH_BLPM_BLPL_BL

[+] Feedback




AC Low Power Comparator SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parametersapply to 5V at 25°C and are for design guidance only.

AC Digital Block SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 30. AC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units Notes

TRLPC LPC response time – – 50 μs ≥ 50 mV overdrive comparator reference set within VREFLPC.

Table 31. AC Digital Block Specifications

Function Description Min Typ Max Units NotesAll Functions

Maximum Block Clocking Frequency (> 4.75V) 49.2 MHz 4.75V < Vdd < 5.25V.Maximum Block Clocking Frequency (< 4.75V) 24.6 MHz 3.0V < Vdd < 4.75V.

Timer Capture Pulse Width 50[12] – – nsMaximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.Maximum Frequency, With Capture – – 24.6 MHz

Counter Enable Pulse Width 50[12] – – nsMaximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.Maximum Frequency, Enable Input – – 24.6 MHz

Dead Band

Kill Pulse Width:Asynchronous Restart Mode 20 – – nsSynchronous Restart Mode 50[12] – – nsDisable Mode 50[12] – – ns

Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.CRCPRS(PRS Mode)

Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.

CRCPRS(CRC Mode)

Maximum Input Clock Frequency – – 24.6 MHz

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.1 nsWidth of SS_ Negated Between Transmissions 50[12] – – ns

Trans-mitter

Maximum Input Clock FrequencyVdd ≥ 4.75V, 2 Stop Bits

–

–

–

–

24.6

49.2

MHz

MHz

Maximum data rate at 3.08 MHz due to 8 x over clocking.Maximum data rate at 6.15 MHz due to 8 x over clocking.

Receiver Maximum Input Clock FrequencyVdd ≥ 4.75V, 2 Stop Bits

–

–

–

–

24.6

49.2

MHz

MHz

Maximum data rate at 3.08 MHz due to 8 x over clocking.Maximum data rate at 6.15 MHz due to 8 x over clocking.

Note12.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period)

[+] Feedback




AC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 32. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesTROB Rising Settling Time to 0.1%, 1V Step, 100pF

LoadPower = LowPower = High

––

––

44

μsμs

TSOB Falling Settling Time to 0.1%, 1V Step, 100pF LoadPower = Low Power = High

––

––

3.43.4

μsμs

SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF LoadPower = LowPower = High

0.50.5

––

––

V/μsV/μs

SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF LoadPower = LowPower = High

0.550.55

––

––

V/μsV/μs

BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF LoadPower = LowPower = High

0.80.8

––

––

MHzMHz

BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF LoadPower = LowPower = High

300300

––

––

kHzkHz

Table 33. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesTROB Rising Settling Time to 0.1%, 1V Step, 100pF

Load Power = Low Power = High

––

––

4.74.7

μsμs

TSOB Falling Settling Time to 0.1%, 1V Step, 100pF LoadPower = Low Power = High

––

––

44

μsμs

SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF LoadPower = LowPower = High

.36

.36––

––

V/μsV/μs

SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF LoadPower = LowPower = High

.4

.4––

––

V/μsV/μs

[+] Feedback




AC External Clock SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF LoadPower = LowPower = High

0.70.7

––

––

MHzMHz

BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF LoadPower = LowPower = High

200200

––

––

kHzkHz

Table 34. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency 0.093 – 24.6 MHz– High Period 20.6 – 5300 ns– Low Period 20.6 – – ns– Power Up IMO to Switch 150 – – μs

Table 33. 3.3V AC Analog Output Buffer Specifications (continued)


Table 35. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12

MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle require-ments.

FOSCEXT Frequency with CPU Clock divide by 2 or greater

0.186 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.

– High Period with CPU Clock divide by 1 41.7 – 5300 ns– Low Period with CPU Clock divide by 1 41.7 – – ns– Power Up IMO to Switch 150 – – μs

[+] Feedback




AC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

AC I2C SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 36. AC Programming Specifications

Symbol Description Min Typ Max Units NotesTRSCLK Rise Time of SCLK 1 – 20 nsTFSCLK Fall Time of SCLK 1 – 20 nsTSSCLK Data Set up Time to Falling Edge of SCLK 40 – – nsTHSCLK Data Hold Time from Falling Edge of SCLK 40 – – nsFSCLK Frequency of SCLK 0 – 8 MHzTERASEB Flash Erase Time (Block) – 10 – msTWRITE Flash Block Write Time – 10 – msTDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

Table 37. AC Characteristics of the I2C SDA and SCL Pins

Symbol DescriptionStandard Mode Fast Mode

Units NotesMin Max Min Max

FSCLI2C SCL Clock Frequency 0 100 0 400 kHzTHDSTAI2C Hold Time (repeated) START Condition.

After this period, the first clock pulse is generated.

4.0 – 0.6 – μs

TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μsTHIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μsTSUSTAI2C Set-up Time for a Repeated START

Condition4.7 – 0.6 – μs

THDDATI2C Data Hold Time 0 – 0 – μsTSUDATI2C Data Set-up Time 250 – 100[13] – nsTSUSTOI2C Set-up Time for STOP Condition 4.0 – 0.6 – μsTBUFI2C Bus Free Time Between a STOP and

START Condition4.7 – 1.3 – μs

TSPI2C Pulse Width of spikes are suppressed by the input filter.

– – 0 50 ns

Note13.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This will automatically be

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

[+] Feedback




Figure 27. Definition for Timing for Fast/Standard Mode on the I2C Bus Packaging Dimensions

Packaging InformationThis chapter illustrates the packaging specifications for the CY8CPLC20 PLC device, along with the thermal impedances for eachpackage and the typical package capacitance on crystal pins.

Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulationtools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.

Figure 28. 28-Pin (210-Mil) SSOP

SDA

SCL

S Sr SP

TBUFI2C

TSPI2CTHDSTAI2C

TSUSTOI2CTSUSTAI2C

TLOWI2C

THIGHI2CTHDDATI2CTHDSTAI2C

TSUDATI2C

51-85079 *C

[+] Feedback

http://www.cypress.com/design/MR10161

http://www.cypress.com/design/MR10161




Figure 29. 48-Pin (7x7 mm) QFN

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note athttp://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.

001-12919 *A

[+] Feedback

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf




Figure 30. 100-Pin TQFP

Thermal Impedances Capacitance on Crystal Pins

Solder Reflow Peak TemperatureFollowing is the minimum solder reflow peak temperature to achieve good solderability.

51-85048 **51-85048 **

51-85048 *C

Table 38. Thermal Impedances per Package

Package Typical θJA[14]

28 SSOP 94 oC/W48 QFN[15] 28 oC/W100 TQFP 50 oC/W

Table 39. Typical Package Capacitance on Crystal PinsPackage Package Capacitance28 SSOP 2.8 pF48 QFN 1.8 pF

100 TQFP 3.1 pF

Notes14. TJ = TA + POWER x θJA 15. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.16. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

Table 40. Solder Reflow Peak Temperature

Package Minimum Peak Temperature[16] Maximum Peak Temperature

28 SSOP 240oC 260oC

48 QFN 220oC 260oC

100 TQFP 220oC 260oC

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Development Tool SelectionSoftware

PSoC Designer™At the core of the PSoC development software suite is PSoCDesigner used by thousands of PSoC developers. This robustsoftware has been facilitating PSoC designs for half a decade.PSoC Designer is available free of charge athttp://www.cypress.com under Order- Download Software.

PSoC Express™As the latest addition to the PSoC development software suite,PSoC Express is the first visual embedded system design toolthat enables a user to create an entire PSoC project andgenerate a schematic, BOM, and data sheet without writing asingle line of code. Users work directly with application objectssuch as LEDs, switches, sensors, and fans. PSoC Express isavailable free of charge at http://www.cypress.com/psocexpress.

PSoC ProgrammerPSoC Programmer is a very flexible programming application. Itis used on the bench in development and is also suitable forfactory programming. PSoC Programmer works either in astandalone configuration or operates directly from PSoCDesigner or PSoC Express. PSoC Programmer software iscompatible with both PSoC ICE Cube In-Circuit Emulator andPSoC MiniProg. PSoC programmer is available free of charge athttp://www.cypress.com/psocprogrammer.

CY3202-C iMAGEcraft C CompilerCY3202 is the optional upgrade to PSoC Designer that enablesthe iMAGEcraft C compiler. It is available at the Cypress OnlineStore at http://www.cypress.com, under Order. Click PSoC(Programmable System-on-Chip) to view a current list ofavailable items.

Development KitsAll development kits are sold at the Cypress Online Store.

CY3274-PLC HV Development KitThe CY3274-PLC is for prototyping and development on theCY8CPLC20 with PSoC Designer. This kit supports in-circuitemulation. The software interface enables users to run, halt, andsingle step the processor and view the content of specificmemory locations. PSoC Designer also supports the advancedemulation features. The hardware comprises of the High Voltagecoupling circuit for 110VAC-230VAC Powerline which iscompliant with the CENELEC/FCC standards. This board alsohas an onboard Switch Mode Power Supply. The kit comprises:

■ High Voltage (110-230VAC) PLC Board

■ CY8CPLC20-OCD (100TQFP)

■ Software CD

■ Supporting Literature

■ MiniProg

■ USB to I2C Bridge

CY3275-PLC LV Development KitThe CY3275-PLC is for prototyping and development on theCY8CPLC20 with PSoC Designer. This kit supports in-circuitemulation. The software interface enables users to run, halt, andsingle-step the processor and view the content of specificmemory locations. PSoC Designer also supports advancedemulation features. The hardware comprises of the Low Voltagecoupling circuit for 12-24V AC/DC Powerline. This board alsohas an onboard Switch Mode Power Supply. The kit comprises:

■ Low Voltage (12-24V AC/DC) PLC Board

■ CY8CPLC20-OCD (100TQFP)

■ Software CD

■ Supporting Literature

■ MiniProg

■ USB to I2C Bridge)

CY3215-DK Basic Development KitThe CY3215-DK is for prototyping and development with PSoCDesigner. This kit can be used in conjunction with the PLC kitsto support in-circuit emulation. The software interface enablesusers to run, halt, and single step the processor and view thecontent of specific memory locations. PSoC Designer alsosupports the advanced emulation features. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

CY3210-ExpressDK PSoC Express Development KitThe CY3210-ExpressDK is for advanced prototyping and devel-opment with PSoC Express (used with ICE-Cube In-CircuitEmulator). It provides access to I2C buses, voltage reference,switches, upgradeable modules, and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ Four Fan Modules

■ Two Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ USB 2.0 Cable

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■ Serial Cable (DB9)


■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples



Evaluation ToolsThe evaluation kits do not have onboard Powerline capability ,but can be used with a PLC kit for evaluation purposes. All evalu-ation tools are sold at the Cypress Online Store.

CY3210-MiniProg1The CY3210-MiniProg1 kit enables the user to program PSoCdevices via the MiniProg1 programming unit. The MiniProg is asmall, compact prototyping programmer that connects to the PCvia a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample


■ Getting Started Guide

■ USB 2.0 Cable

CY3210-PSoCEval1The CY3210-PSoCEval1 kit features an evaluation board andthe MiniProg1 programming unit. The evaluation board includesan LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kitincludes:

■ Evaluation Board with LCD Module


■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)



■ USB 2.0 Cable

CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a devel-opment board for the CY8C24794-24LFXI PSoC device. Specialfeatures of the board include both USB and capacitive sensingdevelopment and debugging support. This evaluation board alsoincludes an LCD module, potentiometer, LEDs, an enunciator,and plenty of bread boarding space to meet all of your evaluationneeds. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD


■ Wire Pack

Device ProgrammersAll device programmers are purchased from the Cypress OnlineStore.

CY3216 Modular ProgrammerThe CY3216 Modular Programmer kit features a modularprogrammer and the MiniProg1 programming unit. The modularprogrammer includes three programming module cards andsupports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards




■ USB 2.0 Cable

CY3207 ISSP In-System Serial Programmer (ISSP)The CY3207ISSP is a production programmer. It includesprotection circuitry and an industrial case that is more robust thanthe MiniProg in a production programming environment.Note that CY3207ISSP needs special software and is notcompatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD


■ USB 2.0 Cable

Third Party ToolsSeveral tools are specially designed by the following third partyvendors to accompany PSoC devices during development andproduction. Specific details of each of these tools are found athttp://www.cypress.com under Design >> Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on emulating the circuit before going to volume pro-duction using an on-chip debug (OCD) non-production PSoCdevice, see Application Note “Debugging - Build a PSoCEmulator into Your Board - AN2323” athttp://www.cypress.com/design/AN2323.

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Ordering Information

The following table lists the CY8CPLC20 PLC devices’ key package features and ordering codes.

Ordering Code Definitions

Table 41. CY8CPLC20 PLC Device Key Features and Ordering Information

Pack

age

Ord

erin

gC

ode

Flas

h(B

ytes

)

RA

M(B

ytes

)

Switc

h M

ode

Pum

p

Tem

pera

ture

Ran

ge

Dig

ital P

SoC

Blo

cks

Ana

log

PSoC

Blo

cks

Dig

ital I

OPi

ns

Ana

log

Inpu

ts

Ana

log

Out

puts

XRES

Pin

28-Pin (210 Mil) SSOP CY8CPLC20-28PVXI 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes28-Pin (210 Mil) SSOP

(Tape and Reel)CY8CPLC20-28PVXIT 32K 2K Yes -40C to +85C 16 12 24 12 4 Yes

48-Pin QFN CY8CPLC20-48LFXI 32K 2K Yes -40C to +85C 16 12 44 12 4 Yes100-Pin OCD TQFP[17] CY8CPLC20-OCD 32K 2K Yes -40C to +85C 16 12 64 12 4 Yes

CY 8 C PLC 20 - PC xxxPackage Type: Thermal Rating:

PX = PDIP Pb-Free C = CommercialSX = SOIC Pb-Free I = IndustrialPVX = SSOP Pb-Free E = ExtendedLFX/LKX = QFN Pb-FreeAX = TQFP Pb-Free

Pin Count: 28/48/100Programmability: PSoC CoreFamily Code: Powerline Communication SolutionTechnology Code: C = CMOSMarketing Code: 8 = Cypress PSoCCompany ID: CY = Cypress

Note17. This part may be used for in-circuit debugging. It is NOT available for production.

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Document Number: 001-48325 Rev** September 18, 2008 Page 45 of 45

PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registeredtrademarks referenced herein are property of the respective corporations.Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under thePhilips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All products and company namesmentioned in this document may be the trademarks of their respective holders.


© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of anycircuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as criticalcomponents in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the officeclosest to you, visit us at cypress.com/sales.

ProductsPSoC psoc.cypress.comClocks & Buffers clocks.cypress.comWireless wireless.cypress.comMemories memory.cypress.comImage Sensors image.cypress.com

PSoC SolutionsGeneral psoc.cypress.com/solutionsLow Power/Low Voltage psoc.cypress.com/low-powerPrecision Analog psoc.cypress.com/precision-analogLCD Drive psoc.cypress.com/lcd-driveCAN 2.0b psoc.cypress.com/canUSB psoc.cypress.com/usb

Document Title: CY8CPLC20 Powerline Communication SolutionDocument Number: 001-48325

Rev. ECN No. Orig. of Change

Submission Date Description of Change

** 2571957 GHH/PYRS 09/24/08 New Data Sheet

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CY8CPLC20 Powerline Communication Solution