EX.NO: 1(a) PN SEQUENCE GENERATIONDATE:

Aim: To generate a pseudo noise (PN) sequence.

Apparatus Required:

S.NO APPARATUS QUANTITY1. IC74LS164 12. IC74LS86 1 3. Resistor 3.3KΩ 1 4. Capacitor 0.1µF 15. Trainer kit 1

Theory: A pseudo-noise (PN) sequence or maximum length sequence is defined as a coded sequence of 1s and 0s with certain autocorrelation properties. This sequence is basic to the operation of spread spectrum modulation. It is usually periodic in that a sequence of 1s and 0s repeat itself with a exactly known period. PN sequences are generated using a linear feedback shift register (IC74LS164).

Procedure:1. The circuit connections are made as shown in the circuit diagram.2. Reset the circuit.3. Give input (high) to pins 1 and 2.4. Then connect the EX-OR gate output to pins 1 and 2.5. The PN sequences are generated.

Truth table:(EX-OR Gate):

A B C0 0 00 1 11 0 11 1 0

IC74LS164:RESET CLOCK A B Qa Qb…. Qn

L X X X LL….L

H L X X No Change

H PGT H H H Shift

H PGT L X L Shift

H PGT X L L Shift

PN Sequence: Initial state:

Result: Thus PN sequence was generated using IC74LS164.

CLK Q0 Q1 Q2 Q3

1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1

EX NO: 1(b) GOLD SEQUENCE GENERATIONDATE:

Aim: To generate gold sequence using IC74LS164 (8 bit serial in parallel out shift register).

Apparatus Required:

S.NO COMPONENT QUANTITY1. IC74LS164 22. IC74LS86 13. Digital trainer kit 14. Resistor(3.3KΩ) 25. Capacitor(0.1µF) 2

Theory:

Gold sequence is the special case of PN- sequences. The generation of gold sequence is embedded in the gold theorem which states that g1(x) and g2(x) be preferred pair of primitive polynomial of degree n whose corresponding shift register generate maximal length sequence of period of 2n-1 and whose cross correlation function has magnitude less than or equal to

2(n+1)/2+1 for n is odd or 2(n+1)/2 +1 for n is evenThen shift register corresponding to product polynomial g1(x).g2(x) will generate 2n+1 different sequences. With each sequence having a period of 2n-1 and cross correlation between any pair of such sequences satisfying the “preceding condition” it must satisfies the following properties:

Balance property: The given sequence is said to posses good balance property if the number of binary ones differs from zeros by at most one digit in a period.

Run property: The run is defined as the sequence of single type of binary digits. Its properties states that among the runs of ones and zeros it is desirable that one half of each type are of length one

Correlation property: If period of sequence is compared term by term with any cyclic shift of itself, it is best if the number of agreements differs from the number of disagreements.

Procedure:1. The circuit connections are made as shown in the circuit diagram.2. The PN sequences are generated and observed on the LEDs for PRNS1 and

PRNS2.3. The PN sequences are EX-ORed to generate gold sequence.4. The gold sequence generated is verified using the truth table.

Observation:

Clk PNS1 PNS2 Gold sequenceQa Qb Qc Qd Qe Qa Qb Qc Qd Qe

Result: Thus the gold sequence was generated using IC74LS164 and IC74LS86 and verified manually.

EX.NO: 2 SCRAMBLER AND DESCRAMBLERDATE:

AIM: To obtain the scrambler and descrambler output using IC 74LS164.

APPARATUS REQUIRED:

S.NO Apparatus Required Quantity 1 IC74LS164 1 2 IC74LS86 1 3 Resistor 3.3K 1 4 Capacitor 0.1uf 1

BLOCK DIAGRAM:

PIN DIAGRAM:

FRAME SYNCHRONIZED SCRAMBLER AND DESCRAMBLER:

InputData

PN Sequence

Scrambled Data

OriginalSequence

PN Sequence

14 9

1 2 4 5 7

SELF SYNCHRONIZED SCRAMBLER AND DESCRAMBLER:

14 9

1 2 4 5 7

FUNCTIONAL DIAGRAM:

FRAME SYNCHRONIZED SCRAMBLER

FRAME SYNCHRONIZED DESCRAMBLER

SELF SYNCHRONIZED SCRAMBLER

SELF SYNCHRONIZED DESCRAMBLER

THEORY:

A better method is to scramble the data before it modulates the carrier. The receiver circuitry must contain the corresponding descrambling algorithm to recover the bit sequence before data are sent to DTE. The purpose of a scrambler is not simply to detect the occurrence of a undesirable bit sequence and convert it to more acceptable pattern. In general scrambler tends to make the data more random by removing long strings of 1’s and 0’s. Scrambling can be helpful in timing extraction by removing long strings of 0’s in binary data and are optimizes for that purpose. Such optimization may result in data. The scrambler consists of a feedback register and the matching descrambler has feed forward shift register. Each stage in shift register delays a bit by one unit. To analyze the scrambler and the matched descrambler, consider the output sequence of the scrambler. If S is the input sequence to the scrambler, then

S+DT+D3 T=T Where D represents the delay operator that is DT is the sequence T delayed by n units. The symbol indicates modulo 2 sums. Adding (D+D3) on both sides of the equation, we get S=T+ (D+D3) T = (1+ (D+D3)) T = (1+F) T Where f=D+D3

To design the descrambler at the receiver start with T, the sequence received at the descrambler, from the above equation.

S=T+FT =T+ (D+D3) T This equation where we regenerate the input sequence S from the received T is readily implemented by the descrambler. A single detection error in the received sequence T will affect there output bits in R. Hence scrambling has the disadvantage of causing multiple errors for a single bit received.

PROCEDURE:

1. Connect the PRBS sequence as shown in the figure with the message in logic 0 condition

2. Apply reset and observe LED’s 1,2,3,4 are in logic 0 condition. Ensure reset pin in logic 1 state

3. Apply INIT pulse momentarily so that Q of PRBS 1 & PRBS 2 becomes logic 1 with a slow clock.

4. Keep INIT switch in logic 0 state and LED 2 & LED 4 outputs flashing synchronously depending upon the clock speed.

5. Observe with the message input at logic 0, the message output is also 0, even though LED 2 & LED 4 are flashing.

6. Now keep message in at logic 1 and observe the message out at logic at 17. Observe that the message in and out follows each other irrespective of clock

speed.

FRAME SYNCHRONIZED SCRAMBLER:

Message input

Flip flop outputs Scrambled output Qa Qb Qc

FRAME SYNCHRONIZED DESCRAMBLER:

Scrambled output

Flip flop outputs Descrambled output Qa Qb Qc

SELF SYNCHRONIZED SCRAMBLER:

Message input

Flip flop outputs Scrambled output Qa Qb Qc

SELF SYNCHRONIZED DESCRAMBLER:

Scrambled output

Flip flop outputs Descrambled output Qa Qb Qc

RESULT:

Thus long ones and zeros have been eliminated by using frame and self synchronized scrambler and scrambled output are then descrambled to get original message input (long ones and zeros).

EX.NO: 3 DIRECT SEQUENCE SPREAD SPECTRUMDATE:

Aim: To provide a form of secure communication by using pseudo random noise sequence.

Apparatus Required:

S.NO APPARATUS QUANTITY1. IC74LS164 12. IC74LS86 1 3. IC74LS04 1 4. Capacitor 0.1µF 15. Resistor 3.3KΩ 1

Pin Diagram:

IC 74LS164

IC 7486 (XOR Gate)

Circuit Diagram

Functional Diagram

Theory:

An important attribute of spread spectrum modulation is that it can provide protection against externally generated interfering signals with finite power. The jamming signal may consist of a fairly powerful broadband noise, a multi-tone waveform that is directed at the receiver for the purpose of disrupting communication. Protection against jamming waveforms is provided by purposely making the information bearing signal occupy a bandwidth far in excess of the maximum bandwidth necessary to transmit. This has the effect of making the transmitted signal assume a noise like appearance so as to blend into the background. The relatively wide bandwidth of the transmitted signal is caused by an independent modulating waveform, called the spreading signal, and this signal must be known in the receiver in order for the message signal to be detected.The transmitted signal may be represented as

m(t) = c(t) * b(t)The received signal r(t) is

r(t) = m(t) + i(t) = [ c(t) * b(t) ] + i(t)

The received signal is passed through a low pass filter and the demodulating signal is obtained.

Applications

Though the communication system is primarily concerned in increasing efficiency in terms of bandwidth and SNR, in some applications we need to consider multiple-access capability, anti-jam capability, interference rejection or low probability of intercept capability. These objectives can be optimized using spread spectrum techniques.Multiple access capability is needed in cellular telephone and personal communication applications where many users share a band of frequencies because there is not enough available bandwidth to assign a permanent frequency channel to each user. Spread spectrum techniques can be used to provide simultaneous use of wide frequency band by many users via code division multiple access (CDMA) techniques. This is an alternate approach to band sharing. Two other such approaches are time-division multiple access (TDMA) and frequency-division multiple access (FDMA).

Procedure:

1. The circuit connections are made as shown in the diagram.2. The message signal is EX-ORed with the PN sequence.3. Thus the direct sequence spread spectrum is generated.4. Then it is demodulated again to produce the original message signal.

Tabulation:

CLOCK INPUT MESSAGE

FF OUTPUTS DSSOUTPUT

DEMODULATED OUTPUTQa Qb Qc Qd

111111111111111

Result:

Thus a message signal has been modulated and demodulated by means of direct sequence spread spectrum.

EX NO: 4 DIGITAL MODULATION TECHNIQUES

DATE:

AIM:

To perform the following digital modulation techniques, 1. amplitude shift keying using ring modulator and using IC40522. Phase shift keying3. Frequency shift keying.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY1. Transformer 230v/12-0-12v 22. Diode 1N4001 43. Function generator (0-15 MHZ) 24. Cathode ray oscilloscope (0-60MHZ) 15. IC 4052,IC 741 - 1,1

PIN DIAGRAM:

CONNECTION DIAGRAMS:

Pin diagram for DIP and SOIC

TRUTH TABLE:

CIRCUIT DIAGRAM:

AMPLITUDE SHIFT KEYING(ASK):

FREQUENCY SHIFT KEYING(FSK):

PHASE SHIFT KEYING(PSK):

7 +12V

-12V 4

THEORY:

ASK: (Amplitude shift keying):

The two binary values(0,1) are represented by two different amplitudes of the carrier.The binary ‘1’ is represented by the presence of the carrier.The binary ‘0’ is represented by the absence of the carrier.

S(t)= A sin(2ΠFct) -->binary 1 0 -->binary 0

FSK:(Frequency shift keying):

Here the two binary values are represented by two different frequencies near the carrier frequency.The resulting signal is

S(t)=A sin(2Πf1t) -->binary ‘1’ A sin(2Πf2t) -->binary ‘0’Where f1 and f2 are typically offset from the carrier frequency fc by equal but opposite amounts.

PSK(Phase shift keying):

Here the phase of the carrier signal is shifted to represent binary datas.Binary ‘0’ is represented by sending a signal burst of the same phase as the previous signal burst.A binary ‘1’ is represented by sending a signal burst of opposite phase to the preceding one . S(t)=A sin (2ΠFct+θ) -->binary ‘1’ A sin (2ΠFct) -->binary ‘0’

PROCEDURE:

1. Establish the circuit as shown in the diagram.2. Set the carrier signal as a sinusoidal wave and message signal of amplitude 0-a few volts.3. Now observe the amplitude shift keyed waveform on the CRO.4. Again set the message signal with positive and negative amplitude.5. Observe the PSK output on the CRO.

OBSERVATION:

ASK WAVEFORM:

PARAMETER MODULATINGINPUT

CARRIERSIGNAL

MODULATEDWAVE

FRQUENCY(KHz) 0 0 1 01 1

AMPLITUDE (V) 0 0 5 01 5

FSK WAVEFORM:

PARAMETER MODULATINGINPUT

CARRIERSIGNAL

MODULATEDWAVE

FREQUENCY(KHz) 0 1 10 11 10

AMPLITUDE (V) 0 5 5 51 5

PSK WAVEFORM:

PARAMETER MODULATINGINPUT

CARRIERSIGNAL

MODULATEDWAVE

FREQUENCY(KHZ) 0 1 1 11 1

AMPLITUDE(V) 0 5 5 51 5

PHASE(Degree) 0 00 1800 00

1 1800

RESULT: Thus the digital modulation techniques like Amplitude shift keying (using both ring modulator and IC4052),Phase shift Keying,Frequency shift keying were performed and output was verified.

EX NO: 5 QUADRATURE PHASE SHIFT KEYINGDATE:

AIM:

To design and to construct a quadrature phase shift keying generator circuit.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1. Resistor 1.5kΩ1 kΩ

23

2. Function generator (0-15 MHZ) 23. Cathode ray oscilloscope (0-60MHZ) 14. IC 4052,IC 741 - 1,35. Capacitor 0.1µF 2

PIN DIAGRAM:

CIRCUIT DIAGRAM:

DESIGN:

Differentiator: Assume C1=0.1μF and fc=1KHz

Fo= 1/(2*П*R1*C1)

R1=1/(2*П*Fo*C1) R1=1.5 KΩ

PROCEDURE:

1. Establish the circuit as shown in the diagram.2. Set the carrier signal as a sinusoidal wave and message signal of amplitude 0-a few volts.3. Again set the message signal with positive and negative amplitude.4. Observe the QPSK output on the CRO.

OBSERVATION:

S.NoDIGITAL DATA

I\P OUTPUT OUTPUT PARAMETERS

A B AMPLITUDE FREQUENCY1.2.3.4.

RESULT: Thus the quadrature shift keying generator circuit is constructed and the output is verified

Ex.No:6 CONVOLUTION CODESDate:

AIM:

To produce the convolution code by using 74LS164 and 74LS86.

APPARATUS REQUIRED:

S. No. Apparatus Range Quantity1. IC74LS164 - 12. IC74LS86 - 23. IC74LS04 - 14. IC74LS08 - 15. Resistor 3.3kΩ 16. Capacitor 0.1µF 1

THEORY:

A convolution encoder operates on the incoming message sequence continuously in serial manner. The encoder of a binary convolution code with rate 1/n, measured in bits per symbol may be viewed as a finite state machine that consists of an M-stage shift registers with prescribed connections to n-module 2 adders and a multiplier that serializes the output of the adders. An L-bits message sequence produces a coded output sequence produces a coded output sequence of length L+M bits. The code rate is r = L/n (L-M) bits/symbol. We have L>>M. Therefore r = 1/n. The constraint length of a convolution encoder is given in terms of message bits is defined as a number of shifts over which an M-stage shift register output can influence the encoder output. In an encoder, with an M-shift stage register, the memory of the encoder equals M message bits and (M+1) shifts are required for the message bit to enter the shift register and comes out.

BLOCK DIAGRAM:

CIRCUIT DIAGRAM:

MANUAL CALCULATION:I. m(D) = 1011;

g0 (D) = 1111;g1 (D) = 1101Message m (D) = 1+D2+D3

g0 (D) = 1+D+D2+D3;g1 (D) = 1+D+D3

C0 = m (D) g0 (D) = (1+D2+D3) (1+D+D2+D3) = 1+D+D3+D6

C0 = 1, 1, 0, 1, 0, 0, 1

C1 = m (D) g1 (D) = (1+D2+D3) (1+D+D3) = 1+D+D2+D3+D4+D5+D6

C1 = 1, 1, 1, 1, 1, 1, 1

Output = 11, 11, 01, 11, 01, 01, 11

II. m(x) = 1111

C0= 1010101

C1=1001011

Output = 11, 00, 10, 01, 10, 01, 11

OBSERVATION:

Message Convolution Code

Theoretical Practical1101 C0 = 1101001

C1 = 1111111Output = 11,11,01,11,01,01,11

1111 C0 = 1010101 C1= 1001011Output = 11,00,10,01,10,01,11

1101 C0 = 1010001C1 = 1001011

Output = 11,00,10,01,00,01,11

RESULT:Thus the convolution code is produced by using 74LS164 and 74LS86.

EEx.No:7Date:

CYCLIC CODE GENERATOR AND SYNDROME CALCULATOR

OBJECTIVE:

To generate parity bit using encoder for(7,4) Cyclic code to be generated for the given generator polynomial y(x)= 1+x+x^3 and also verify the syndrome calculator for the above polynomial.

APPARATUS REQUIRED:

THEORY:A binary code is said to be cyclic if

1. The sum of two code words is also a code word.2. Any cyclic shift of a code word is also a code word.

CODE GENERATOR:

Since there is no symbol for parity code in non-symmetric form systematic code is used.

1. Multiply the message polynomial D(x) with X(n-k) => D(x) * X(n-k).2. Divide with generator polynomial X(n-k)*D(x)/G(x).3. Remainder gives the parity bit.4. Form the code word as parity bit, message bit recombination.

SYNDROME CALCULATOR:

During the decoding if the syndrome is zero, there is no transmission error or if it is non-zero then there is a transmission error to be detected. The syndrome calculator can be constructed with use of q(x) which is identical to the encoder except that the received bits are fed into the (n-k) stages of the feedback shift registers from left. After shifting all the bits, the content of the shift registers define the desired syndrome. The correction can be obtained with the use of error pattern corresponding to the obtained syndrome.

PIN DIAGRAM:

S.NO COMPONENT QUANTITY1. IC 74175 1

2. IC 7486 1

3. Digital trainer kit 1

Code Generator:Block diagram:

D0(new)=input ex-or D2(previous)D1(new)=D0(new)ex-or D0(previous)D2(new)=D1(previous)

Circuit diagram:

Calculation:

1. G(x) =generator polynomial=1+x+x3

2. D(x) =message polynomial=1+x3

3. X(n-k)*D(x)=x3*(1+x3)

Remainder polynomial:x2+x=0

Code word: 1001 011 (message) (parity)The state of the register after giving last message bit=011.Hence the redundant bits are 011.The code word is formed as 1001011

Cylclic code Generation:

Syndrome calculator:

Block diagram:

S0 (new) = input ex-or (previous)S1 (new) = S0(previous)ex-or S2(previous)S2 (new)=S1(previous)

Circuit diagram:

Syndrome Calculator with no error: Shifts Received bits Register contents

FF1 FF2 FF301234567

X 1 1 0 1 0 0 1

0 1 1 0 0 1 1 0

00111100

00011110

Syndrome calculator with one bit error: 7 bit error 6 bit error 5 bit error 4 bit error 3 bit error 2 bit error 1 bit error1001010 1001001 1001111 1000011 1011011 1101011 0001011ff ff ff1 2 3

ff ff ff 1 2 3

ff ff ff1 2 3

ff ff ff1 2 3

ff ff ff1 2 3

ff ff ff1 2 3

ff ff ff1 2 3

0 0 00 0 01 0 00 1 01 0 11 0 00 1 0

0 0 01 0 00 1 00 0 10 1 00 0 11 1 0

0 0 01 0 01 1 01 1 10 0 11 1 00 1 1

0 0 01 0 01 1 00 1 11 1 11 0 11 0 0

0 0 01 0 01 1 00 1 10 1 10 1 11 1 1

0 0 01 0 01 1 00 1 10 1 11 1 10 0 1

0 0 01 0 01 1 00 1 10 1 11 1 11 0 1

1 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 0 0Syndrome Syndrome Syndrome Syndrome Syndrome Syndrome Syndrome

Error Correction: Received code word with no error or 1 bit errorr=(c+e)

Syndrome(s) Error pattern(e) Correct code vectorReceived code+error code(r+e)=(c+e)+e=c

1001011 000 0000000 1001011 1001010 101 0000001 1001011 1001001 111 0000010 1001011 1001111 011 0000100 1001011 1000011 110 0001000 1001011 1011011 001 0010000 1001011 1101011 010 0100000 1001011 0001011 100 1000000 1001011

Result:

Thus cyclic codes are generated and a syndrome calculator is designed to check for the errors appearing in the codes.

Ex.No:8

DIGITAL TO UNIFORM QUANTIZATION LEVEL DECODER

A IM : To construct the digital to uniform quantization level decoder circuit using IC 7493.

A PPARATUS R EQUIRED :

S.NO COMPONENT RANGE QUANTITY1 IC 741 - 12 IC 7493 - 1

3 Resistors750 Ω,1.5 K Ω3.0 KΩ,6.0 KΩ

1 k Ω1

4 CRO (0-60) MHz 1

P IN DIAGRAM :

S PECIFICATION :

IC 741 Supply voltage = + 12V & -12V Differential input voltage = 30 V Maximum power dissipation =500mW

C IRCUIT DIAGRAM :

Date:

D ESIGN :

Let Rf = 1 KΩ ; Vin = 3V

Vo = Rf * Vin/R

R = Vin*Rf/Vo

R = 3*1*103/0.5

R = 6 KΩ R/2 = 3 KΩ R/4 = 1.5 KΩ R/8 = 750 Ω

M ODEL GRAPH :

T HEORY :

The conversion of an analog sample of the signal into a digital form is called quantization process i.e. ., straight line representing the relation between input and the output of a linear analog system is replaced by transfer characteristics i.e. ., staircase like appearance. Quantization is achieved using a quantizer .The amplitude in a quantizer are called decision levels or decision thresholds .the amplitude levels at the quantizer output are called representation levels or reconstruction levels .The spacing between two adjacent representation levels are called as quantum step size .Quantizer can be uniform or non-uniform.

In a uniform quantizer, the representation levels are uniformly spaced.

P ROCEDURE :

(i) Establish the connection according to the circuit diagram(ii) Measure the output voltage on a CRO for each step corresponding to 1 KHz(iii) Equivalent from the LEDs corresponding t0 10 KHz(iv) Plot the graph

T ABULA TION :

Clock

Output Voltage

S.NoBinary Equivalent Output Voltage(V)

Qd Qc Qb Qa Theoretical Practical

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

-0.5

-1

-1.5

-2

-2.5

-3

-3.5

-4

-4.5

-5

-5.5

-6

-6.5

-7

-7.5

R ESULT : Thus the digital to uniform quantization level decoder is designed and its output is verified.

Ex.No:9Date:

BASE BAND SIMULATION OF PERFORMANCE ANALYSIS OF DIGITAL MODULATION

SYSTEMS IN AWGN CHANNEL

AIM:

To perform bit error rate analysis for ASK, PSK, FSK in MATLAB.

SOFTWARE REQUIRED:

MATLAB 7.0

T HEORY:

Bit Error Rate:

In Digital Communication, an error ratio is the ratio of the number of bits, elements, characters, or blocks incorrectly received to the total number of bits, elements, characters, or blocks sent during a specified time interval. The most commonly encountered ratio is the bit error ratio (BER) - also sometimes referred to as bit error rate.

ASK (Amplitude shift keying):

The two binary values (0, 1) are represented by two different amplitudes of the carrier. The binary ‘1’ is represented by the presence of the carrier. The binary ‘0’ is represented by the absence of the carrier.

S (t) = A sin (2ΠFct) -->binary 1 0 -->binary 0

The bit error rate (BER) of ASK in AWGN can be calculated as:

FSK (Frequency shift keying):

Here the two binary values are represented by two different frequencies near the carrier frequency. The resulting signal is

S (t) = A sin (2Πf1t) -->binary ‘1’ A sin (2Πf2t) -->binary ‘0’Where f1 and f2 are typically offset from the carrier frequency fc by equal but opposite amounts.

The bit error rate (BER) of FSK in AWGN can be calculated as:

PSK (Phase shift keying):

Here the phase of the carrier signal is shifted to represent binary data. Binary ‘0’ is represented by sending a signal burst of the same phase as the previous signal burst. A binary ‘1’ is represented by sending a signal burst of opposite phase to the preceding one. S (t) = A sin (2ΠFct+θ) -->binary ‘1’ A sin (2ΠFct) -->binary ‘0’

The bit error rate (BER) of PSK in AWGN can be calculated as:

ASK - Bit Error Rate Analysis:

clc;clear all;close all;N=1000;data=randint(1, N);for snrindb=1:1:10 snrindb sigampask= (sqrt (2*10. ^ (snrindb/10))).*data; for monte=1:1:100 noise=randn (1, N); unit=noise/sort(var(noise)); rxsigask=sigampask+unit; for i=1:1:N if rxsigask(i)>(sqrt(2*10.^(snrindb/10)))/2 decask(i)=1; else decask(i)=0; end end error=0; for i=1:1:N if decask(i)~=data(i) error=error+1; end end ber(monte)=error/N; end pb(snrindb)=mean(ber);endsnr1=1:1:10;semilogy(snr1,pb,'r+-');hold ongrid on;snrindb=1:1:10;snr=10.^(snrindb/10);pbask=0.5*erfc(0.5*sqrt(snr));semilogy(snrindb,pbask,'kd-');legend('practical','theoretical');xlabel('SNR in dB');ylabel('PROBABILITY OF ERROR');title('PERFORMENCE OF ASK');

FSK - Bit Error Rate Analysis:

clc;clear all;close all;N=1000;data=randsrc(1,N,[1,0]);for snrindb=1:1:10 snrindb sigampfsk=(sqrt(2*10.^(snrindb/10))); for monte=1:1:100 noise1=randn(1,N); unit1=noise1/sqrt(var(noise1)); noise2=randn(1,N); unit2=noise2/sqrt(var(noise2)); for i=1:1:N if data(i)==1 rxsigfsk1(i)=sigampfsk+unit1(i); rxsigfsk2(i)=unit2(i); else rxsigfsk1(i)=unit1(i); rxsigfsk2(i)=sigampfsk+unit2(i); end end decfsk=(rxsigfsk1-rxsigfsk2)>0; error=0; for i=1:1:N if decfsk(i)~=data(i) error=error+1;

end end ber(monte)=error/N; end pb(snrindb)=mean(ber);endsnr1=1:1:10;semilogy(snr1,pb,'bs-');hold onsnrindb=1:1:10;snr=10.^(snrindb/10);pbfsk=0.5*erfc(sqrt(0.5*snr));semilogy(snrindb,pbfsk,'mo-');hold ongrid onlegend('practical','theoretical');xlabel('SNR in dB');ylabel('PROBABILITY OF ERROR');title('PERFORMENCE OF FSK');

PSK - Bit Error Rate Analysis:

clc;clear all;close all;N=1000;z=randn(1,N);for i=1:1:N if z(i)>0 data(i)=1; else data(i)=-1; endendfor SNRindB=1:1:10; pe(SNRindB)=0; np=10.^(-SNRindB/10); for monte=1:1:N; n=sqrt(np/2)*complex(randn(1,N)); n1=real(n); s=data+n1; for i=1:N if s(i)>0 dec(i)=+1; else dec(i)=-1; end end error=0; for i=1:N if dec(i)~=data(i) error=error+1; end end ber(monte)=error/N; end pe(SNRindB)=mean(ber);endSNRindB=1:1:10;semilogy(SNRindB,pe,'rd-');hold on;th=0.5*erfc(sqrt(10.^(SNRindB/10)));grid on;semilogy(SNRindB,th,'b+-');legend('practical','theoretical');xlabel('SNR in dB');ylabel('Probability of ERROR');title(‘PERFORMANCE OF PSK’);

RESULT:

Thus the performance of various digital modulation systems ASK, PSK, FSK in AWGN channel have been analyzed using MATLAB software and the corresponding BER is plotted.