DC/DC Buck Converter - hps.hs-regensburg.de

lektronikabor

Practical Training

DCDC Buck Converter

Martin J W Schubert

Elektroniklabor

Ostbayerische Technische Hochschule Regensburg

Regensburg

M Schubert Exmaple DCDC Buck Converter Regensburg Univ of Appl Sciences

- 2 -

Abstract A small project is solved as system design with mixed time-continuous and time-discrete circuitry The example is a digitally controlled DCDC buck converter

1 Introduction 11 Objectives The objective of this project for engineering students is to train system design using V-Model as process model Examples system is a DCDC buck converter

12 Project Tasks Intention is to model the system from top-level behavioral simulation eg with Spice behavioral models down to a bottom level detail view with VHDL Any group has to deliver a documentation Language is German or English The documentation has to be prepared in the typical publication format (title abstract

introduction main part summary references) The documentation has to cover the V-Model levels

+ specification requirements engineering + system top-level behavioral simulation (here Spice) + subsystem an algorithmic finite state machine model (here Matlab) + module (here VHDL) + implementation (hardware)

Any student must be able to handle the tools Cooperate with other group members but do not forget to handle the tools yourself too

13 Upside Down Process The experienced system designer is recommended to process V-Model top-town However when training students handling the tools for the first time learning success and understanding are better when the system is build bottom-up Or let us say when we ldquoscrumrdquo towards our goal introducing agile methods too


- 3 -

14 Possible Problems to Investigate Fig 14 shows a power supply of logic blocks of an FPGA stepping 33V down to 18V and 12V with LDO AME1117 by dissipating voltage difference as heat This corresponds to thermal losses of 45 and 64 respectively which is unsupportable for battery powered devices Later versions of this FPGA boards are equipped with DCDC converters using analog control circuits Our goal is to build a DCDC buck converter with digital control unit taking advantage of the computational power of the FPGA

(a) Schematics of an elderly FPGA board with energy efficient DCDC buck converter DCDC buck converter LM2676 [11] and low drop out (LDO) regulator AME1117 [12] that translate voltage differences to heat

(b) VCC12 VCC18 in (a) generated with LDOs (c) goal use configurable DCDC converters

Fig 14 Generation of core voltages for an FPGA


- 4 -

15 Outline The organization of this communication is as follows Section 1 introduces into this document Section 2 presents some procedural management models Section 3 defines the DCDC conversion task to be done Section 4 deals with modeling and characterization of the RLC lowpass Section 5 Section 6 Section 7 gives some concluding remarks and outlook Section 8 offers some references


- 5 -

2 Procedural Management Models Successful projects begin with accurate specifications

21 V-Model Among the different system models we decide for V-Model in this project It is an extension to the waterfall model (left branch only) by validation (right branch) V-Model was developed in 1991 for Deutsche Bundeswehr The latest version release 21 was published in 2017 [x]

Fig 21 Simple V-Model Structure Table 2 illustrates the system interpretation of this project We shall do subsystem design with Spice and Matlab in a first step using behavioral models then the design is broken down to finite state machines (FSMs) Module design translates Matlab FSMs to VHDL modules

Fig 22 V-Model interpretation and tools of this practical training


- 6 -

Table 22 V-Model layers general and for the particular project

Layer General Particular Requirements amp Specs

Requirements analysis System specification

System requirements specific (dt Lastenheft) Product specification (dt Pflichtenheft)

System System design System design w Spice andor Matlab-Simulink Subsystem Subsystem Design Cycle-based FSM model with Matlab code Module Module implementation VHDL design behavioral rarr rtl rarr synthesis Implementation Hardware Implementation Download into FPGA and test

22 Agile Methods Scrum Agile methods [2] typically intended for software development are less predetermined than V-Model [1] The most known agile method is probably Scrum [3] which is based on iterations as illustrated in Fig 22

Fig22 Scrum [3] development model One of many possible interpretations Classical process models Milestones must be reached Example A car must be ready

when sold Otherwise delivery will be delayed or work force increased AgileScrum Example Deadlines must be reached when practical training ends


- 7 -

23 System Description

231 General Procedure

The system description consisting of requirement specification and product specification is the measure wither a contract is fulfilled or not It has to obey Requirements specification (dt Lastenheft) Customer describes his needs Project specification (dt Pflichtenheft) Contractor describes how he intends to realize it Trade-off Costs ndash Time ndash Contents 232 Customerrsquos Requirements Specification (dt Lastenheft)

Desirable is a configurable DCDC converter with 8-bit input signal setUout allowing to adjust analog output voltage in steps of 1mV from 045hellip3V Maximum output current is 1A Fig 232 Generation of by 033V PWM signal

233 Contractorrsquos System Elaboration (dt Pflichtenheft)

Fig 233 Regulation of Uout by digitally controlled feedback loop


- 8 -

3 RLC Lowpass We will investigate the lowpass as 1 schematics ie component based model 2 translate it into a 2nd order polynomial model in s 3 translate it into a general 2nd order system model in s using zeros and A0 f0 D 4 translate it into a 2nd order polynomial model in z

31 Theory Understanding the Schematics

Fig 31 RLC lowpass (a) schematics (b) Bode diagram (c) pulse-with modulated signal At DC operation Iin = Iout in Fig 31 From reasons of power transmission efficiency we have to deliver Uin as pulse-width modulated (PWM) signal and smoothen it with the LC lowpass Resistors RC and RD cause losses and are therefore to be held as small as possible To stabilize the output voltage Uout we will later control Uin by a control unit To control Uin we will have to control the duty cycle of the PWM signal


- 9 -

32 Modeling amp Simulation

321 Component Based Modeling with Spice

Simulate the circuit of Fig 31 The author will proved the LTspice input files RLClowpass_1devicesasc and plt where the latter defines plot configurations only Fig 321 Simulation of the RLC lowpass using devices

Spice Notation In Fig 31 device names have the typical Spice naming rules with initials indicating their function C Capacitors I independent current sources L inductors R resistors V independent voltage sources a dot like in tran or params indicates a Spice directive and text after as semi-colon is comment eg achellip Parameterization You will find devices such as Rg Rw L Chellip have a name and a value In Fig 31 the values are provided as parameters defined within the params statement Voltages In the LTspice simulation in put deck shown in Fig 321 Vin corresponding to Uin of Fig 31 and is the internal voltage source of the waveform generator Vg is its output voltage that we measure (at plug labeled GenOut at oscilloscope DSO X-2024) and Vout1 corresponds to Uout in Fig 31 Capacitor and inductor C and L are the total capacitance and inductance values respectively which may be composed in reality of several parallel and or serial devices Resistors Rg is its output resistance of the voltage source and is typically 50Ω for waveform generators Rw is the wire resistance of the inductor and RC is the equivalent series resistance (ESR) of the capacitor The total driving resistance in Fig 31 is obtained from RD=Rg+Rw Exercise Get the schematics in Fig 321 simulated


- 10 -

322 Biquadratic (ldquobiquadrdquo) Polynomial in s

The circuit in Fig 31 can be represented with biquadratic (biquad) filters whereas bi stand for both numerator and denominator and quadratic for the second order polynomials in s We have the process and inference (ldquoquarrelrdquo) transfer functions

20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s

Models in s or z are linear and time invariant (LTI) allowing for linear superposition of independent sources which are here given by input voltage Uin and load current IL Consequently Fig 31 can be modeled as

out in LU PTF U QTF I

According to [LinearFeedbackLoops] parameters of PTF(s) and QTF(s) are obtained from

0 1pa 1p Ca C R 2 0pa

0 1p D Lb R G 1 ( )p C D D C L Lb R R R R G C G L 2 (1 )p C Lb R G LC

0q Da R 1 ( )q C Da R R C L 2q Ca R LC

0 0q pb b 1 1q pb b 2 2q pb b

Fig 322 shows on the left hand side the same circuit as Fig 321 and on the right side the same circuit made with voltage controlled voltage sources (Spice initial E) and a behavioral voltage source (Spice initial B) for the summation of PTF and QTF The parameters of the polynomials are computed from the device parameters within params directives Exercise Get the schematics in Fig 322 simulated Proof that V(out1) = V(out2)

Fig 322 Left circuit made from devices plus right circuit made from polynomials in s


- 11 -

323 NullsPolesConstant (npc) Model in s

Polynomials can be broken in product terms of their zeros as (1-ssn) where sn is the zero Zeros of denominator polynomials are called poles

1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s

Polynomials with real coefficients have either real zeros or pairs of conjugated-complex zeros that can be summarized as second order polynomial with real coefficients Using

0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s

with a zero in 1n and poles represented depending on |D|gt1 or lt1 as

2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s

represents the model with DC amplification A0 ω0 the intercept of the asymptotes of 0 and -40 dBdec in the Bode diagram and D a measure for the damping per wavelength According to [LinearFeedbackLoops] we compute the model parameters from

0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C

D LD D D 0C D LR R G 2

D CR R C

L

+

2LG L

C


- 12 -

Fig 323 Left circuit made from devices plus right circuit made from polynomials in s In Fig 323 the right hand side shows an extension of Fig 322 made from behavioral sources and the pole-zero-constant representation in s The author offers the respective LTspice simulation files with named RLClowpass_3npc Exercise Get the schematics in Fig 323 simulated Proof V(out1) = V(out2) = V(out3)


- 13 -

324 Polynomial Model in z

In the time-discrete domain we typical work with z rather than s whereas factor z-1 corresponds to a delay Ts In digital systems typically Ts=1fs with fs being the sampling frequency and z-1 is realized as flipflop (FF) Model analog FFs with switches causes a loss of AC simulation capability Therefore we model z-1 as delay here The mathematically correct relation ssTz e ln( )ss f z is typically approximated by 1 12 (1 ) (1 )ss f z z which

delivers after insertion of the biquad polynomial

2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q

d d z d z d d z d zPTF z PTF z U QTF z I U I

c c z c z c c z c z

with coefficients related to the time-discrete DCDC buck converter model computed from

xd0 = 2210 22 ss fafaa xd1 = 220 222 sfaa xd2 = 2210 22 ss fafaa

0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f

We can work with these parameters but to avoid a (mostly digital) division we typically seek to get 0 1c by 0x xc c c and 0x xd d c for =012

Exercise Get the schematics in Fig 324 simulated Proof V(outx) = V(outy) for xy=1hellip4

Fig 324 Circuit simulating the RLC oscillator model with polynomials in z R4C4 lowpass removes spikes

From 0 1 1 2 2 0 1 1 2 2n n n n n nd x d x d x c y c y c y follows

0 1 1 2 2 1 1 2 20

1n n n n n ny d x d x d x c y c y

c

in time-domain It is obvious that c0=1 saves numerical effort If this is not possible when all coefficients have to be integral numbers it is recommended to choose c0=2N with N being an integral number Then division by c0 can then be performed as bit-shift operation In frequency domain xn-k Xꞏz-k delivers the transfer function

1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -

33 Experimental Build and Characterize the RLC lowpass 331 Understanding DSO-X 2024A oscilloscope

Handling Oscilloscope Switch on oscilloscope Switch on channel 1 (CH1 yellow) only Connect plug Gen-Out Ch1 with a short USB cable Press key WaveGen then use buttons under screen to select -gt Waveform -gt Sinus (try different waveforms) -gt Frequency -gt turn leftmost button below with signature ldquoPush to Selectrdquo -gt 1000Hz -gt push to select -gt Amplitude 1 Vpp -gt Offset 500mV Press key AutoScale on top right of the button panel Turn big rotary knob over enlightened channel 1 LED -gt observe mvdiv units on top left edge of the screen Turn small rotary knob under enlightened channel 1 LED -gt observe yellow ground symbol on the left side of the screen Push key Cursors You should have Modus Manual Channel 1 Select cursor X1 with button under screen (Select X1 and then wait until accepted) -gt turn small rotary knob under signature ldquoPush to Selectrdquo to the first maximum -gt select Select cursor Y1 set it to the first maximum Select cursor X2 adjust it to second maximum Select cursor Y2 adjust it to second minimum In the right hand side of the screen read ΔX in 1KHz and ΔY in mV


- 15 -

Characterization of Oscilloscope Features

Fig 331 Measurement of in- and output impedances Measure Output Impedance RG of your Waveform Generator See Agilent InfiniiVision 2000 X-Series Oscilloscopes Userrsquos Guides Do you find the output impedance of the waveform generator (wavegen) 50Ω Measure output impedance Zout of your generator yourself Connect a resistor from the wavegenrsquos output to ground (You might Connect output and ground of the wavegen to a bread board to plug the resistor) Knowing that such wavegenrsquos are prepared to drive BNC cables with high frequencies we expect Zout = 50Ω Output a wave eg 500KHz 033V with load resistor RL rarr infin corresponding to S2 open or RL removed in Fig 331 Measure the maximum of Uout on your oscillopscope CH1 note it as Ucircoutinfin = 330V Now set load resistor RL asymp Zout (eg RL = 47Ω) corresponding to S2 open or RL removed in Fig 331 Measure Exact RL = 471Ω and maximum of UcircoutL = Ucircout(RL) = 159V

From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω

Important What is the input resistance of your Volt-meter (noted on the meter) RVin gt1MΩ Is RVinRG ge 200 to measure RG with an accuracy of 1 RVinRG asymp 19700 rarr yes Respect this result as generator output impedance RG in your Spice model


- 16 -

Measure Input Impedance Rin of your Oscilloscope Important Check on your oscilloscope what are the scopesrsquos input resistance Rin = 1MΩ and input capacitance Cin = 11 pF Is RVinRin ge 200 to measure Rin with an accuracy of 1 RVinRin asymp 1 rarr no As we cannot measure the input impedance directly we measure it indirectly Output a wave eg 500KHz 033V directoly to CH1 of your oscilloscope corresponding to S1 closed or RG=0 Measure the maximum of Uin on your oscillopscope CH1 note it as Ucircin0 = 330V Now insert a shunt resistor RS asymp Zin (eg RS = 1MΩ) corresponding to S1 open in Fig 331 Measure Exact RS = 1006MΩ and maximum of UcircinS = Ucircin(RS) = 165V

From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -

332 Build an RLC Lowpass

Sit on a lab table with your group number (We can change group numbers if you prefer a particular table) Take a breadboard and mark it with a paper notice with your group number It will be your board until semester ends We will now build the circuit illustrated in Fig 31 We will model and simulate with an LTspice model like RLClowpass_1devices as shown in Fig 321 Table 332 Groups and nominal device values (for available capacitors)

Gr 1 2 3 4 5 6 7 8 9 10 L μH 10 10 10 10 10 10 10 10 33 33 C1 min min min min min min min min min min C2 pF 330 330 330 330 330 330 330 330 330 330 C3 μF 100 120 150 220 330 470 680 820 100 150 3321 Setup 1 C = minimal Connect ground and GenOut of your DSO-X 2024A wavegen output to your breadboard On the bread board take the inductor of your group and build the circuit shown in Fig 31 Do not include resistors all resistors are unavoidable The load resistor RL=1GL and capacitor C1 is nothing than the unavoidable input impedance of the oscilloscopersquos CH1 input plus parasites Copy simulation model RLClowpass_1devices to model Gr_R=50_L=10uH_C1=min with being your group number Adopt the inductor to your grouprsquos value Do not use a load capacitor Open your spice model and set Rg to the value of your wavegen Measure inductance and serial resistance of your inductor (eg with HM8118) Plug only inductor L with your grouprsquos inductance according to Tab 332 What do you measure Adopt your Spice model to that values L = 116 μH Rw = 213 mΩ RD = Rg + Rw = 506 Ω Do not plug a capacitor C into your breadboard use your oscilloscopersquos CH1 input only as load impedance What do we get according to InfiniiVision 2000 X Userrsquos Guides C = 82 pF RL = 100 KΩ GL = 1RL = 10 μS

Argue why we can approximate 0 1 LC as observed oscillation frequency on our scope

Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

RD GL = 506Ωmiddot10μS = 5E-4 ltlt 1 RC GL lt 1Ωmiddot10μS = 10E-6 ltlt 1


- 18 -

Measure the frequency of oscillation on your oscilloscopersquos CH1 when CH1 is the only load Let T0 being the delay between first and second maximum of the step response on your oscilloscope f0 = 1T0 and ω01 = 2πꞏf0 Use cursors to measure T01 = 260 ns f01 = 385 MHz rarr ω01 = 242e6 rads Umax1 = 558 V Umax2 = 460 V ΔUmax = 0987 V What is the load capacitor CL1 of this test 1 that you are measuring Formula and value

CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF

This load capacitor is made up of CH1 input capacitance plus parasitic capacitance How big are the parasitic caps Cp Formula and value Cp = CL1 ndash CCH1 = 1473 pF ndash 85pF = 139 pF Verify these values with your Spice model use cursors 1 and 2 (In the LTspice graphics window click left mouse button on label V(out1) with cursor over this label click right mouse button and select ldquoAttached cursor 1st amp 2ndrdquo) T01 = 258 ns f01 = 388 MHz ω01 = 244e6 rads Umax1 = 576 V Umax2 = 468 V ΔUmax = 1076 V Are the tolerances acceptable yes Why does this setup oscillate We know that the 2nd order model generates complex poles when damping constant Dlt1 We can approximate


D CR R C

L

+

2LG L

C

2D CR R C

L

Calculate approximated D for Situation 1 termed D1

1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009

Calculate A0 for setup 1 termed A01

01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -

3322 Setup 2 C = 330 pF nominal Take a capacitor with nominal 330pF Let us call it C2 Measure its capacitance C2 and its serial resistance RC2 with HM8118 CL2 is the total load capacitance in this setup RC2 = 5 mΩ C2 = 335 pF CL2 = CL1 + C2 = 147 pF + C2 = 482 pF (not measurable) Consequently we now expect to see a calculated oscillation with

02 21 LL C = 134e6 rads rarr f02 = 213 MHz T02 = 1f02 = 470 ns

Measured with the oscilloscope T02 = 469 ns f02 = 216 MHz ω02 = 136e6 rads Umax1 = 5175 V Umax2 = 3913 V ΔUmax = -1263 mV Spice simulation model Copy Spice model files Gr_R=50_L=10uH_C1=min to Gr_R=50_L=10uH_C2=330pF Set capacitance C of the Spice model to total load capacitor CL2 simulate and measure with cursors T02 = 480 ns f02 = 208 MHz ω02 = 130e6 rads Umax1 = 525 V Umax2 = 399 V ΔUmax = -126 V Are the tolerances acceptable yes Calculate approximated D for setup 2 termed D2

2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995

After all RC2 causes a zero at

122 2

1

2nC

fR C

= ltdifficult to measuregt


- 20 -

3323 Setup 3 C ge 100 μF nominal according to table 332 Take a capacitor with your nominal capacitance Let us call it C3 Measure its capacitance C3 and its serial resistance RC2 with HM8118 Plug C3 parallel to C2 CL3 is the total load capacitance in this setup (Keep C2 plugged as large capacitors behave poor at high frequencies) RC3 = 268 mΩ C3 = 882 μF CL3 = CL2 + C3 = 482 pF + C3 = 882 μF Consequently we now expect to see a calculated asymptotes intercept at

03 31 LL C = 313e3 rads rarr f03 = 498 MHz T03 = 1f03 = 201 μs

Calculate approximated D for setup 3 termed D3

3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702

The damping constant here is gtgt1 because of the wavegenrsquos high output impedance When power MOSFETs are used to generate Uin then Rg may be in the mΩ range yielding Dlt1 Calculate A0 for setup 3 termed A03

03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995

Compute poles from 212 03 3 3 1ps D D fp1 = 354 Hz fp2 = 698 KHz

After all RC a zero at 133 3

1

2nC

fR C

= 67KHz

Spice simulation model Copy Spice model Gr_R=50_L=10uH_C2=330pF to Gr_R=50_L=10uH_C3=xxx uF (use your group specific capacitor) Set capacitance C of the Spice model to total load capacitor CL3 simulate it in AC mode an measure poles fp1 fp2 at phase -45deg and -135deg resp To see fp2 in the Spice model we have to set RC=0 which eliminates zero fn1=1(2π RC C) Poles within Spice model fp1 = 356 Hz fp2 = 699 KHz Experimental Feed this circuit with a 500KHz PWM modulated signal oscillating between gnd=0V and VCC=33V Modify the pulse-width What is the relation between output voltage average Uout and duty cycle d = Ton (Ton+Toff) And what minimum and maximum average output voltages can be obtained with this setup

( )outU d = dmiddotVCC minoutU = 50 mV maxoutU = 3225 V


- 21 -

333 Characterize RLC Lowpass with Bode 100

Build again the circuit illustrated in Fig 31 and use C3 corresponding to your group number according to table 332 Use Bode100 Network Analyzer [B] to characterize your different RLC lowpasses [B] httpshpshs-regensburgdescm39115homepageeducationothersBODE100_QuickstartBODE100_Quickstarthtm 3331 Setup 1 C = minimal Characterize the setup without load capacitor ie with parasitic load capacitor only 3332 Setup 3 C = minimal Characterize the setup with Bode100 without load capacitor ie with parasitic load capacitor only 3333 Setup 2 C = 330 pF nominal Characterize the setup with Bode100 with load capacitor 330pF 3334 Setup 2 C = 330 pF nominal Characterize the setup without load capacitor ie with 330pF as load capacitor 3335 Setup 3 C ge 100 μF nominal according to table 332 Characterize the setup with Bode100 with load capacitor corresponding to your group number according to table 332 3336 Setup 3 C ge 100 μF nominal according to table 332 || 330pF Characterize the setup with Bode100 with load capacitor corresponding to your group number according to table 332 in parallel with the 330pF capacitor Large electrolyte capacitors are typicall y poor at high freuqencies Therefore we often find them in parallel with a small ceramic capacitor


- 22 -

34 Characterize the Output Impedance of our Digital Hardware Draw output header JP schematics of oyour FPGA board (See respective schematics file) Measure pull-down driver impedance Drive a logic 0 to an output pin as shown in Fig 512(a) Make sure with a voltmeter that there is no voltage between ground and the output pin (except some mV offset eg of the voltmeter) Then turn the meter to measure ohms For your board measure output impedance for the pins 1-10 of user header JP2 driven by signal gpio_1[0 TO 9] To do so either write gpio_1(0 TO 9) lt= (OTHERS=gt0)

or when gpio_1 is control by the switches due to gpio_1(9 DOWNTO 0) lt= sw(9 DOWNTO 0)

then pull switches 0-9 down Verify that there is 0V between the output pin 1 and gnd acc to Fig 341(a) Then turn the voltmeter ot measure ohms acc to Fig 341(b) Note the impeance turn the meter back to measure voltage To get a figure vor variance measure pins 1-10 and note the result in the lower row of table 341 Measure pull-up driver impedance Pull switches 0-9 up or drive gpio_1(0 TO 9) lt= (OTHERS=gt1) Verify that there is 0V between the output pin 1 and VCC3P3 acc to Fig 341(c) Then turn the voltmeter ot measure ohms acc to Fig 341(d) Note the resistance turn the meter back to measure voltage To get a figure vor variance measure pins 1-10 and note the result in the upper row of table 341 Table 341 JP2 pins 1-10 output impedance when driving high (Rout1) and low (Rout0)

Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553

Board-Pin output impedances Upper row DE1-SoC Lower row DE2

Fig 341 Measurement of pull-down and pull-up driver output impedances


- 23 -

4 VHDL Modeling 41 Organizing the Work

411 Building a Counter in a Flat Directory

Getting started with VHDL synthesis and download into an FPGA with a simple example

Fig 411 (a) Counter symbol (b) schematics (c) counter chain Navigate within Windows to directory Model_FilesVHDLlib_flat This path name which will be referred to hereinafter as ltpathnamegt In this directory we should have at least the files listed in Table 411 Table 411 Files that must be at least contained in the flat directory VHDLlib_flat

countervhd counter entity and architectures de1soc_countervhd counter model embedded in DE1-SoC board environment cfg_countervhd configuration of counter entity ndash architecture to be used cfg_de1soc_countervhd configuration of se1soc_counter entity ndash architecture tb_de1soc_countervhd testbench for de1soc_countervhd pk_vectorsvhd declarations eg type integer_vector for old VHDL vesions workdo ModelSim Tcl command file to control the simulator wavedo ModelSim Tcl file defining the wave (graphics) window ci_de1soc_countervhd Quartus II configuration interface for de1soc_countervhd DE2_pin_assigmentscsv Quartus II 8 assignments for DE2 board eg pins etc DE1_SoC_pin_assigmentscsv Quartus II 18 assignments for DE1-SoC board eg pins etc


- 24 -

4111 Simulation and Verification Using ModelSim Goal Getting started with VHDL simulation using a flat directory Navigate within Windows to directory Model_FilesVHDLlib_flat Copy the full path name which will be referred to hereinafter as ltpathnamegt TcL Control

ModelSim can be controlled by menu selections or by Tcl (Tool Command Language) control commands Menu commands will be echoed in the transfer window by the respective Tcl commands Lines beginning with in Tcl are comment lines Getting startet with ModelSim

Copy the pathname of your directory Start ModelSim simulator and navigate it into our actual directory ModelSim menu bar File gt Change Directoryhellip gt ltpathnamegt ModelSim Transcript window gt dir you should now see a listing of the files ModelSim menu bar Quit gt Yes Start ModelSim gt Menu bar gt Recent Directories gt hellipVHDLlib_flat Controlling ModelSim with Tcl Commands

ModelSim menu bar File gt New gt Libraryhellip Library name work Library physical name work gt OK Observe command echos in the Transcript indow vlib work vmap work Write into ModelSim Transcript window edit workdo file workdo opens You will now see the same commands vlib work vmap work as seen in the command echo Write into ModelSim Transcript window do workdo the do file workdo is processed Fig 4111 Explaining Tcl commands

comment

vlib work

vmap work work

vcom -work work countervhd

vcom -work work cfg_ountervhd

vcom -work work tb_countervhd

vsim workcfg_tb_counter

do wavedo

run 1 us

a in column 1 makes it a comment line

Create working library named work

Map logical name work to working lib work

Compile file countervhd to working lib work

Compile file cfg_countervhd to lib work

Compile file tb_countervhd to lib work

Simul config cfg_tb_counter located in work

Run file wavedo defining the wave-win

Simulate a time span of 1 μs

stands for ldquothis directoryrdquo

stands for ldquoparent directoryrdquo


- 25 -

4112 Synthesis and Download Using Quartus II First Steps and Synthesis with Quartus II

Goal Getting started with VHDL synthesis amp download into an FPGA using a flat directory Navigate within Windows o directory Model_FilesVHDLlib_flat Copy the full path name which will be referred to hereinafter as ltpathnamegt Start Quartus II 18 gt New Project Wizard gt Next gt Working directory ltpathnamegt (ending with lib_flat) Project Nmae ci_de1soc_counter Design file ci_de1soc_counter (must contain the top-level entity with same name) Next gt Empty project gt Next gt Design file ltpathnamegtci_de1soc_counter gt Next gt Familiy Cyclone V Device 5CSEMA5F31C6 gt Next gt Next gt Finish To assign signal to pins select Quartus II gt Assignments gt Pin Planner Close it again Use an ASCII editor (eg Notepad++) to look into file DE1_SoC_pin_assignmentscsv Then QII gt Assingments gt Import Assignments gt DE1_SoC_pin_assignmentscsv gt open gt OK Now letrsquos compile the design ldquoQuartus II gt Tools gt Compilerdquo will deliver an error message that files are missing Close Qurtus II Use an ASCII editor (eg Notepad++) to look into files ci_de1soc_counterqpf (Quartus project file) ci_de1soc_counterqsf (Quartus specification file) ci_de1soc_countervhd (VHDL source file) You may delete all other files in a directory With these three files you can rebuild th entire project Double-click on file ci_de1soc_counterqpf to start Quartus II Compile again To get rid of the error messages we have to add the missing files to the project Quartus II gt Project gt AddRemove File in Project gt (all vhd files) gt Open gt Apply gt OK Downlaod into DE1-SoC Board with Quartus II

Connect your DE1-SoC Board to an USB port of your computer Start the download tool Quartus II gt Tools gt Programmer (You can also click on the respective shortcut button) Next to Hardware Setup you must us see ldquoDE-SoC [USB-1]rdquo If not click on Hardware Setup and then on DE-SoC until you see ldquoCurrently selected hardware DE-SoC [USB-1]rdquo gt Close Now we have to set up the programmer In the Programmer window click on button Auto Detect gt 5CSEMA5 gt OK gt Yes In the Programmer window you will now see devices SOCVHPS and 5CSEMA5 as icons Click on 5CSEMA5 and delete it Then click Add File gt output files gt ci_de1soc_countersof gt open


- 26 -

Now you should see the device icons named SOCVHPS and 5CSEMA5F31 Click on line output_filesci_de1soc_countersof only check box ProgramConfigure must be activated Then click on Start button and watch your DE1-SoC board Diodes should darken Then the programmer begins to run Congratulations you got it In Quartus II gt project Navigato gt ci_de1soc_countergt de1soc_counteri_cnt (Label and entitiy namea are flipped) double-click on de1soc_conteri_cnt You should see the source code of this design unit now Read it Which keys are designed to act as global reset and enable Press the respective keys on the DE1-SoC board to verify the functionality and fil table 4112 below Table 4112 Keys ad their functionalities

Signal key( ) Functionality

reset global reset

eni global enable if not pressed

4113 Finishing Work within Flat Diectory and Conclusion Delete all unnecessary files from your flat directory There are only 2 new file to preserve qpf and qsf Preserving cdf memorizes the programmer settings Clicking on the qpf file should start Quartus II in the correct working directory Using the compile button will rebuild all the other files that we had deleted The directory is confusingly full although we have only built a simple counter More projects will cause more confusion and Quartus II refuses to place several project into one directory We have to build a structural directory such that we can clearly distinguish projects and that differnet projects an reuse testet building blocks such as the counter


- 27 -

412 Building a Structural Directory

Goal Learn tu use structural directory oranization

Fig 412 Structural directory o


- 28 -

In the structurakl directory within directory Model_FilesVHDLlib_struct we find the 3 subdirectories VHDL containing files that do not depent on a particular tool and are suitable for

reuse ModelSim containing files that are specific to the ModelSim tool or a particular project

using ModelSim Quartus II containing files that are specific to the Quartus II tool or a particular project

using ModelSim The VHDL subdirectory contains the three subdirectories beh whereas beh stands for ldquobehavioralrdquo claiming to contain non-synthezisable code It

contains the 2 sdubdirectories common containing common design units such as a counter de1soc containing design units that are particular to the DE1-SoC board

rtl whereas rtl stands for ldquoregister transfer levelrdquo claiming to contain synthezisable code It contains the 2 sdubdirectories common containing common design units such as a counter de1soc containing design units that are particular to the DE1-SoC board

std containing standard files typically declarations in packages indicated by prefix pk_ ModelSim subdirectory contains several subdirectories that contain VHDL testbenches and

do-files specific to particular test situations eg testing a counter QuartusII subdirectory contains several subdirectories that contain configuration interfaces

and project files specific to particular synthesis situations eg testing a counter


- 29 -

413 Building a Counter in a Structural Directory

Consider the files in the flat directory (listed in table 411) and think how to distribute them into the structural directory in Fig 412 Decide which file of Table 411 has to be placed in what directory of Fig 412 Then look into the structured directory to compare your results Note

Die you realize that configuration files cfg_countervhd and cfg_de1soc_countervhd are placed in several directories eg in VHDLrtlcommon and ModelSimtb_de1soc_counter and ModelSimtb_de1soc_counter In the common directory we will place the most common configuration to be used as default In directories ModelSimtb_de1soc_counter and QuartusIIci_de1soc_counter we may test very particular configurations It is up to the user which configuration file has to be compile for a particular project or test 4131 Simulation and Verification Using ModelSim Adapt file workdo for ModelSim from the flat directory structure such that command ldquodo workdordquo in the Transcript window works again an delivers the same results as in the flat directory While Windows separtes directories with backslash UnixLinux separate them with slash ModelSim uses UnixLinux directory notations with slash = this directory = parent directory rtl = up to parent directory and then down into directory rtl 4132 Synthesis and Download Using Quartus II Adapt file the Quartus II project such from the flat directory structure such that the complie command works again an delivers the same results as in the flat directory Exercise

Look into Quartus specification file (suffix qsf) How does Quartus II note directory trees in Windows or in UnixLinux manner Copy an example from QSF file


- 30 -

42 Designing a Finite State Machine with VHDL Goal Learn different aternatives to design finite state machines with VHDL Subdivide your design in combinational logic and memory holding the state The state latches the nextstate with the application of the active clock edge The nextstate logic must neither contain memory nor feedback loops within combinational logic 421 Designing Edge-Triggered Memory

Among the many possibilities of modeling sequential logic VHDL synthesizers are typically sensitive to the following constructs a) p_dffPROCESS(clkreset)

BEGIN IF reset=0 THEN qlt=0 [AFTER delay] ELSIF clkEVENT AND clk=1 THEN qlt=d [AFTER delay] END IF END PROCESS p_dff

b) p_state_memoryPROCESS(clkreset) BEGIN IF reset =0 THEN statelt=reset_state [AFTER delay] ELSIF clkEVENT AND clk=1 THEN statelt=next_state [AFTER delay] END IF END PROCESS p_state_memory

Listing 421 Modeling memory (a) for a scalar state and (b) for a state vector 422 Designing Combinational Logic

Modeling combinational is well done with concurrent statements Example for a 1-bit half adder sum lt= a xor b carry_out lt= a AND b In many situations designers use a PROCESS statement of the form p_combinationalPROCESS(sensitive_signals) BEGIN driven_output_signals lt= f(sensitive_signals other_signals) END PROCESS p_combinational The process generates (forbidden) latches if one of the following two basic rules for combinational logic is violated

1 All input signals of the process must be listed in its sensitivity list 2 All output signals must be driven all time

Violation example for rule 1 In the process below labeled p_partial_sensitivity_list the assignment ylt=b can be executed if and only if an event on signal a occurs To realize that a double-edge triggered FF using signal a as clock signal is required which is not combinational


- 31 -

p_partial_sensitivity_listPROCESS(a) BEGIN ylt=b -- latch generation b is not in the sesitivity list END PROCESS p_partial_sensitivity_list Violation example for rule 2 In the process below labeled p_wrong the assignment next_ylt=b can be executed if and only if a=1 When a=0 then next_y must not change To guarantee this the synthesizer generates a latch so that the code is no more purely combinational This problem is removed in process p_good Donrsquot forget that y has now to appear in the sensitivity list because it is an input signal a) p_wrongPROCESS(ab)

BEGIN IF a=1 THEN next_y lt= b -- what happens if a=0 END IF END PROCESS p_wrong

b) p_goodPROCESS(aby) BEGIN IF a=1 THEN next_y lt= b ELSE next_y lt= y END IF END PROCESS p_good


- 32 -

423 VHDL-Design of Synchronous Finite State Machines

4231 General Guidelines for Event-Driven FSM Design

Next State Logic

F(StimuliState)

StateMemoryNextState

Output Logic

G(StimuliState)

state

stimuli

state

clock

synchronous_reset asynchronous_reset

outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable

Fig 4231-1 Clocked state machine structure MealyMoore machine Moore outputs depend only on state and not on stimuli the latter may be asynchronous Signal enable depends on the implementation (can be avoided by not changing NextState)

Avoid Mealy outputs if possible Mealy outputs depend directly on input signals and are difficult to test because they are subject to change any time The delay of a chain of modules with mealy outputs is difficult to predict There are two possibilities to code the feedback-loop of a finite state machine

1 Using a single process for both next-state logic and memory 2 Using two processes one for the next-state logic and an other for the memory

Example counter We will now build the counter known from the Matlab model above

Fig 4231-2 The counter entity corresponds to the schematics symbol The prefix c denotes cPeriod as a constant (Constants are passed to a VHDL entity as generics)

counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut

A bitwidth cM can be declared directly using eg std_logic_vector(cM-1 DOWNTO 0) or INTEGER RANGE 0 TO 2cM or indirectly using eg INTEGER RANGE 0 TO 2cM In this case the bitwidth can be computed from the C-code cM=integer(ceil(log(countMax)log(2))) where the logarithms dualis can be computed from ld(x)=loga(x)loga(2) for any base a


- 33 -

4232 Entity and Architecture Create a directory lib_flat Within it Create an ASCII file countervhd and add entity counter and an architecture rtl_counter_fsm0 as shown in listing 4232 modeling a counter that counts in range count= 0cPeriod-1 Letrsquos add a very simple empty architecture to make the system compilable Listing 4232 File countervhd containing entity counter and empty architecture for it

LIBRARY ieee USE ieeestd_logic_1164ALL ENTITY counter IS GENERIC(cPeriodPOSITIVE=10) PORT(resetclockIN std_logic EnableInIN std_logic EnableOutBUFFER std_logic countBUFFER NATURAL RANGE 0 TO cPeriod-1 ) END ENTITY counter ARCHITECTURE rtl_counter_0 OF counter IS SIGNAL NextCountNATURAL RANGE 0 TO cPeriod-1 BEGIN -- do not count count lt= 0 EnableOut lt= 0 END ARCHITECTURE rtl_counter_0 4233 Configuration Create a configuration file combining entity counter with architecture rtl_counter_fsm2_up according to listing 4233 The statements LIBRARY WORK USE WORKALL are redundant because the VHDL compile adds them by default However they allow for easy change from WORK to an other library Listing 3233 File cfg_countervhd containing configuration cfg_counter

LIBRARY WORK USE WORKALL CONFIGURATION cfg_counter OF counter IS FOR rtl_counter_fsm2_up END FOR END CONFIGURATION cfg_counter


- 34 -

4234 Two PROCESS Statements for Next-State Logic and State Memory There are two design techniques to model the feedback-loop of a FSM Two PROCESS statements one for next-state logic and one for the memory or a single PROCESS statement for both We will investigate that in the next subsections Append architecture rtl_counter_fsm2_up to file countervhd Check for extrema eg cPeriod=1 Listing 3234 Architecture rtl_counter_fsm2_up appended to file countervhd

ARCHITECTURE rtl_counter_fsm2_up OF counter IS SIGNAL NextCountNATURAL RANGE 0 TO cPeriod-1 BEGIN -- Begin NextState Logic p_NextStatePROCESS(EnableIncount) BEGIN NextCountlt=count IF EnableIn=1 THEN IF count = cPeriod-1 THEN NextCountlt=0 ELSE NextCountlt=count+1 END IF END IF END PROCESS p_NextState -- End NextState Logic -- -- Begin State Memory p_StateMemoryPROCESS(resetclock) BEGIN IF reset=0 THEN count lt= 0 ELSIF clockEVENT AND clock=1 THEN count lt= NextCount END IF END PROCESS p_StateMemory -- -- output logic EnableOut lt= 1 WHEN (count=cPeriod-1 AND EnableIn=1) ELSE 0 END ARCHITECTURE rtl_counter_fsm2_up The above example reflects the state machine composed of next-state logic and memory When choosing this solution you should keep in mind the 2 rules for combinational logic

1 Have all input signals in the sensitivity list of the combinational-logic process and

2 Drive every output-bit of the next-state logic any time in any situation (Use ELSE and OTHERS keywords in IF and CASE statements respectively)

One method to guarantee 2 above is to begin the combinational next-state process with the following code line

State lt= NextState

Within a process the last of several signal assignments is valid So we have driven any bit of the state vector and may now drive some of its bits if desired


- 35 -

4235 One PROCESS Statement for Next-State Logic and State Memory Append architecture rtl_counter_fsm2_up to file countervhd Listing 3235 Architecture rtl_counter_fsm1_dn appended to file countervhd

ARCHITECTURE rtl_counter_fsm1_dn OF counter IS SIGNAL NextCountNATURAL RANGE 0 TO cPeriod-1 BEGIN -- Counter p_fsmPROCESS(resetclock) BEGIN IF reset=0 THEN count lt= 0 ELSIF clockEVENT AND clock=1 AND EnableIn=1 THEN IF count = 0 THEN -- Begin NextState Logic count lt= cPeriod-1 ELSE count lt= count-1 END IF -- End NextState Logic END IF END PROCESS p_fsm -- -- output logic EnableOut lt= 1 WHEN (count=0 AND EnableIn=1) ELSE 0 END ARCHITECTURE rtl_counter_fsm1_dn This realization uses the same memory model as the example above but replaces the next-state assignment countlt=NextCount by the combinational logic Advantages

There are no other signals in the sensitivity list than reset and clock There is no ELSE or OTHERS clause to define what happens when enable=0 Such code is often easier to read shorter and less error prone to maintain

To obtain the solution in example 2 from the solution in example 1 hellip

1 Replace the statement countlt=NextCount (or statelt=NextState) inside the memory by the next-state logic

2 Rename NextCount to count (or NextState to state) and remove the signal declaration statement for the NextCount (or NextState) vector

3 Remove the process for the NextState logic


- 36 -

4236 Design example of our flat and Structural Code

Listing 4236 VHDL model of a counter different architectures LIBRARY ieee USE ieeestd_logic_1164ALL ENTITY counter IS GENERIC(maxcntPOSITIVE=9) PORT(resetclockIN std_logic eniIN std_logic enoBUFFER std_logic countBUFFER NATURAL RANGE 0 TO maxcnt ) END ENTITY counter ARCHITECTURE rtl_counter_empty OF counter IS BEGIN END ARCHITECTURE rtl_counter_empty ARCHITECTURE rtl_counter_0 OF counter IS SIGNAL nextstateNATURAL RANGE 0 TO maxcnt BEGIN -- no Counter eno lt= 0 count lt= 5 END ARCHITECTURE rtl_counter_0 ARCHITECTURE rtl_counter_fsm1_dn OF counter IS SIGNAL statenextstateNATURAL RANGE 0 TO maxcnt BEGIN -- Counter p_fsmPROCESS(resetclock) BEGIN IF reset=0 THEN state lt= 0 ELSIF clockEVENT AND clock=1 AND eni=1 THEN IF state = 0 THEN -- Begin NextState Logic state lt= maxcnt ELSE state lt= state-1 END IF -- End NextState Logic END IF END PROCESS p_fsm -- -- output logic count lt= state -- Moore outputs eno lt= 1 WHEN (state=0 AND eni=1) ELSE 0 -- Mealy outputs END ARCHITECTURE rtl_counter_fsm1_dn ARCHITECTURE rtl_counter_fsm2_up OF counter IS SIGNAL statenextstateNATURAL RANGE 0 TO maxcnt BEGIN -- Begin NextState Logic p_NextStatePROCESS(enistate) BEGIN nextstatelt=state IF eni=1 THEN IF state = maxcnt THEN nextstatelt=0 ELSE nextstatelt=state+1 END IF END IF END PROCESS p_NextState -- End NextState Logic -- -- Begin State Memory p_StateMemoryPROCESS(resetclock) BEGIN IF reset=0 THEN state lt= 0 ELSIF clockEVENT AND clock=1 THEN state lt= nextstate END IF END PROCESS p_StateMemory -- -- output logic count lt= state -- Moore outputs eno lt= 1 WHEN (state=maxcnt AND eni=1) ELSE 0 -- Mealy outputs END ARCHITECTURE rtl_counter_fsm2_up


- 37 -

43 Building a Pulse-Width Modulator The PWM module acts as both power-DAC and enable generator for sampling frequency fs 431 Schematics Entity and Architecture

Understanding the schematics which is an extension of the counter

Fig 431 Pulse-Width Modulator (a) symbol (b) schematics Listing 431 VHDL model of pulse-width modulator architecture with single-process FSM LIBRARY ieee USE ieeestd_logic_1164ALL ENTITY pwm IS GENERIC(pwm_periodNATURAL=7) PORT(resetclockIN std_logic eni IN std_logic levelIN INTEGER pwmo BUFFER std_logic eno BUFFER std_logic countBUFFER NATURAL RANGE 0 TO pwm_period ) END ENTITY pwm ARCHITECTURE rtl_pwm_fsm1 OF pwm IS SIGNAL statenextstateNATURAL RANGE 0 TO pwm_period BEGIN -- pwm p_fsmPROCESS(resetclock) BEGIN IF reset=0 THEN state lt= 0 ELSIF clockEVENT AND clock=1 AND eni=1 THEN IF state = pwm_period-1 THEN -- Begin NextState Logic state lt= 0 ELSE state lt= state+1 END IF -- End NextState Logic END IF END PROCESS p_fsm -- -- output logic count lt= state -- Moore pwmo lt= 1 WHEN (stateltlevel AND eni=1) ELSE 0 -- Mealy eno lt= 1 WHEN (state=pwm_period-1 AND eni=1) ELSE 0 -- Mealy END ARCHITECTURE rtl_pwm_fsm1


- 38 -

432 Simulation and Verification

Goal Understanding the PWM by simulation Compile Model_FilesVHDLlib_structModelSimtb_de1soc_pwm with ModelSim change to its directory and start simulation with do workdo Check simulation results and conclude to draw signals pwmo and eno in the timing diagram of Fig 432 (Hint draw eno first)

Fig 431 PWM timing diagram for pwm_period=4 Exercise The code of listing 431 is found in file pwmvhd Verify it within testbench tb_pwm with ModelSim simulator Then delete the blue parts of the code and write them on your own again Train it using a both with 1 single process and with 2 processes for nextstate logic and state memory Solution

Fig 431 PWM timing diagram for pwm_period=4


- 39 -

433 Synthesis and Test

Goal Verification of the PWM by synthesis download into an FPGA and measurement Compile lib_structQuartusIIci_de1soc_pwm_Q18ci_de1soc_pwmvhd with Quartus II and download it into the DE1-SoC FPGA Does it work (use oscilloscope) If not make it work Check the code of hellipVHDLlib_structVHDLrtlde1socde1_soc_pwmvhd to figure out which keys have the meanings in the tables below Fill them For testing with an oscilloscope use the connections listed in table below Trigger flag eno as it comes reliable and reliable in the same position the last bits of the pwmo sequence It is recommended to drive a further pin (eg 1) with pwmo to drive the RLC lowpass and measure its mean output value What is this DACrsquos minimum voltage step Table 433 Hardware interface of pulse-width modulator

Signal Osci JP2 pin Functionality eno CH 1 Pin 2 Enable-out bit =1 during last bit in period pwmo CH 2 Pin 3 Pulse-width modulated output bit NOT pwmo CH 3 Pin 38 Inverted pulse-width modulated output bit ltRLC outputgt CH 4 Mean value of PWM signal Signal key( ) Functionality

reset global reset when pressed

eni global enable off when pressed

ltload current ongt switch load current on (when used for DCDC conversion)

ltadd LSB to levelgt Adds an LSB to signal level when pressed

Signal sw( ) Functionality

level Set level pwmo=1 when count_state lt level


LEN Low-side driver ON = synchronous mode

Signal PIN of J2 gpio_1( ) Functionality

pwmo Pulse-width modulated output bit

eno Enable-out bit =1 during last bit of PWM sequence

LEN Low-side driver ON = synchronous DCDC mode

ltcount_stategt Last 16 bit of the count state


- 40 -

44 LTI System Design Goal Building the control unit which is a digital filter and consequently a linear and time-invariant (LTI) system from its nature Time continuous LTI systems are modeled in Laplace variable s while time discrete systems are modeled in z where z = exp(sꞏTs) with sampling interval Ts = 1fs 441 Data Structures

Goal explain the notation of LTI systems as real vectors The representation of LTI systems of order R is accomplished as vectors typically named $TF_s and $TF_z representing $TF(s) and $TF(z) respectively whereas $ is a place holder for a code letter eg CTF_s and CTF_z for controller transfer functions (After translation to Matlab variables with data type sys are named TF$_s and TF$_z respectively) Time-continuous systems $TF_s have vector length is 2R+4 Time-continuous systems $TF_z have vector length from 2R+3 to 2R+4 whereas missing

trailing elements default to 0 with exception of c0 which defaults to 1 (a) Time-continuous system data object

Time-continuous System

0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s

Order R Contents of time- continuous LTI system object $TF(s) of order R Index 1 2 3 hellip R+3 R+4 hellip 2R+4 $TF_s() 0 R a0 hellip aR b0 hellip bR

Order 2 Contents of time-continuous LTI system object $TF(s) of order 2 Index 1 2 3 4 5 6 7 8 $TF_z() 0 2 a0 a 1 a2 b2 b1 b2

(b) Time-discrete system data object c0 hellip cR may be omitted and default to 1 0hellip0

Time-discrete System

10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z

Order R Contents of time-discrete LTI system object $TF(z) of order R index 1 2 3 hellip R+3 R+4 hellip 2R+4 content Ts R d0 hellip dR c0 hellip cR

Order 2 Contents of time-discrete LTI system object $TF(z) of order 2 index 1 2 3 4 5 6 7 8 content Ts 2 d0 d1 d2 c0 c1 c2

Table 441 Vector notations of LTI systems


- 41 -

442 Synthesis Example of a 2nd Order IIR Filter

(a) Schematics of digital 2nd order IIR filter in 1st canonical direct structure before translation to VHDL code

(b) RTL View after synthesis of VHDL code by Quartus II 81

(c) Timing information of the synthesizer delivers timing information such as tsu tco tpd

Clock clock has Internal fmax of 1116 MHz hellip (period= 89586 ns) tsu for register (x[18] clock) is -99523 ns tco from clock to destination pin y[29] is 90072 ns Longest tpd from pin x[18] to pin y[29] is 100009 ns (d) Timing information explanation

Fig 442 Synthesis of a 2nd order IIR filter with Quartus II [10]


- 42 -

Fig 442(a) illustrates a 2nd order IIR filter in 1st canonic direct structure It has an infinite impulse response (IIR) due to the feedback loops via c1 c2 and it is canonic as the order of the filterrsquos transfer function equals the number of memories Fig 442(b) illustrates the schematics synthesized Quartus II 81 for Cyclone II device EP2C35F672C6 [6] (Tools gt Netlist Viewers gt RTL Viewer) of the respective VHDL source code Exercise Identify the instantiated components of Fig 442(a) in Fig 442(b) Component Fig 442(a) Fig 442(b)

State memory for s1 iff1


Adder of d0 x + s1 ia0

Adder of d1 x + s2 ndash c1 y ia1

Adder of d2 x ndash c2 y ia2

Division by c0 id

Multiplication by c1 im3


Multiplication by d0 im0




- 43 -

Explain the timing information tsu tco and tpd in Fig 442(c) tsu hellip hellip stands for value in Fig 442(c) hellip meaning tco hellip hellip stands for value in Fig 442(c) hellip meaning tpd hellip hellip stands for value in Fig 442(c) hellip meaning tcp Critical path delay What is the critical path delay of an FSM design Computed tcp From Fig 442(c)


- 44 -

45 Modeling IIR Filter with VHDL Goal develop canonical IIR filter of 2nd and arbitrary order with intputoutput signals of both data types real and integer Simulate and synthesize them as far as possible Fig 45 2nd order filter simulation Clock reset enable Stimulus x y(filterf_canon1_order2) y(filterf_canon1) y(filteri_canon1_order2) y(filteri_canon1) ix iy

Exercise

You will find testbench tb_filtervhd and files wavedo and work_exercisedo in directory Model_FilesVHDLlib_structModelSimtb_filter_iir Open tb_filter_iirvhd with ModelSim change actual directory of ModelSim to the directory containing tb_filter_iirvhd and run it with Tcl file work_exercisedo

You should now see something like Fig 45 with no filter responses We will now complete the VHDL source codes to get Fig 45 at the end

The curves we see in Fig 45 are lttopgt (green) signals clock reset enable x (white) stimulus filter input jumping from 0 to 1 yfo2 (yellow) output response of filterf_canon1_order2 to x yf (orange) output response of filterf_canon1 to ix yio2 (green) output response of filteri_canon1 to ix after conversion to float yi (cyan) output response of filteri to ix after conversion to float ix (grey) stimulus x after AD conversion to integer before being fed to filteri iy (violet) output response of filteri to ix before DA conversion to float Hint Be aware that in VHDL real numbers must be written with a decimal point and with at least one digit before and behind it Consequently 1 is data type INTEGER 10 is REAL and notations like 1 and 1 are wrong


- 45 -

451 IIR Filter Float IO 1st Canonical Direct Structure 2nd Order

Goal Develop an IIR filter model of 2nd order with real type (floating point) IO signals Listing 451 Behavioral VHDL model of filterf_canon1_order2 USE workpk_stdALL USE workpk_vectorsALL LIBRARY ieee USE ieeestd_logic_1164ALL ENTITY filterf_canon1_order2 IS GENERIC(STF_zreal_vector) -- time-discrete LTI system PORT( reset IN std_logic -- reset low active clock IN std_logic -- sampling clock rising edge active enableIN std_logic -- enables sampling clock when 1 x IN REAL=00 -- input signal y BUFFER REAL=00) -- output signal END ENTITY filterf_canon1_order2 ARCHITECTURE rtl_filterf_canon1_order2 OF filterf_canon1_order2 IS CONSTANT RNATURAL=2 -- = INTEGER(STF_z(0)) CONSTANT dreal_vector(0 TO R)=STF_z(3 TO R+3) CONSTANT creal_vector(0 TO R)=STF_z(R+4 TO 2R+4) SIGNAL ns sreal_vector(1 TO 2)=(OTHERS=gt00) BEGIN ASSERT STF_z(1)=00 REPORT rtl_filterf_canon1_order2 Ts is not 0 SEVERITY ERROR ASSERT STF_z(2)=20 REPORT rtl_filterf_canon1_order2 is order 2 = STF_z(0) SEVERITY WARNING -- -- NextState logic --p_nextstatePROCESS(xy) --BEGIN ns(1) lt= d(1)x - c(1)y + s(2) ns(2) lt= d(2)x - c(2)y --END PROCESS p_nextstate -- -- State memory p_statememoryPROCESS(resetclock) BEGIN IF reset=0 THEN s lt=(OTHERS=gt00) ELSIF clockEVENT AND clock=1 AND enable=1 THEN s lt= ns END IF END PROCESS p_statememory -- -- output logic Mealy y lt= (d(0)x + s(1)) WHEN c(0)=10 ELSE (d(0)x + s(1))c(0) END ARCHITECTURE rtl_filterf_canon1_order2

Listing 451 shows a VHDL model of the 2nd order IIR filter in 1st canonical direct structure as illustrated in Fig 442(a) In the listing above IO signals x and y are declared as floating-point type REAL This is with most tools not synthesizable but we can simulate this model without need of AD and DA conversion As real number processing is rather for simulation than for synthesis we may save simulation time when avoiding division by c(0) for the typical case c(0)=1 In concurrent code we may use the WHEN statement Function f_filterf_canon1_order2 realizes an 2nd order filter in 1st canonical direct structure using floating point Inputoutput data with STF_z defining the time-discrete system transfer function Statement ASSERT STF_z(1)=00 REPORT rtl_filterf_canon1 Ts is not 0 SEVERITY ERROR


- 46 -

prints the report string if the condition Ts=0 is not fulfilled ie when the system STF_z it not time-discrete Statement CONSTANT RNATURAL= INTEGER(round(STF_z(2))) -- R = oRder writes the filter order to the constant R As function INTGER(hellip) truncates we use function round(hellip) to secure against possible round-noise on STF_z(2) Statement CONSTANT dreal_vector(0 TO R)=STF_z(3 TO R+3) CONSTANT creal_vector(0 TO R)=STF_z(R+4 TO 2R+4)

copies the respective parts of SFT_z to coefficients vectors d(0R) and c(0R) Exercise The code of listing 451 is found in file filterf_canon1_order2vhd Verify it within testbench tb_filter with ModelSim simulator Delete the blue parts of the code and write them on your own again Train it using concurrent statements and a process for the nextstate logic


- 47 -

452 IIR Filter Float IO 1st Canonical Direct Structure Any Order

Listing 452 Behavioral VHDL model of filterf_canon1 order is arbitrary ge 0 USE workpk_stdALL USE workpk_vectorsALL LIBRARY ieee USE ieeestd_logic_1164ALL ieeemath_realround ENTITY filterf_canon1 IS GENERIC(STF_zreal_vector) -- time-discrete LTI system PORT( reset IN std_logic -- reset low active clock IN std_logic -- sampling clock rising edge active enableIN std_logic -- enables sampling clock when 1 x IN REAL=00 -- input signal y BUFFER REAL=00) -- output signal END ENTITY filterf_canon1 ARCHITECTURE rtl_filterf_canon1 OF filterf_canon1 IS CONSTANT RNATURAL=INTEGER(round(STF_z(2))) -- R = oRder CONSTANT dreal_vector(0 TO R)=f_mult(STF_z(3 TO R+3)) CONSTANT creal_vector(0 TO R)=f_mult(STF_z(R+4 TO 2R+4)) SIGNAL sreal_vector(1 TO R)=(OTHERS=gt00) -- s(0) may be required for R=0 --SIGNAL s_dreal_vector(dRANGE)=d -- to make d visible in ModelSim debugger --SIGNAL s_creal_vector(cRANGE)=c -- to make c visible in ModelSim debugger BEGIN -- -- NextState logic and State memory in one Process p_fsmPROCESS(resetclock) BEGIN IF reset=0 THEN s lt=(OTHERS=gt00) ELSIF clockEVENT AND clock=1 AND enable=1 THEN l_nextstateFOR k IN sRANGE LOOP IF k lt R THEN s(k) lt= d(k)x - c(k)y + s(k+1) ELSE s(k) lt= d(k)x - c(k)y END IF END LOOP l_nextstate END IF END PROCESS p_fsm -- -- output logic Mealy g_r0IF R=0 GENERATE y lt= d(0)x WHEN c(0)=10 ELSE d(0)xc(0) END GENERATE g_r0 g_rxIF Rgt0 GENERATE y lt= d(0)x + s(1) WHEN c(0)=10 ELSE (d(0)x + s(1))c(0) END GENERATE g_rx END ARCHITECTURE rtl_filterf_canon1

Listing 452 shows a VHDL model of an arbitrary order IIR filter of 1st canonical direct structure whereas order R=2 is illustrated in Fig 442(a) In the listing above IO signals x and y are declared as floating-point type REAL This is with most tools not synthesizable A particular problem is order R=0 Most compiles accept the declaration statement sreal_vector(1 TO R) which translates to sreal_vector(1 TO 0) when R=0 However the output logic is different for R=0 and Rgt0 As this cases are controlled by a generic (R is constant) in concurrent code it must or should (dependent on the simulator or synthesizer) be made with the GENERATE statement Exercise The code of listing 452 is found in file filterf_canon1vhd Verify it within testbench tb_filter with ModelSim simulator Delete the blue parts of the code and write them on your own again Train it using 1 and 2 processes for nextstate logic and state memory


- 48 -

453 IIR Filter Integer IO 1st Canonical Direct Structure 2nd Order

Listing 453 Behavioral VHDL model of filterf_canon1 order is arbitrary ge 0 USE workpk_stdALL USE WORKpk_vectorsALL LIBRARY ieee USE ieeestd_logic_1164ALL ENTITY filteri_canon1_order2 IS GENERIC( STF_zreal_vector -- LTI system NoFractNATURAL=16) -- Number of fractional bits in coefficients PORT( reset IN std_logic -- reset low active clock IN std_logic -- sampling clock rising edge active enableIN std_logic -- enables sampling clock when 1 x IN INTEGER=0 -- input y BUFFER INTEGER=0) -- output END ENTITY filteri_canon1_order2 LIBRARY ieee USE ieeestd_logic_signed+ieeestd_logic_signed ARCHITECTURE rtl_filteri_canon1_order2 OF filteri_canon1_order2 IS CONSTANT RNATURAL=2 -- = INTEGER(STF_z(2)) CONSTANT dinteger_vector(0 TO R)=f_mult(STF_z( 3 TO R+3)20NoFract) CONSTANT cinteger_vector(0 TO R)=f_mult(STF_z(R+4 TO 2R+4)20NoFract) SIGNAL ns sinteger_vector(1 TO R)=(OTHERS=gt0) BEGIN ASSERT STF_z(2)=20 REPORT rtl_filteri_canon1_order2 is order 2 = STF_z(0) SEVERITY WARNING -- -- NextState logic --p_nextstatePROCESS(xys(2)) --BEGIN ns(1) lt= d(1)x - c(1)y + s(2) ns(2) lt= d(2)x - c(2)y --END PROCESS p_nextstate -- -- State memory p_statememoryPROCESS(resetclock) BEGIN IF reset=0 THEN s lt=(OTHERS=gt0) ELSIF clockEVENT AND clock=1 AND enable=1 THEN s lt= ns END IF END PROCESS p_statememory -- -- output logic Mealy y lt= d(0)x + s(1) WHEN c(0)=1 ELSE (d(0)x + s(1))c(0) END ARCHITECTURE rtl_filteri_canon1_order2

Listing 453 shows a VHDL model of 2nd order IIR filter of 1st canonical direct structure as illustrated in Fig 442(a) In the listing above IO signals x and y are declared as INTEGER types This is with most tools synthesizable The initialization of coefficient vectors d and c is realized with self-made function integer_vector = f_mult(real_vectorfactor) which multiplies the elements of the real_vector before rounding them to deliver the same-length integer_vector The reason will be detailed below Exercise The code of listing 453 is found in file filteri_canon1_order2vhd Verify it within testbench tb_filter with ModelSim simulator Delete the blue parts of the code and write them on your own again Train it using concurrent statements and a process for the nextstate logic


- 49 -


Goal Develop an IIR filter model of arbitrary order with integer type IO signals Listing 454 Behavioral VHDL model of filterf_canon1 order is arbitrary ge 0 USE workpk_stdALL USE workpk_vectorsALL LIBRARY ieee USE ieeestd_logic_1164ALL ieeemath_realround ENTITY filteri_canon1 IS GENERIC( STF_zreal_vector -- time-discrete LTI system NoFractNATURAL=16) -- Number of fractional bits in coefficients PORT( reset IN std_logic -- reset low active clock IN std_logic -- sampling clock rising edge active enableIN std_logic -- enables sampling clock when 1 x IN INTEGER=0 -- input y BUFFER INTEGER=0) -- output END ENTITY filteri_canon1 ARCHITECTURE rtl_filteri_canon1 OF filteri_canon1 IS CONSTANT RNATURAL=INTEGER(round(STF_z(2))) -- R = oRder CONSTANT dinteger_vector(0 TO R)=f_mult(STF_z(3 TO R+3)20NoFract) CONSTANT cinteger_vector(0 TO R)=f_mult(STF_z(R+4 TO 2R+4)20NoFract) SIGNAL sinteger_vector(1 TO R)=(OTHERS=gt0) -- s(0) may be required for R=0 --SIGNAL s_dinteger_vector(dRANGE)=d -- to make d visible in ModelSim debugger --SIGNAL s_cinteger_vector(cRANGE)=c -- to make c visible in ModelSim debugger BEGIN -- -- NextState logic and State memory in one Process p_fsmPROCESS(resetclock) BEGIN IF reset=0 THEN s lt=(OTHERS=gt0) ELSIF clockEVENT AND clock=1 AND enable=1 THEN l_nextstateFOR k IN sRANGE LOOP IF k lt R THEN s(k) lt= d(k)x - c(k)y + s(k+1) ELSE s(k) lt= d(k)x - c(k)y END IF END LOOP l_nextstate END IF END PROCESS p_fsm -- -- output logic Mealy g_r0IF R=0 GENERATE y lt= d(0)x WHEN c(0)=1 ELSE d(0)xc(0) END GENERATE g_r0 g_rxIF Rgt0 GENERATE y lt= d(0)x + s(1) WHEN c(0)=1 ELSE (d(0)x + s(1))c(0) END GENERATE g_rx END ARCHITECTURE rtl_filteri_canon1

Listing 454 shows a VHDL model of an arbitrary order IIR filter of 1st canonical direct structure whereas the case R=2 is illustrated in Fig 442(a) In the listing above IO signals x and y are declared as type INTEGER This is with most tools synthesizable Exercise The code of listing 454 is found in file filteri_canon1vhd Verify it within testbench tb_filter with ModelSim simulator Delete the blue parts of the code and write them on your own again Train it using 1 and 2 processes for nextstate logic and state memory


- 50 -

455 Synthesis of Data Types

Goal Test synthesis of the filters introduced above 4551 Synthesis of Signals with Data Type INTEGER Goal Here we will try to synthesize signals with data type INTEGER Navigate to directory Model_FilesVHDLlib_structQuartusIIci_de2_filter In this directory Create a project named ci_de2_filter with Quartus II 81 Assign Device Family Cyclone II

and Device EP2C35F672C6 and import the respective pin assignments for this device Add files ci_de2_filtervhd de1soc_filtervhd pk_stdvhd pk_vectorsvhd

filter_canon1vhd filter_canon1_order2vhd filteri_canon1_order2vhd filteri_canon1vhd

Compile the project What is the name of the chiprsquos IO connector in row AD column 23

What is the top-level-entityrsquos signal name connected to pad row AD col 23

Look into the synthesized schematics of design unit filteri_canon1 What is the

synthesized name of the multiplier for coefficient d2

Which devices realize the division by coefficient c0

4552 Synthesis of Signals with Data Type REAL (Floating Point)

Now we will try to synthesize signal with data type REAL (ie floating-point) Uncomment statement i_floatfilterf_canon1 GENERIC MAP(CTF_zCNoFract) PORT MAP(resetclock_50enablereal_xreal_y)

Compile it What is the compilerrsquos response

Comment this statement again (Isnrsquot it surprising that the synthesizer has no problem with REAL type signals real_x

real_y when statement ifloatfilter_canon1hellip is commented)


- 51 -

456 Synthesis of Transfer Function with Integral Coefficients

Goal Look deeper in the synthesis of IIR filter models with integral coefficients 4561 Theoretical Background

Goal Gain theoretical understanding for the tests below The evaluation of signal transfer function

1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z

is numerically realized as yn = 1

0c [d0ꞏxn + d1ꞏxn-1 + d2ꞏxn-2 - c1ꞏyn-1 - c2ꞏyn-2]

Using floating-point numbers we can avoid the division by c0 by setting c0=1 which is easily obtained by dividing the coefficients of both numerator and denominator by c0 Using integral numbers this method may cause significant round-off errors Consider transfer function

11

0 1

1( )

cSTF z

c c z

which corresponds to a time-continuous RC lowpass with time constant RC=Ts ln(-1c1) Example letrsquos set c1=025 so that we can represent this STF mathematically identical as

1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z

While coefficients of STF2(z) do not change after rounding to integer STF1(z) becomes after rounding STF1(z) = 1 (1-0ꞏz-1) = 1 which is an amplifier with amplification 1 or simply some wires The disadvantage of STF2(z) is that we need the required division by c0 This division facilitates to a simple bit-shift operation when c0=2N with N being an integral number We then say that coefficients are represented with N fractional bits as rounding a real number x to N fractional bits is computed as ix = round(xꞏ2N) ꞏ 2-N where we typically omit multiplication with 2-N and keep in memory that N bits are fractional This is the so-called Q Format

Format Qgf (1+g+f) bits first bit is sign bit f bits are assumed to be fractional Format UQgf (g+f) bits unsigned f bits are assumed to be fractional Most common are 32-bit integer numbers are typically processed in the Q formats

Format Q1516 32-bit vector first bit is sign bit 16 bits are assumed to be fractional Format UQ1616 32-bit vector unsigned integer 16 bits are assumed to be fractional


- 52 -

4562 Applications with ModelSim

Goal prove theoretical considerations with a simulator that allows us to see signal values This subsection illustrates the need to use coefficient c0 gtgt 1 for integral coefficients Open file Model_FilesVHDLlib_structModelSimtb_filtertb_filtervhd with ModelSim and look Which code line declares the number of fractional bits for coefficients Run testbench tb_filter with in ModelSim (Change Directoryhellip do workdo) Uncomment in file filterf_canon1vhd lines SIGNAL s_dreal_vector(dRANGE)=d -- make d visible in the ModelSim debugger SIGNAL s_creal_vector(cRANGE)=c -- make c visible in the ModelSim debugger to make the values of constants STF_s and STF_z visible in the ModelSim debugger (You can edit the respective files within ModelSim after first compilation) Run ModelSim with the lines above activated an look into the debugger (instances i_yf) for the following values real type of STF_z d(0) = d(1) = d(2) = c(0) = c(1) = c(2) = Uncomment in file filteri_canon1vhd lines SIGNAL s_dinteger_vector(dRANGE)=d -- make d visible in the ModelSim debugger SIGNAL s_cinteger_vector(cRANGE)=c -- make c visible in the ModelSim debugger to make the values of constants d(02) and c(02) visible in the ModelSim debugger Run ModelSim with the lines above activated an look into the debugger (instance i_fi) for the following integral values d(0) = d(1) = d(2) = c(0) = c(1) = c(2) = Comment the uncommented statements check again if the system runs well and close ModelSim


- 53 -

4563 Applications with Quartus II 81

This subsection is a study on how to choose optimal values for coefficient c0 Open file Model_FilesVHDLlib_structQuartusIIci_de2_filterci_de2_filtervhd with Quartus II 81 Which code line declares the number of fractional bits for coefficients Create a project or same name in directory ci_de2_filter using FPGA with family Cyclone II and device EP2C35F672C6 Compile the Project and check for the following parameters tsu = tco = tpd = fmax = Look into the RTL Viewer Which devices realize the division by c0 of instance i_integfilteri_canon1 Navigate to instance i_integfilteri_canon1 and modify the statements CONSTANT dinteger_vector(0 TO order)= f_mult(STF_z(1 TO order+1)20NoFract) CONSTANT cinteger_vector(0 TO R)= f_mult(STF_z(R+4 TO 2R+4)20NoFract)

to

CONSTANT dinteger_vector(0 TO order)= f_mult(STF_z(1 TO order+1)20NoFract-10) CONSTANT cinteger_vector(0 TO R)= f_mult(STF_z(R+4 TO 2R+4)20NoFract-10)

Compile the project again and check for the following parameters tsu = tco = tpd = fmax = Look into the RTL Viewer Which devices realize the division by c0 of instance i_integfilteri_canon1 Undo the modifications and explain why the modification -10 makes the filter much slower


- 54 -

46 Control Unit with PWM and ADA Conversion Goal Assemble PWM DAC and control unit to a DCDC buck converter

Fig 46 Model de1soc_control (a) symbol embedded in circuitry (b) schematics Fig 46 shows the design unit de1soc_control made to fit into DE1-SoC board In Fig part (a) illustrates how to embed de1soc_control in circuitry allowing for some DCDC buck conversion and Fig part (b) illustrates its inner schematics 461 Understanding the Role of the PWM Module

Check for chapter 42 for detailed understanding of the PWM module In de1soc the pwm_period is by default 256 so that the inner counter of the PMM module counts from count=0hellip255 and delivers enc=1 when count=255 and enc=0 otherwise When enc=1 the 50MHz clock signal named clock_50 triggers the state memory Consequently as Tclock_50MHz = 20ns the sampling clock interval has a duration of Ts = pwm_periodꞏTclock_50MHz = 20ns = 5120ns and the sampling clock speed is fs = 1 Ts asymp 195KHz asymp 200KHz Search the code of module de1soc_control for signals clock_50 pwm_period fclock_50MHz Tclock_50MHz Ts and fs


- 55 -


Open Model_FilesVHDLlib_structModelSimtb_de1soc_controltb_de1soc_controlvhd with ModelSim and change directory in ModelSim to this path Run the simulation typing do workdo in the transcript window Zoom the situation around enable flag enc at time 10520ns until you can see the numbers of signal count which is state and output of the PWM counter When the rising edge of clock_50 triggers count to change to pwm_period-1 = 255 then enc goes to 1 At the next rising edge of clock_50 signal count goes back to 0 and at the same time flag enc enables the clock entry of the controller (realized as filteri_canon1) Consequently its output changes too in this case from c=28 to 45 As now count lt c signal pwmo goes to 1 As signal assignments in our VHDL code were made without delays they default to zero Zero delays are realized in VHDL with simulation deltas (Δ) They are not visible in the wave window Consequently all these events seem to happen at a time when looking at the graphics Exercise In Fig 462 signal events are illustrated to happen with visible Δ delays Complete the timing diagram including reaction arrows Fig 462 Timing diagram with reaction arrows around enable-flag enc for pwm_period=256

Zoom the situation around 10μs v=0 w=80ꞏx The controller (filteri_canon1) is not enabled as enc=0 but its output changes from c=8 to 28 Explain that event on c although enc=0 Fig 462 Timing diagram with reaction arrows around enable-flag enc for pwm_period=256


- 56 -

463 Synthesis and Test Testing DA2 Daughter Boardrsquos IO Channels

Goal Make DACs and ADCs a monitoring and sense units respectively Navigate to directory Model_FilesVHDLlib_structQuartusIIci_de1soc_control_Q18 Where you will find file ci_de1soc_controlvhd Create a project named ci_de1soc_control in this directory with Quartus II 18 The project requires the following 8 files to be included ci_de1soc_controlvhd de1soc_controlvhd pk_stdvhd pk_vectorsvhd adcivhd pwmvhd filteri_canon1vhd and ndash in case you want to test it ndash filteri_canon1_order2vhd Top-level entity is ci_de1soc_control Compile the project an download it into the DE1-SoC board Does it work without errors (Should) 4631 Test of DAC1 of DA2 Daughter Board Plug DA2 daughter board on user header gpio_1 of DE1-SoC board Make sure the following settings of in top-level module ci_de1soc_control CONSTANT xREAL=-10 -- lt 0 w=conv_integer(sw())hellip CONSTANT ctrl_modeNATURAL=0 -- control mode 0 e=w 1 e=v others e=w-v CONSTANT pwm_periodPOSITIVE=28 -- pwm-length in clock cycles of clock_50MHz CONSTANT adc_selectNATURAL=0 -- =0 v=da2_adcdout32 (no other ADC installed) CONSTANT sync_modestd_logic=1 -- DCDC works in 0 async 1 sync mode

Get aware of the meaning of these settings Set-point voltage x lt 0 causes switches sw(80) to be interpreted as input Otherwise ie

if xge0 then w = round( x25633V ctrl-mode=0 causes e = w as filter input ctrl-mode=0 =1 e = v and ctrl-mode=2 e w - v pwm_period is the length of one pwm output (pwmo) sample in cylcles of clock_50MHz adc_select is irrelevant as we have no other ADC than the Flash-ADC of the DA2 board Sync_mode is irrelevant as we have no board with pull-up and pull-down power-FETs Compile and download this into your FPGA Verify with voltage measurements at Udac1out of DA2 board that switches sw(70) control Udac1out and sw(8) is ignored 4632 Test of Flash ADC and DAC2 DAC3 of DA2 Board To test the 9-level flash ADC of the DA2 daughter board we make its digital output visible with the two 9-level DACs named DAC2 and DAC3 This digital feed-through is accomplished within module de1soc_control by the code lines -- DA2 Daughter Board da2_adcdout9 lt= gpio_1(35 DOWNTO 28) -- read flash ADC output da2_dac2din9 lt= da2_adcdout9 -- drive flash ADC output to DAC2 da2_dac3din9 lt= da2_adcdout9 -- drive flash ADC output to DAC3 Use a voltmeter to set thresholds =0hellip7 on DA2 board to circa CPref = ( + frac12) 33V8 = 02062 06187 10313 14437 18562 22687 26812 30938 Connect CH1 of DSO-X 2024 oscilloscope to the wavegen output (Gen Out) Set wavegen to a triangular voltage with range 0hellip33V (Amplitude 33Vpp Offset 165V) After you verified this voltage on CH1 and DEx boards are power on connect the wavegenrsquos output also to DA2 baordrsquos flash-ADCrsquos input eg pin A31


- 57 -

Illustrate DAC2 and DAC3 output voltages on the oscilloscopersquos CH2 and CH3 respectively You should now see two 9-level staircase functions around the input signal on CH1 Disconnect the wavegen from DA2 board and CH1 of the oscilloscope From now on CH1 will display the output Udac1out the 256-level output voltage of DAC1 on the DA2 board 4633 Test of Further Setting and Monitoring Units Set-point adjustment

w = sw(70)+NOT(key(3)) WHEN x lt 0 else w = x25633V Further Monitoring Possibilities

Udac1out DAC1 is used as monitoring unit controlled by sw(98) according to Udacout = m33V256 sw(98) = ldquo00rdquo = 0 monitorin quantity is m = w sw(98) = ldquo01rdquo = 1 monitorin quantity is m = v sw(98) = ldquo10rdquo = 0 monitorin quantity is m = e + 128 whereas 128 VCC2= 165V sw(98) = ldquo11rdquo = 0 monitorin quantity is m = c ledr(90) As DAC1 with ist 256 input levels can only display the 8 least significant bits of m we also indicate m on the 10 red diodes If LEDR(8) or LEDR(9) are on there are more significants bits not monitored by Udac1out 7-segment displays There are six 7-seg displays + The left 3 of them show set-point w in deciVolts (1dV=10mV) + The right 3 digitis show the input of DAC1 and ledr(90) in dV Example Display 2 3 1 3 2 4 has to be interpreded as w=231V and m=324V whereas m depends on sw(98) as detailed above


- 58 -

464 Testing the Control Unit

Goal Check for proper operation of the control unit realized as time-discrete filter Connect CH1 of the DSO-X oscilloscope to the output of DAC1 of the DA2 board (pin A1) Be aware that VHDL real numbers need at least one digit before and after the decimal point 4641 Testing the Control Unit with Order R=0

Using order R=0 reduces the controllerrsquos transfer function to

0

0

( )d

CTF zc

Set CONSTANT xREAL=-10 -- lt 0 w=conv_integer(sw())hellip CONSTANT ctrl_modeNATURAL=0 -- control mode 0 e=w 1 e=v others e=w-v CONSTANT pwm_periodPOSITIVE=28 -- pwm-length in clock cycles of clock_50MHz CONSTANT adc_selectNATURAL=0 -- =0 v=da2_adcdout32 (no other ADC installed) CONSTANT sync_modestd_logic=1 -- DCDC works in 0 async 1 sync mode hellip CONSTANT CTF_zreal_vector(1 TO 4)=(Ts00 10 10) -- TF order=0 CONSTANT CNoFractNatural=16 -- No of Fractionals of controller coefs CTF_z = (TsRd0c0)=(Ts011) causes a controller transfer function in z domain (as

Tsne0) order R=0 amplification d0c0=11=1 CNoFract=16 causes controller coefficients realized with accuracy of 16 fractional bits Change dac1_mode to 1 has the effect that DAC1 monitors output signal c of the controller which is realized by filter_canon1 As its amplification is d0c0=11=1 there should not be any difference Verify that sw(8) is ignored Can you verify that Set sw(70)=11111111 Output voltage minimal or maximal Add an LSB by pressing key(3) Output voltage minimal or maximal Set CTF_z=(Ts0255256) Constant dac1_mode remains at dac1_mode=1 Filter transfer function is now the amplification d0c0=255256 Set sw(80)=100000000 Output voltage minimal or maximal Add an LSB by pressing key(3) Output voltage minimal or maximal


- 59 -

4642 Testing the Control Unit with Order R=1

Using order R=1 delivers the controllerrsquos transfer function as

10 1

10 1

( )d d z

CTF zc c z

Set CONSTANT CTF_zreal_vector(1 TO 6)=(Ts00 10 00 10 00) Now CTF_z=(TsRd0d1)=(Ts1 10 10) As dac1_mode=1 DAC1 monitors output signal c of the controller realized by filter_canon1 Its DC amplification is d0c0=11=1 DC amplification is the same as measured for same d0 c0 Can you verify that Connect Udac1out to CH1 (yellow) of DSO-X 2024 oscilloscope Set 1VDiv Check DC amplification Set CTF_z=(TsRd0d1)=(Ts1 1+c1 0 1 c1) with c1=-05 As dac1_mode=1 DAC1 monitors output signal c of the controller realized by filter_canon1 Its DC amplification is 1 Switch sw(8) should work due to round-off errors Can you verify that CTF_z corresponds to a time-continuous RC lowpass with time constant RC = Tsln(1b) What time constant do you expect To check this we observe Udac1out at CH1 of DSO-X 2024 1VDiv horizontal 5 microsDiv trigger level at 2V set sw(80)=000000000 Press reset=key(0) at the DE1-SoC board and ldquoSinglerdquo button of the oscilloscope Then push sw(8) from 0-gt1 An RC lowpass with 355 micros time constant should reach 2V (asymp63 of 33V) after some 355 micros How much delay do you ndash approximately ndash measure until reaching 2V This was too fast for our DAC1 Set pwm_period=212 Now Ts=4096Tclock_50MHz = 82 micros How much delay do you ndash approximately ndash measure until reaching 2V


- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z

Comment the actual statement defining CTF_z and use the 2nd order system CONSTANT pwm_periodPOSITIVE=212 hellip CONSTANT A0REAL=10 CONSTANT DREAL=025 CONSTANT f0REAL=10e3 CONSTANT w0REAL=20math_pif0 CONSTANT CTF_sreal_vector(1 TO 8)= (0020 A0w0w00000 w0w020Dw010) CONSTANT CTF_zreal_vector(1 TO 8)=f_c2d_bilin_order2(CTF_sTs) We how create a time-continuous 2nd order system CTF(s) = A0w0^2 (s^2 + 2Dw0s + w0^2) and translate it to CTF(z) by function f_c2d Hint for the following measurements you get best results when setting sw(7)=1 all other switches to 0 and then press and release reset=key(0) Test step response to sw(7) with f0=1 KHz for D=025 Test step response to sw(7) with f0=1 KHz for D=0 Can you verity the oscillation frequency of 1 KHz for D=0 Set pwm_period=28 Test step response to sw(7) with f0=10 KHz for D=0 Can you verity the oscillation frequency of 10 KHz Can you verity the oscillation frequency of 10KHz for D=0


- 61 -

47 Testing the PWM-DAC Goal Test PWM unit in interaction with the control unit yet without feedback This chapter proves Udac1out = Upwm_out when CTF(z)=1 and no load current is drawn from Upwm_out Which VHDL statements in the configuration interface module ci_de1soc_control obtain the following settings Udac1out controlled by sw(70) e lt= w pwm_period = 28 CTF(z)=1 CTF_z = (Ts011) Connect your self-made LC lowpass to the PWM output of your circuit Pin gpio_1(1) is covered by the DA2 board but you can connect it on the DA2 board at pin labeled PIN1 orand at gpio_0(1) CH1 Observe Udac1out with oscilloscopersquos CH1 (monitoring w v e c depending on sw(98)) CH2 Observe pwm_out with CH2 of the oscilloscope CH2 Observe Udac2out with CH3 of the oscilloscope monitoring v continuously CH4 Observe y (=LC lowpass output) with CH4 of the oscilloscope Operate switches sw(70) Does y follow Udac1out for most settings When do Uda1out and y differ severely Set pwm_period to pwm_period =210 Observe the reaction of y(sw(80)) Describe and explain the differences to the experiments with pwm_period =28 Reset pwm_period to pwm_period =28


- 62 -

48 Building a DCDC Buck Converter Goal Simulate build and understand a DCDC buck converter by closing the feedback loop 481 System Setup

(a) Schematics digital control DA and AD converter LCR lowpass

(b) Laboratory setup digital DE1-SoC board DA2 board with ADC and DACs LCR lowpass

Fig 481 DCDC buck converter (a) theoretical model and (b) practical setup


- 63 -

The setup to be simulated and synthesized is illustrated in Fig 481 Building blocks

Digital-to-digital converter (DDC) and controller are realized within the FPGA as mathematical functions

Digital-to-analog converter (DAC) is realized as pulse-with modulator Analog-to-digital converters (ADC) are realized with DA2 daugthter board plugged to

gpio_1 user header of the DE1-Soc board The RLC lowpass is realized with inductor L and capacitor C their unavoidable parasitic

resistors and a load resistor RL Signals

Signals x u y are assumed to be voltages typically in the range 0hellip33V x is the setpoint voltage (dt Sollwert) It is given as real number in the range 0hellip33 u is the output voltage of the DA converter (DAC) y is the output voltage (dt analoger Istwert) that should equal x as good as possible Signals w v e c are integral numbers where range 0hellip256 corresponds to 0hellip33V w is the digital setpoint (dt Sollwert) computed as w = round(x25633V) v is the AD converted output voltage or process variable (dt digitaler Istwert) e =w-v is the digital control deviation (dt Regelabweichung) fed to the controller c is the output of the controller (dt Stellgroumlszlige) We will now close the control loop by feeding back the output voltage y of the LC lowpass to the ADC in the feedback loop Hint Due to statement gpio_0 lt= gpio_1 within module de1soc_control signals of user header J2 (which driven by signal gpio_1) can be observed also at user header J1 (which is driven by signal gpio_0) Plug DA2 board to the DE1-SoC boardrsquos user header J2 gpio_1 Pins 1 and 3 of are labeled PIN01 and PIN03 on the DA2 board PIN01 is PWM output (pwmo) and PIN03 is the enable flag for the controller enc not required for this measurements Connect LC lowpass PWM output (pwmo PIN01) is input to inductor L whose other end is output y Its voltage is measured versus ground across capacitor C On the bread board ground can be delivered by the BNC cable connecting y with the oscilloscopersquos CH4 In case load resistors andor currents are applied they are connected parallel to capacitor C Connect Oscilloscope CH1 observes DA2 boardrsquos Udac1out with CH1 It is a monitor controlled by sw(98) CH2 observes pwmo with (PIN01 of J1 and J2) CH3 observes Udac2out or Udac3out CH3 monitores v the voltage measured by the ADC CH4 observe y (=LC lowpass output) and delivers its gound connection


- 64 -

Switches sw(70) Set-point adjustment

When generic x is xlt0 then set point w is selected with switches sw(70)+NOT(key(3)) wheres key(3) is low when pressed When xge0 w is computed from x Responsibe is the following statement within module de1soc_control w = sw(70)+NOT(key(3)) WHEN x lt 0 ELSE w = x25633 Switches sw(98) Monitoring with 256 level DAC1

Udac1out = mꞏ33 256 whereas m = w v e v when sw(98)=0 1 2 3 4 respectively DAC1 is used as monitoring unit controlled by sw(98) according to Udacout = m33V256 sw(98) = ldquo00rdquo = 0 monitoring quantity m = w sw(98) = ldquo01rdquo = 1 monitoring quantity m = v sw(98) = ldquo10rdquo = 0 monitoring quantity m = e + 128 whereas 128 VCC2= 165V sw(98) = ldquo11rdquo = 0 monitoring quantity m = c Keys key(0) global reset key(1) global enable key(2) load current on (when DCDC dauther board is connected) key(3) pressing key(3) adds 1 LSB to sw(70) LEDR(90) The 10 red LEDs are monitoring m like Udac1out however LEDR(90) have a rance of 10 bits ie 2 bits more than DAC1 Consequently output of DAC1 is meaningless when LEDR(9) or LEDR(9) are on 7-segment displays There are six 7-seg digitson the DE1-SoC board + The left 3 digits show set-point w in deciVolts (1dV=10mV) + The right 3 digitis show monitoring quantitiy m in dV (= input of DAC1 and LEDR) Getting Started Setup Validate settings in configuration interface ci_de1soc_control CONSTANT xREAL=-10 -- lt0 w=conv_integer(sw()) else wlt=x25633V CONSTANT ctrl_modeNATURAL=2 -- control mode 0 e=w 1 e=v others e=w-v CONSTANT pwm_periodPOSITIVE=28 -- pwm-length in clock cycles of clock_50MHz CONSTANT adc_selectNATURAL=0 -- =0 v=32adcdout of DA2 board (only ADC) CONSTANT sync_modestd_logic=1 -- DCDC board in 0 async 1 sync mode

Parameter ctrl_mode=2 causes the control unit to be fed with e=w-v where w is the set point and v is the process variable delivered by the ADC This is closing the feedback loop Be sure your flash ADC on the DA2 board works well Check its 8 threshold voltages labeled CPref(07) being adjusted to CPref(i)=(i+frac12)ꞏVCC8 = 02062 06187 10313 14437 18562 22687 26812 30938V respectively Be aware that the ADC outputs 9 levels in steps of 32 ie 0 32 64 96 128 160 192 224 256 Connect the output of your LC lowpass with the flash-ADC input eg pin A31 on DA2 board


- 65 -

482 First Simulation and Synthesis

Goal Get the DEDC buck converter system run Simulation Open a Windows10 window and navigate it to directory ModelSimtb_de1soc_DCDCbuck Open file tb_de1soc_DCDCbuckvhd with ModelSim and navigate ModelSim to the working directory ModelSimtb_de1soc_DCDCbuck Synthesis Open a Windows10 window and navigate it to directory QuartusIIci_de1soc_control He you should find files ~qpf ~qsf and ~vhd with ~ = ci_de1soc_control Click on ci_de1soc_controlqpf to open the respective project Use the PI controller setting CTF(s) = KP + KI s by CONSTANT KPREAL=10 CONSTANT fIREAL=100e3 CONSTANT KIREAL=20math_pifI CONSTANT CTF_sreal_vector(1 TO 6)=(0010 KI KP 00 10) -- -- translate s-gt z CONSTANT CTF_zreal_vector(CTF_sRANGE)= f_c2d(CTF_sTs) -- s-gtz

Simulate both top-level modules tb_de1soc_DCDCbuckvhd and ci_de1soc_DCDCbuckvhd with with ModelSim and Quartus II respectively You shuld get reasonable results in both cases In the simulation model process transfer function PTF models the impact of input voltage u on output voltage y and QTF models the impact of load current i on output voltage y As the LTI sysems are linear we can assume linear superposition as illustrated in Fig 482

Fig 482 Time-discrete DCDC buck converter model


- 66 -

483 Stability Issues

Goal Understand that feedback loops must be broken by latches 4831 Unlatched Feedback Path Goal Observe a feedback loop without latching Within the ADC interface module adci (instantiation i_adciadci) change the latched signal assignment to signal adci_out -- process latching input from Flash-ADC p_adciPROCESS(resetclock) BEGIN IF reset=0 THEN adci_dout lt= 0 ELSIF clockEVENT AND clock=1 AND enable=1 THEN IF adc_select=0 THEN adci_dout lt= f_sum(adci_din)ada_factor ELSE adci_dout lt= conv_integer(adci_din) END IF END IF END PROCESS p_adci

to the the unlatched signal assignment to signal adci_out -- process latching input from Flash-ADC -- p_adciPROCESS(resetclock) -- BEGIN -- IF reset=0 THEN -- adci_dout lt= 0 -- ELSIF clockEVENT AND clock=1 AND enable=1 THEN -- IF adc_select=0 THEN adci_dout lt= f_sum(adci_din)ada_factor -- ELSE -- adci_dout lt= conv_integer(adci_din) -- END IF -- END IF -- END PROCESS p_adci Simulate tb_de1soc_DCDCbuck with ModelSim again What happens Explain and illustrate it in Fig 482 Compile the System with QuartusII download it into the FPGA and run the circuit What happens (If circuit does not oscillate press rest or eneable butten or increase KP from 1rarr10)


- 67 -

4832 Latching unsettled signals Goal Understand that feedback loops must be broken by latching settled signals Within module de1soc_control (instantiation i_fpga de1soc_control) change i_adciadci GENERIC MAP(adc_selectada_factor) PORT MAP(resetclock_50encda2_adcdout9vadc_sclkadc_dinadc_csadc_dout)

To the always enabled case i_adciadci GENERIC MAP(adc_selectada_factor) PORT MAP(resetclock_501da2_adcdout9vadc_sclkadc_dinadc_csadc_dout)

Signals within the ADC are now latched with the 50 MHz clock rather than the sampling speed fs = 50MHz pwm_period Simulate tb_de1soc_DCDCbuck with ModelSim again What happens Compile the System with QuartusII download it into the FPGA and run the circuit What happens (If circuit does not oscillate press rest or enable butten or increase KP from 1rarr10)


- 68 -

484 Operation and Improvement of the Control Loop

Need to know Setting control transfer function CTF(s) and CTF(z) in the VHDL code Nice to know Optimization of PID control parameters KP KI KD Not SK students Please learn formula (48-3) olny Feedback loop heory for students of course SK only

Control loop amplification with forward network F feedback-network B and loop amplification FB = FB can be shown to feature the transfer function

1

FH

FB

(48-1)

In our case using controller transfer function CTF and RLC lowpass transfer function PTF forward network is

1F CTF ꞏPTF with DAC amplification Δ1 = 33V 256 = 1V 776

1B with ADC amplification γ1 = 256 33V = 776 V

so that with Δ1 ꞏ γ1 = 1

| |11 1

1 11 1CTF PTFCTF PTF

H CTF PTFCTF PTF CTF PTF

Consequently for CTFrarr infin w = 0hellip256 translates to y = 0hellip33V Due to x = Δ1ꞏw we get the total system transfer function

| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)

In a first step observing DC behavior only using 0 ( 0)STF STF f 0 ( 0)CTF CTF f

and 0 ( 0) 1PTF PTF f we get the system transfer function

0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -

4841 0th Order Kontroller CTF = KP

Goal Get a stable DCDC converter control loop work Open both tools Simulation Open a Windows10 window and navigate it to directory ModelSimtb_de1soc_DCDCbuck Open file tb_de1soc_DCDCbuckvhd with ModelSim and navigate ModelSim to the working directory ModelSimtb_de1soc_DCDCbuck Synthesis Open a Windows10 window and navigate it to directory QuartusIIci_de1soc_control He you should find files ~qpf ~qsf and ~vhd with ~ = ci_de1soc_control Click on ci_de1soc_controlqpf to open the respective project In a first step we simply use a constant as controlle transfer function CTF = KP Set this by CONSTANT KPREAL=10 CONSTANT CTF_sreal_vector(1 TO 4)=(Ts00 KP 10) -- CTF(z) order R=0 A0=KP -- -- translate s-gt z CONSTANT CTF_zreal_vector(CTF_sRANGE)= f_c2d(CTF_sTs) -- s-gtz

in both files tb_de1soc_DCDCbuckvhd with ModelSim and ci_de1soc_DCDCbuckvhd within Quartus II

0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)

At your DSO-X 2024 oscilloscope press button Meas gt Clear meas gt Clear all Source 1 gt DC-RMS F(ull) S(creen) gt Add Measurement Source 2 gt DC-RMS F(ull) S(creen) gt Add Measurement Source 3 gt DC-RMS F(ull) S(creen) gt Add Measurement Source 4 gt DC-RMS F(ull) S(creen) gt Add Measurement Press RunStop button eventually several times to get a figure of the mean signal values Start tests with setting controller transfer function to CTF(z) = KP = 1 In this case DC amplification of the loop is STF0 = CTF0 (1 + CTF0) = frac12 To test this set at CTF=1 by CTF_z=(Ts0 10 10) What DC output voltage y do we get Use switches sw(70) = 0100 1110 to set x = 100V = 100dV Set sw(98) = 00 so that Udac1out = x(w) = 100V Measure Udac1out (sw=rdquo00 0100 1110) =1V Order

R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -

4842 1st order CTF_s=(Ts1 KI KP 00 10) -- 0th Order Trafnsfer Functions CONSTANT KPREAL=10 -- CONSTANT CTF_sreal_vector(1 TO 4)=(Ts00 Kp 10) -- CTF(z) order R=0 -- -- 1st Order Trafnsfer Functions CONSTANT fIREAL=10000 CONSTANT KIREAL=20math_pifI CONSTANT CTF_sreal_vector(1 TO 6)=(0010 KI KP 00 10) -- -- translate s-gt z CONSTANT CTF_zreal_vector(CTF_sRANGE)= f_c2d(CTF_sTs) -- s-gtz

Check stability by pressing RunStop button several times Signal pwmo (CH2) shold show same bit-densitiy If it performs long series of 1rsquo and 0rsquos it is not stable -gt decrease KI=2πꞏfI Order

R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X

4843 2nd order CTF_s=(Ts2 KI KP KD 00 10 00) fD = fs 2 system has unstabilities particularly whe we obsever control signal c or output voltage y


- 2 -

Abstract A small project is solved as system design with mixed time-continuous and time-discrete circuitry The example is a digitally controlled DCDC buck converter

1 Introduction 11 Objectives The objective of this project for engineering students is to train system design using V-Model as process model Examples system is a DCDC buck converter

12 Project Tasks Intention is to model the system from top-level behavioral simulation eg with Spice behavioral models down to a bottom level detail view with VHDL Any group has to deliver a documentation Language is German or English The documentation has to be prepared in the typical publication format (title abstract

introduction main part summary references) The documentation has to cover the V-Model levels

+ specification requirements engineering + system top-level behavioral simulation (here Spice) + subsystem an algorithmic finite state machine model (here Matlab) + module (here VHDL) + implementation (hardware)

Any student must be able to handle the tools Cooperate with other group members but do not forget to handle the tools yourself too

13 Upside Down Process The experienced system designer is recommended to process V-Model top-town However when training students handling the tools for the first time learning success and understanding are better when the system is build bottom-up Or let us say when we ldquoscrumrdquo towards our goal introducing agile methods too


- 3 -






- 4 -



- 5 -






- 6 -










- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 3 -






- 4 -



- 5 -






- 6 -










- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 4 -



- 5 -






- 6 -










- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 5 -






- 6 -










- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 6 -










- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 7 -








- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 8 -





- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 9 -






- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 10 -



20 1 2

20 1 2

( )( )

( )p p pout

in p p p

a a s a sU sPTF s

U s b b s b s

2

0 1 2

20 1 2

( )( )

( )q q qout

L q q q

a a s a sU sQTF s

I s b b s b s











- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 11 -



1 20

1 2

(1 )(1 )( )

(1 )(1 )n n

p p

s s s sH s A

s s s s


0

( )L

out

in I

UPTF s

U

2

0 0 12 2

0 0

(1 )

2nA s

s D s


2 212 0 01 1ps D D D j D

0

( )in

out

L U

UQTF s

I

2(1 ) ( )D nR s PTF s

20 0 1 2

2 20 0

(1 )(1 )

2D n nR A s s

s D s


0

1

1 D L

AR G

0D LR G 1

1

1n

CR C

0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC

2 (1 )(1 )D C D C L

D

D L C L

R R R R G CD

LR G R G

0C D LR R G

2D CR R C

L

2 (1 )(1 )L

L

D L C L

G LD

CR G R G

0C D LR R G

2LG L

C


D CR R C

L

+

2LG L

C


- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 12 -



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 13 -




2 20 1 2 0 1 2

2 20 1 2 0 1 2

( ) ( ) ( ) p p p q q qin L in L

p p p q q q


c c z c z c c z c z



0xc = 2

0 1 22 2s sb b f b f 1xc = 2

0 22 2 2 sb b f 2xc = 2

0 1 22 2s sb b f b f





0 1 1 2 2 1 1 2 20


c


1 20 1 2

1 20 1 2

( )( )

( )

d d z d zY zTF z

H z c c z c z


- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 14 -




- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 15 -



From intL

outL out

RU U

R Z

using int

outout

Ua

U = 04818

we conclude 1 out

out Lout

aZ R

a

= 5065Ω



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 16 -


From inin G

in S

RU U

R R

using in 0

ininS

Ua

U = 05

we conclude 1

inin S

in

aZ R

a

= 1 MΩ


- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 17 -





Because 0

1 1

1D L

C L

R G

R G LC

0C D LR R G 1

LC



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 18 -


CL1 = 2 201

1 1

116 (2 385 )L H MHz

= 1473 pF



D CR R C

L

+

2LG L

C

2D CR R C

L


1 11 2

D C LR R CD

L

=

506 0 147

2 116

pF

F

= 009


01

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 19 -




2 22 2

D C LR R CD

L

=

506 005 482

2 116

pF

H

= 016


02

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995


122 2

1

2nC

fR C



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 20 -




3 33 2

D C LR R CD

L

=

506 0268 882

2 116

F

H

= 702


03

1

1 D L

AR G

= 1(1+506Ω100KΩ) = 09995



1

2nC

fR C

= 67KHz




- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X



- 21 -




- 22 -




Pin No 1 2 3 4 5 6 7 8 9 10 Rout1 Ω

564 759

634 756

620 760

575 760

619 754

580 760

620 752

617 754

616 751

610756

Rout0 Ω

667 553

660 551

666 554

667 554

662 550

655 556

661 549

660 551

661 548

659553




- 23 -







- 24 -





comment

vlib work

vmap work work





do wavedo

run 1 us













- 25 -





- 26 -



reset global reset




- 27 -





- 28 -











- 29 -






- 30 -










- 31 -





- 32 -



Next State Logic

F(StimuliState)


Output Logic

G(StimuliState)

state

stimuli

state

clock


outputsOutput Logic

H(State)

outputs

Moore

Mealy

Moore

State

stimuli

enable






counter

reset

clock

countcM

cPeriod

EnableIn

EnableOut



- 33 -





- 34 -






State lt= NextState



- 35 -









- 36 -




- 37 -





- 38 -






- 39 -


















- 40 -





0 1

0 1

( )( )

( )

RR

RR

a a s a sY sSTF s

X s b b s b s





10 1

10 1

( )( )

( )

RR

RR

d d z d zY zSTF z

X z c c z c z





- 41 -








- 42 -







Division by c0 id







- 43 -



- 44 -


Exercise





- 45 -





- 46 -




- 47 -





- 48 -





- 49 -





- 50 -
















- 51 -




1 20 1 2

1 20 1 2

( )d d z d z

STF zc c z c z




11

0 1

1( )

cSTF z

c c z


1 1

075( )

1 025STF z

z

== 2 1

3( )

4STF z

z





- 52 -




- 53 -



to




- 54 -





- 55 -





- 56 -






- 57 -





- 58 -




0

0

( )d

CTF zc




- 59 -



10 1

10 1

( )d d z

CTF zc c z



- 60 -


2 20 0 0 1 2

2 2 20 0 0 1 2

( )2

A a a s a sCTF s

D s s b b s b s

rarr

1 20 1 2

1 20 1 2

( )d d z d z

CTF zc c z c z



- 61 -



- 62 -






- 63 -








- 64 -






- 65 -






- 66 -





- 67 -





- 68 -




1

FH

FB

(48-1)





| |11 1




| | 11

CTF PTFy CTF PTFSTF

x CTF PTF

(48-2)



0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

(48-3)


- 69 -




0| |00

0 0

( 0 ) 11

CTF

f Hz

CTFySTF f Hz STF

x CTF

=12 (48-3)


R KP RL Ω x V w 00 v 01 e 10 c 11 y V

0 1 infin 100

0 1 100 100


- 70 -



R KP fI

∙Hz RL Ω x V w 00 v 01 e 10 c 11 y V

1 1 100 infin 100

1 1 100 100 100

1 1 10K infin 100

1 1 10K 100 100 X X X


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DC/DC Buck Converter - hps.hs-regensburg.de