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ABBOTTABAD Lab Assignment#10 Subject: Industrial Electronics Submitted By: Naveed Mazhar FA09-BEE-143 Submitted To: Sir Muhammad Sajjad Durani Date: 15 th November, 2012

decoder implementation with Ladder Logic

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Text of decoder implementation with Ladder Logic

ABBOTTABADLab Assignment#10

Subject:Industrial Electronics

Submitted By:Naveed Mazhar FA09-BEE-143

Submitted To:Sir Muhammad Sajjad Durani Date: 15th November, 2012

DECODERA decoder is a combinational circuit which converts binary information from n input lines to 2 unique output lines.

Truth Table:Logic table for 3 to 8 decoder is given by:

InputsX 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0

OutputsD3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1

GATE LEVEL IMPLEMINTATION (3 to 8 Decoder):The circuit diagram of 3 to 8 decoder is:

LADDER DIAGRAM:Ladder logic diagram of 3 to 8 decoder is given by: