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DEPFET, a vertex detector for the ILC

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DEPFET, a vertex detector for the ILC. DEPFET Principle Basic system Ladder proposal ILC demands Testbeam performance Device simulation Summary & Outlook. J.J. Velthuis for the DEPFET collaboration. Monolithic Active Pixel detector A p-FET transistor is integrated in every pixel. - PowerPoint PPT Presentation

Text of DEPFET, a vertex detector for the ILC

  • DEPFET,a vertex detector for the ILC

    DEPFET PrincipleBasic systemLadder proposalILC demandsTestbeam performanceDevice simulationSummary & OutlookJ.J. Velthuis for the DEPFET collaboration

  • DEPFET PrincipleMonolithic Active Pixel detectorA p-FET transistor is integrated in every pixel.By sidewards depletion potential minimum created below internal gate.Electrons, collected at internal gate, modulate transistor current

  • DEPFET PrincipleAdvantages:Fast signal collection due to fully depleted bulkLow noise due to small capacitance and amplification in pixelTransistor can be switched off by external gate charge collection is then still active !Non-destructive readout

    Disadvantages:Need to clear internal gate. Need steering chips.

  • Basic systemSelect and Clear signals provided by SWITCHER 64 x 2 outputsMax V = 25V

    Read out row-wise: CUROcurrent based read out128 channelsCDS real time hit finding & zero-suppressionrow rate up to 24 MHz

    DEPFET matrix parameters are being optimizedVarious pixel sizesVarious doping profiles

  • ILC requirementsTime structure: 1 train of 2820 crossings in ~1 ms every ~200msHit density: for r = 15 mm: ~ 100 tracks / mm2 / trainPlan to read out 20x during trainRow readout rate: > 20 MHz Turn off in between to save powerOccupany < 0.5 %Radiation length: ~0.1% X0 per layerthinned sensors (50 m) low power consumption -> no active coolingRadiation tolerance: 200 krad (for 5 years operation) Resolution: few m ( pixel size 25 x 25 m2)Impact parameter resolution a
  • Ladder proposalModules have active area ~13 x 100 mm2Read out on both sides.Detectors 50m thick, with 300m thick frame yields 0.11% X0SWITCHER & CURO chips connected by bump bondingSWITCHERCURO

  • ILC PowerChallenge: no active coolingMeasured Power Dissipation:Switcher: 6.3 mW per active channel at 50MHzCURO: 2.8 mW / channelAssumed Power Dissipation of DEPFET Sensor:0.5 mW per active pixelduty cycle: 1/200Only active pixel dissipate power1024 active pixels per module8 modules in Layer 1 => 8192 active pixelsExpected Power Dissipation in Layer 1Sensor: 8192 x 0.5 mW / 200 = 20 mWSwitcher: 16 x 6.3 mW / 200 = 0.5 mWCuro: 8192 x 2.8 mW / 200 = 114 mW For Layer 1 Sum: 135 mWFor 5 Layer DEPFET Vertex Detector: Total ~ 3.6 W no active cooling

    (note Bill [email protected] workshop Ringberg:Can remove up to 80W using gasflow)

  • ThinningThinning technology for active area established

    Currently with 150mm wafers at BSOI at TraciT, GrenobleChallenge: 50m thick detectors

  • Radiation hardnessChallenge: rad. hard up to 200 kradIrradiations with 60Co and X-rays (~17keV) up to ~1Mrad (SiO2) Threshold shift of the MOSFET (~4V) can be compensated by bias voltage shift

  • Zero suppressionCURO (readout chip) has a 0-suppression feature

    Have used it in August testbeam. Analysis in progress

    It works!!

  • TestbeamDESY test beam with 6 GeV e- Bonn ATLAS telescope system:double sided strip detectorspitch 50 m (no intermediate strips)readout rate 4.5 kHz (telescope only)DUT: 450m thick DEPFET with CCG and HERow rate 2.5 MHz (no 0-suppression)

  • Pedestal & NoisePedestal calculated as average signal after hit removalNoise is of signal distribution after pedestal & common mode subtraction & hit removalSome pixels are blocked because they are:Very noisyStrange pedestalHot

  • ClusteringLook for hits:pixel with largest signal && >5Add neighbors with signal 2 in maximum area

    Clusters mostly confined to 3x3S/N=112.00.3


  • Position resolutionUsing CoG:X=8.70.1m Y=7.00.1mUsing :X=8.10.1m Y=7.10.1m pixel size=36x22m Note in Y worse than CoGRemaining crosstalk in Y direction. Still under study.Numbers still include uncertainty in predicted position (6 GeV particles)

  • Multiple ScatteringFrom GEANT simulation, found (2int+2MS)=6.94m

    Uncertainty not well known, but point is 5m. High energy testbeam ended Sept 3rd; analysis in progress

  • EfficiencyLook for clusters in ROI of predicted position 2 pixelsEfficiency @ 5=99.75%Some hits at wrong location due to multiple scattering ?Applying very modest 2-cutEfficiency @ 5=99.96%

  • PurityGood cluster has a residual in both X and Y better than 30mBad clusters are number of clusters found in the background. Still, using seed cut 7 purity & efficieny 100%Note: MPV seed around 60

  • New devices2 Large chips in next productionFinal ILC 512x4096

    Large area device512 x 512 matrixPixel size: 32x24marray size: 16.38x12.29 mm Chip size: 21x18mm

    Long ladder size128 x 2048 matrixpixel size: 24 x 24 marray size: 3.07 x 49.15 mm chip size: 8.5 x 56 mm

  • Performance of a DEPFET vertex detector at ILCHuge study simulating physics events using DEPFET vertex detectorHere results with 450m thick detector and 230e- noise:

    Correspondence is excellent!!

  • SimulationDEPFET implemented in MOKKA (GEANT4-ILC package) Digitization in Marlin:Landau fluctuationsCharge transport, sharing & diffusionLorentz shift ([email protected])Electronic noise (100 e- for ILC, 230e- TB comparison)IP resolution very good! (demands: a
  • SummaryDEPFET good candidate for ILC vertex detector. Project is in full swing. Meets already demands onRadiation length (0.11 X0)Radiation hardness (Vth [email protected])Power consumption (
  • OutlookCurrently analysing high energy testbeam data:Detailed charge collection studyQuantatively test zero suppressionPrecise resolution measurementBuild large matrices (currently in production)Also still developing in parallel different types of DEPFETsFurther development of the readout chips ongoingNew SWITCHER chips are submitted. Expected early December (0.35m CMOS)New CUROs are being designedImplement transimpedence amplifierImplement ADCImplement neighbor logic for 0-suppressionGOAL:Produce full scale prototypeladder by 2010

  • Position resolution CoGCentre-of-Gravity assumes linear charge sharing

    X=8.70.1m Y=7.00.1m pixel size=36x22m

    Numbers still include uncertainty on predicted position

  • algorithmWriting CoG for 2 strips

    Linear charge sharing flat, but in real life is not. Reconstruct position:

  • Readout speedStill need to improve the readout speed

  • ClearingCURO measures: Isig,i+Iped,i & Iped,i+1Need to remove all charge such that Iped,i+1=Iped,iCOMPLETE CLEAR @ Vclear=18V! Far too high for radiation hard technologyClear completeAll charge removed

  • HighE vs non-HighEHighE extra n-type implantMoves internal gate deeper into bulkClearing takes places deeper in the bulkLower signals, but easier clearingclearInternal gatechannelOptional HighE implant

  • ClearingCURO measures: Isig,i+Iped,i & Iped,i+1Need to remove all charge such that Iped,i+1=Iped,iCOMPLETE CLEAR possible for HighE with low voltages (~7V) possible to make radhard SWITCHER in standard CMOSHighE

  • DEPFET for Near DetectorDEPFET advantages:Fully active thickness of 450 mTracking inside device Event rate no problem (~5 Hz pro plane)Pixel size ok (IP 60m)

    Challenges:18 planes of 0.5x0.5 m2Need larger matrices ?Mechanics (but no low mass requirement)

  • Comparison with ILC

  • Author listUniv. of Bonn: M.Karagounis, R.Kohrs, H.Krger, M. Mathes, L.Reuen, C.Sandow, E.von Trne, M.Trimpl, J.Velthuis, N.Wermes

    Univ. of Mannheim: P.Fischer, F.Giesen, I.Peric

    Politecnico di Milano:M. Porro

    MPI Halbleiterlabor Munich:O Hlker, S. Herrmann, L.Andricek, G.Lutz, H.G. Moser, R.H.Richter, M.Schnecke, L.Strder, J.Treis, P.Lechner, S. Wlfel

    THCA of Tsinghua Univ.:C. Zhang, S.N. Zhang

  • DEPMOS TechnologyDEPMOS pixel array cuts through one cellAlong the channelPerpendicular to the channel Metal 2

    Metal 1

    Oxyd Poly 2 Metal 2 Metal 1 Poly 2 Clear Gclear ChannnelpDeep nn+Deep pPoly 1Double poly / double aluminum process on high ohmic n- substrate

    Low leakage current level: < 200pA/cm (fully depleted 450m)

  • ReadoutReadout current based: SWITCHERs turn on a row using an external GateCURO measures Signal+Pedestal currentSignal charge removedCURO measures Pedestal currentCDS in CURO chip

  • Excellent noiseSingle pixel device 10 s shapingRoom temperature (22 C)

  • Excellent noiseLarge structure (64x64):75 x 75 m2 pixel size 45 m gate circumference / 5 m gate lengthDrain in center of pixelCut gate geometryCurved edgeDouble metal

    Operated at:Pixel current 30 ALine processing time 25 s

  • WIMSWide-band Imaging and Multi-band Spectrometer (WIMS) is part of Chinas spacelab mission .Observe high-energy bursts, transients and fast-varying sources over a broad spectral range simultaneously

    Using Macro pixelsPixel size 0.5x0.5 mm2Si-drift chamber readout using DEPFET

  • Switcher und CUROSteuer-ASIC SWITCHER II: 0.8m AMS HV Technologie Maximaler Spannungshub: 25 V Leistungsaufnahme: 1mW/Kanal @ 30MHz 2x64 Kanle mit internem Sequenzer 20V !Switching 20V @ 30MHzAuslese-ASIC CURO II: 0.25m CMOS Technologie 128 Kanal Stromauslesechip Pedestalstrom-Korrektur (CDS) Trefferidentifikation und Null-Unterdrckung Trefferzwischenspeicher Leistungsaufnahme: 2.5mW/Kanal @ 20MHz Rauschen 431 nA




    DU = 20V n = 30 MHz





    currentbuffer A

    current buffer B

    (Iped + Isig) or Iped