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KEK High Energy Accelerat Research Organizatio Development of a Data Acquisition System for the Belle II Silicon Vertex Detector Katsuro Nakamura (KEK) T. Bergauer B , G. Casarosa F , M. Friedl B , K. Hara, T. Higuchi A , C. Irmler B , R. Itoh, T. Konno G , Z. Liu E , M. Nakao, Z. Natkaniec C , W. Ostrowicz C , E. Paoloni F , M. Schnell D , S.Y. Suzuki, R. Thalmeier B , T. Tsuboyama, S. Yamada, H. Yin B Silicon-Strip Vertex Detector ( for Belle II experi 6/ 6/2014 1 TIPP2014, Amsterdam

Development of a Data Acquisition System for the Belle II Silicon Vertex Detector

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Development of a Data Acquisition System for the Belle II Silicon Vertex Detector. Katsuro Nakamura (KEK) T. Bergauer B , G. Casarosa F , M. Friedl B , K. Hara, T. Higuchi A , C. Irmler B , R. Itoh , T. Konno G , Z. Liu E , - PowerPoint PPT Presentation

Text of Development of a Data Acquisition System for the Belle II Silicon Vertex Detector

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Developmentof a Data Acquisition Systemfor the Belle II Silicon Vertex Detector Katsuro Nakamura (KEK)T. BergauerB, G. CasarosaF, M. FriedlB, K. Hara,T. HiguchiA, C. IrmlerB, R. Itoh, T. KonnoG, Z. LiuE,M. Nakao, Z. NatkaniecC, W. OstrowiczC, E. PaoloniF,M. SchnellD, S.Y. Suzuki, R. ThalmeierB, T. Tsuboyama,S. Yamada, H. YinBKEKKavli IPMU (WPI)AHEPHYBIFJC Univ. of BonnD IHEPE, INFN PisaF, Tokyo Metropolitan UnivG.TIPP2014 (June 6, 2014) Silicon-Strip Vertex Detector (SVD)for Belle II experiment6/ 6/20141TIPP2014, AmsterdamKEKHigh Energy AcceleratorResearch OrganizationKEK (High Energy Accelerator Research Organization)

Belle II Experiment andSilicon-Strip Vertex Detector4-layer DSSD sensorsmeasure 2D track position for charged particlesmore than 220,000 readout stripsSVD provides RoI (region of interest) in the inner 2-layer Silicon-Pixel Vertex Detector (PXD)PXD data reduction and accurate track reconstruction

charged particleSilicon-Strip Vertex Detector (SVD)Belle II detectorSuperKEKB @ KEK6/ 6/20142

DSSDTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)2APV25 and Requirement on TriggersAPV25 chipFront-end electronics for DSSD signal readoutProvides 128-channels analog signals sampled among several clock ticksShaping time: 50 nsecSuitable for high occupancy in Belle II SVD 6- and 3-samples/trigger modes will be used for Belle II SVD6-samples/trigger is preferable for good peak findingRequirements on triggers from APV25Maximum trigger rate: (140 clocks/sample)38kHz (6-samples), 76kHz (3-samples)cf. max. trigger rate in Belle II is 30kHzMinimum trigger interval: (3 clocks/3-samples)189nsec (6-samples), 94nsec (3-samples)Maximum trigger latency:5.0 usec (available pipe-line size of 160 samples)

6/ 6/20143APV25 chip

clock tick (32MHz)ADCoutput from APV25(6 samples/trigger)1 samplea particle hitdiscussed laterTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)control signalsSVD Readout System OverviewPerformance of the readout system has to be confirmed with prototypes before final production.FADC x48FTB x48flash ADCzero-sup.data formatdataformatB2LAurora

basf2Belle II DAQHSLBDAQPXD systemPXD RoIdata flowbelle2linkAurora linkBelle II SVDBuffer x4FADC-CtrlB2TT decoderAPV Trig. Gen.coppercablesFADC controlVMEbackplaneclock,trigger,reset clock,trigger,reset belle2ttbelle2tt1748APV25s~2mcoppercablesJunctionboxes( signalrepeater )~10mcoppercables6/ 6/2014TIPP2014, Amsterdam4

clock,trigger,reset SVD readout system

APV25 chipscalculateRoI on-lineBelle IItrigger/timingcontrollerSVD readout system isdriven by 32MHz clock.KEK (High Energy Accelerator Research Organization)

Development of Prototype FADC BoardHigh signal densityreadout 48 APV25 outputsAPV25 signal processing on FADCanalog level conversion (AC coupling)10-bit ADCFPGA (Stratix IV) data processingFIR filterCommon-Mode CorrectionZero-Suppressiondata transmission to FTB

6/ 6/20145prototype FADC boardsignals from 48 x APV25FTB boardVME 9UTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Development of Prototype FADC Board6/ 6/20146

Zero-Suppression functionOnly transmits hits above thresholdThreshold is recoded in the FPGA memoryTwo steps of CMC (Common-Mode Correction) before zero-suppressioncalculates average of ADC shifts from pedestalsSuccessfully prepared hardware and firmware for the FADC prototype.(6-samples/trigger)TIPP2014, Amsterdam

CMC distribution (n-side)

hit information from APV25 chipaverage of ADC shifts from pedestal Common-Mode CorrectionADC distribution before CMC

ADC distribution after CMCtypical MIP:70 ADCtypical MIP:70 ADC[ADC]ADCClock Ticks (32MHz)obtained fromraw ADC dataobtained fromraw ADC dataafter CMCKEK (High Energy Accelerator Research Organization)Development of Prototype FTBFinesse Transmitter Board (FTB)FTB main feature: high speed serial communication with other systemsline to DAQ 2.5 Gbpsline to PXD : 1.3 GbpsStability test for the serial lineswith 3.175 Gbps PRBS-7No errors were observed during an 8-day long bench test with a 2-FTB system. This result corresponds to 11 days of correct SVD data transmission with a 48-FTB system in 95% C.L.assuming 1kB event size from an FADC board and 30 kHz trigger rate.

FTBFTBconnect SFP ports each other76/ 6/2014

SFP portSFP portFPGA Xilinx SPARTAN-6SC signalreceiverSFP portJTAG portdata from FADCDAQPXDStability test for serial lines with PRBS-7prototype FTB boardVME 3UTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)7control signalsOther Componentsin SVD Readout SystemPrototypes of all other remaining components have been developed as well.An integrated SVD readout test was performed with the full system.FADC x48FTB x48flash ADCzero-sup.data formatdataformatB2LAurora

basf2Belle II DAQHSLBDAQPXD systemPXD RoIdata flowbelle2linkAurora linkBelle II SVDBuffer x4FADC-CtrlB2TT decoderAPV Trig. Gen.coppercablesFADC controlVMEbackplaneFTSWclock,trigger,reset clock,trigger,reset belle2ttbelle2tt1748APV25s~2mcoppercablesJunctionboxes( signalrepeater )~10mcoppercables6/ 6/2014TIPP2014, Amsterdam8

clock,trigger,reset SVD readout system

APV25 chipsreduction ofPXD data sizetrigger/timingdistributer

KEK (High Energy Accelerator Research Organization)

SVD Readout Test at DESY Beam Line6/ 6/20149

Superconductingsolenoid magnet

APV25 chips4-layer test SVD modulesDSSD sensorin light-shielding box(max. 1T)test SVD modulesTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)SVD Readout System at Beam Test6/ 6/2014TIPP2014, Amsterdam10

Belle II DAQ setup

PXD-DatCon system

FADC boardJTAG server

FTB boardsame readout chain as Belle II experimentfirst test of the full readout chaintrigger rate: ~ 400 Hzconfirmation of correct data processingevent number checkCRC checksumStable operation of the readout during the beam test (about 3 weeks)

SVD readout systemKEK (High Energy Accelerator Research Organization)Analysis Results from Beam Test Data6/ 6/201411

event displayw/ magnetic fieldSVD modulesreconstructedtrackcluster hit efficiency for tracksTIPP2014, Amsterdamobserved performance of SVD moduleFrom the resulting high efficiency, we confirmed our CMC and zero-suppression do not lose SVD hit efficiency.

cluster charge distribution

cluster size distribution

position of track projection [cm]cluster hit efficiency for tracksefficiency: 99.4%efficiencyKEK (High Energy Accelerator Research Organization)

APV25 Trigger-FIFO and APV25-FIFO EmulatorData transmission in 6-samples mode takes 26.5 usec/trigger and one in 3-samples mode takes 13.2 usec/trigger.The transmission dead time is absorbed by trigger-FIFO in APV25. Available trigger-FIFO depth in APV25 is 32 samples. FIFO overflow has to be avoided.APV25-FIFO emulator calculates the trigger-FIFO occupancy, and asserts a trigger veto in order to stop trigger and avoid FIFO overflow.The APV25-FIFO emulator is to be implemented in future. Trigger dead time from this veto system has to be considered.12Implement APV25-FIFO emulator 6/ 6/2014TIPP2014, Amsterdam

APV25 chipsBelle II SVDBelle II trigger/timing controller module:global decision of Level-1 trigger accepttrigger signalsto all sub-systemsAPV25 trigger-FIFO32 samplesFIFOoccupancyAPV25-FIFO emulator32 samplesemulatedFIFOoccupancythreshold for trigger vetoglobaltriggerdecisionvetoemulatedKEK (High Energy Accelerator Research Organization)13

threshold: 26 samplesno trigger/busy propagationtrigger interval: 190nsec (24 clocks)Trigger dead time vs. Raw trigger rate (Simulation)Belle II designedmax. trigger rateonly 6-samplesonly 3-samplesSimulated Trigger Dead Timefrom APV25-FIFO Emulator6/ 6/2014TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Schedulefor Readout System DevelopmentFADC boardJul. 2014: prototype ver.2fix minor bugs on PCBimplementation of APV25-FIFO emulatorNov. 2014: prototype ver.3 (if necessary)start production from the beginning of 2015

FTB boardHardware/firmware are already developed well.production from the end of 2014

Full readout system will be built up in 2015 toward the start of Belle II experiment in 2016.6/ 6/201414ScheduleTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Summary and OutlookThe SVD readout system are being developed toward the start of Belle II at 2016.Prototypes for FADC, FTB, and all other components were prepared.Common-Mode Correction + Zero-Suppressionstability test for high speed serial link with 3.175Gbps PRBS-7Successful SVD readout test at DESY beam line was performed.full readout chain test at the first timeStable operation was confirmed by checking event numbers and CRC check-sums.Excellent performance of the SVD module was observed.Expected trigger dead time at 30 kHz trigger rate is 3% (acceptable).By increasing 3-samples trigger fraction, we can decrease the dead time.We confirmed that the SVD readout system provides excellent performance for the Belle II experiment.

We will apply minor modifications on FADC board and start the mass production at the beginning of 2015.6/ 6/201415TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Thank you!6/ 6/201416TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)DAQ limitations from APV25Trigger rate1 sample data transmission to FADC takes 140 clock cycles.3-sample mode Maximum trigger rate is 76kHz6-sample mode Maximum trigger rate is 38kHzcf. The target trigger rate in Belle II is 30kHz.6-sample mode works fine in low luminosity, but combination of 3- and 6-samples have to be used in higher luminosity.Minimum trigger interval1 trigger reception needs 3 clock cycles for 3-sample mode and 6 clock cycles for 6-sample mode.3-sample mode Minimum trigger interval is ~94 nsec.6-sample mode Minimum trigger interval is ~190 nsec.CDC also requires 200 nsec separation.Maximum trigger latencyMaximum available pipeline depth is 160 clock cycles.That requires trigger latency of less than 5 usec.APV25 has FIFO with 32-samples depthTo avoid FIFO overflow, a finite trigger-dead-time has to be introduced.6/ 6/201417TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Junction box

Supply HV and LV to DSSD and APV25.DC/DC converterJoint signals between APV25 and FADC board.

6/ 6/201418

2 prototypes for p- and n-sidesDC/DC convertersTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)FADC data output formatModes of operation:Raw moderaw ADC data for a defined lengthTransparent modeAPV25 frame detection with header data and raw data of all stripsZero-suppressed modePedestal subtraction, CMC, only hits above threshold (3 or 6 samples)Zero-suppressed/hit time finding mode (not implemented yet)Peak sample and peak time, all 3 or 6 samples only for unclear cases (such as double peak = pileup)

Raw + transparent are typically used SVD-internally (timing adjustments, pedestal/noise evaluation, calibration, )Zero-suppressed (+hit time finding) are the normal data formats for physics data acquisition

6/ 6/201419TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)selectorFADC datastream diagramAll the three data-modes are working well.6/ 6/201420ADC data decoderAPV frame detectiondata reorderingRAW datapipeline

512cellsCMC 1CMC 2Hit finder & encoderzero suppresseddataencodertransparentdataencoderrawmodedataData Transmitter for FTBADC dataofAPV outputFIFOx 48 APVsTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)

FADC status monitoringError status of FADC is important to guarantee the data correctness.The most probable error sources in firmware:

6/ 6/201421APV FIFO full32sample depthFIFO full2k word depthADC framedetection errorAPV headerdetection errorTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Data format for zero-suppressionError-bits for the quality confirmation and diagnoses.22

new format for the beam test (from Jan. 21, 2014)old format6/ 6/2014TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)FTB data formatThe current data format works well.A few improvements will be applied in future.Confusing magic numbers in header and trailer will be changed.Currently, they are same as the magic numbers in B2L header and trailer.Trailing 0 in the MSB 8-bits to distinguish all types of frames.Leave all the FADC data as they are.23

Current formatNext format6/ 6/2014TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)FADC-Controller and Buffer boardsWe will have 4 crates with FADC modulesOne has single FADC-ControllerReceives FTSW signalsDistributes clock, trigger and other controls to all BufferEach crate has single Buffer moduleReceives FADC-Controller signalsDistributes signals to FADCs through backplane bus

1st prototype of FADC-Controller boardBuffer boardFTSW4 Buffer boardFPGASTRATIX IVFPGACYCLON IIbuffersGbE interfaceFADC-Controller boardAll FADC boards in a cratebuffers6/ 6/201424TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Pedestal and gain calibration6/ 6/201425

particle signal

calibration signalTuxDAQhit mapAPV25 output

TuxOATuxDAQ + TuxOAC++ applicationLinux 32/64 bitUsed at DESY beam testTuxDAQSVD standalone DAQSamples data on FADC data-streamnoise datagain calibration dataas well as physics dataConfigures parameters in FADC systemADC clock delay scanTuxOASimple analyses of sampled FADC dataNoise and pedestalgain calibration constantsHit profile (chip / module level)Worked well at DESY

TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)SVD Run/Slow ControlPXD and IBBelle will employ EPICS, and SVD shares CO2 cooling system and environmental monitors with PXD SVD will be involved in the EPICS control system.Common data logging on EPICS databaseEPICS integration on our software needs to be done.6/ 6/201426Integration plan of SVD run/slow control

SVD run control GUISVD HV/LV control GUI

TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)SVD rack location at IR6/ 6/201427

SVD FWDSVD BWDTIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Manpower for developmentM. Friedl (HEPHY): System & schematics design, supervisionS. Schmid (HEPHY): CAD schematics & PCB layoutJ. Pirker (HEPHY): Parts purchasing, assembly (soldering)M. Eichberger (HEPHY): Assembly (soldering, wire bonding)C. Irmler (HEPHY): Assembly (wire bonding), software supervision, Origami/hybrid testingR. Thalmeier (HEPHY): FADC hardware and firmwareH. Yin (HEPHY): Online softwareW. Ostrowicz (Cracow): FTB hardware and firmwareZ. Natkaniec (Cracow): FTB hardware and firmwareM. Schnell (Bonn): FTB DatCon interface firmwareK. Nakamura (KEK): Firmware, B2Link/B2TT, System integration at KEK6/ 6/201428TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Comparison with simulation6/ 6/201429

20%dead timeTrigger dead time from the FTSW pipeline busy is simulated.Simulation with LFSR (linear feedback shift register) pattern generator, which is really used in FTSW, well describes the measured live ratios. There is no other big dead time sources in our system.Green curve shows expected live ratio with Poisson distribution triggers (real triggers)Dead time is expected to be about 20% at 30kHz. Too large for the Belle II operation. APV25 emulator would be necessary for our busy handling.TIPP2014, AmsterdamKEK (High Energy Accelerator Research Organization)Residual distribution(CMC16, tight cut)30

p-siden-sideNO. NAME VALUE ERROR SIZE DERIVATIVE 1 p0 3.23921e+03 1.94809e+01 2.08186e-05 -5.55985e-03 2 p1 1.32647e-04 3.78820e-05 2.73072e-07 -3.97456e-01 3 p2 7.97590e-03 4.79511e-05 1.34153e-05 7.85978e-03 4 p3 2.60344e+02 1.42551e+01 4.32121e-05 7.62981e-03 5 p4 2.23610e-04 2.20931e-04 1.59234e-06 -4.49666e-01 6 p5 2.04253e-02 3.89271e-04 2.40944e-05 1.84963e-02NO. NAME VALUE ERROR SIZE DERIVATIVE 1 p0 3.63112e+03 1.91311e+01 4.04379e-05 2.35151e-02 2 p1 1.63427e-03 6.42714e-05 8.53023e-07 -1.94406e+00 3 p2 1.45968e-02 7.25321e-05 2.10705e-05 1.11957e-01 4 p3 1.64809e+02 1.00714e+01 7.75674e-05 1.72498e-02 5 p4 3.53879e-04 5.49890e-04 7.27532e-06 -2.24539e-01 6 p5 4.14886e-02 9.68568e-04 5.59383e-05 1.09194e-02KEK (High Energy Accelerator Research Organization)Intrinsic efficiency for cluster finding in L3(CMC16, tight cut)31

red: # of extrapolationsblue: # of associated clusters after previous cut (|x|