Development of an Enhanced ADS® Electrothermal

MOS-AK/GSA Workshop 2010

Simulation Tool for RF CircuitsSalvatore Russo, Vincenzo d’Alessandro, Niccolò Rin aldi

Department of Biomedical, Electronics and Telecommu nications EngineeringUniversity of Naples Federico II, via Claudio 21, 8 1025 Naples, Italy

Outline

� Introduction to electrothermal effects� Relevance of ET effects in RF device/circuits� ADS based simulation software

� Thermal modeling� Approaches to thermal modeling� Approaches to thermal modeling� Thermal models for ET simulation

� Electrothermal simulation� Software structure� Simulation examples

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Thermal issues: reliability• Tmax boundary: caused by failure mechanisms activated at high temperatures

(increased leakage currents, oxide breakdown, electromigration, metal contactdegradation, increased stresses due to differing coefficient of thermal expansionamong materials…). Determines SOA limitation at high power levels, which shrinks inthe downscaling process due to RTH increase in small area devices

• 2nd breakdown boundary: related to self-heating and/or impact ionization. Occurs atlower power levels and shrinks with device downscaling due to increased RTH,reduced breakdown voltage, reduced ballasting effect of parasitic resistancesreduced breakdown voltage, reduced ballasting effect of parasitic resistances

• 1st breakdown boundary: decreases with device downscaling due to vertical dopingoptimization

3

Log(IC)

VCE

HBTDC

SOA

Imax

Tmax

2nd breakdown (electro-thermaland/or avalanche instability)

1st breakdown (avalanche)

Thermal issues in GaAs-based PA’s� In GaAs-based HBT’s used in wireless applications thermal issues are even more

critical due to the combination of the poor GaAs thermal conductivity (about one thirdof that of Si) and high current densities usually handled

� Poor thermal design may cause long term reliability problems, hot spot formation,thermal runaway, current hogging effects eventually leading to performancedegradation (current gain collapse [Liu, T-ED 1993, 1994, 1995, 1996])

� Thermal memory effects also degrade linearity performance

4

T. Nozu, 21st IEEE SEMI-THERM Symposium, 2005

Thermal Issues: Device Isolation� Isolation schemes have evolved over time (STI-DTI/SOI/Silicon-On-Glass) in the

attempt to reduce parasitics, improve noise immunity, reduce leakage currents, etc� Electrical insulating materials also provide an (unwanted) thermal isolation

SOG, Nanver T-ED 2003CEB

5

C

Material K [W/mK]

Si 148

Si (10 nm) 13

Si0.7Ge0.3 8

SiO2 1.4

DTI

box

DTI

box

SOI

Thermal Issues: Device Isolation� Isolation schemes have evolved over time (STI-DTI/SOI/Silicon-On-Glass) in the

attempt to reduce parasitics, improve noise immunity, reduce leakage currents, etc� Electrical insulating materials also provide an (unwanted) thermal isolation

CEB SOG, Nanver T-ED 2003

6

DTI

box

DTI

box

SOI

RTH-trenchSOI ~ 5900 K/W

C

Material K [W/mK]

Si 148

Si (10 nm) 13

Si0.7Ge0.3 8

SiO2 1.4

Electrothermal AnalysisPROBLEM:In solid state devices the current (and hence the dissipated power) is a function of devicetemperature, which, in turn, is determined by the dissipated power. Therefore thedetermination of device current and temperature represents a coupled problem.

oTo solve the circuit equations the device temperature must be known [Ii=f(Ti)]oTo calculate the temperature the power dissipated by the devices should be known[Ti=f(Pi)].

SOLUTION:Develop circuit simulation tools where the electrical and thermal problems are solvedDevelop circuit simulation tools where the electrical and thermal problems are solvedsimultaneously.

7

Electrical analysis:

solve the circuit equations

Thermal analysis:

calculate the temperature of each device

P

T

Electrothermal simulation approaches

� Direct Approach:o Direct coupling between electrical and thermal solverso Solution of the heat diffusion equation at each iteration point (huge computational

effort)

Circuit simulation FEM Thermal solverP

T

� Reduced Thermal Models Approach:o Use reduced thermal models (e.g., RTH matrix or equivalent thermal networks).

Parameters can be extracted in advance through measurements, numericalsimulations, or analytical models.

8

Circuit simulation Compact Thermal ModelsP

T

T

Electrothermal Analysis: Limitations of present circuit simulation tools/models

Commercial circuit simulators (PSPICE) without thermal models:• The temperature is a constant parameter and does not change during thesimulation process.

Most simulators (like ADS® and Spectre) include advanced electrothermal models fordevices; if enabled, the electrothermal feedback can be accounted for through a simplesingle-pole equivalent network; however:

•Only self-heating effect is included, that is, thermal coupling between devices is nottaken into account. However, this might lead to markedly inaccurate results when thetaken into account. However, this might lead to markedly inaccurate results when thetemperature of a transistor is affected by other (close enough) devices•Thermal parameters (RTH, CTH) have to be set manually in the thermal circuit•Single-pole thermal circuits have insufficient accuracy when describing transientevolution.

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T1,P1

T2,P2 T3,P3

TB

P TRTH CTH

Electrothermal Analysis: ADS®

Layout

Thermal model

Thermal modelparameters

Routine for generating a thermal model imports all required

information from the layout.

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T1 T2

P1 P2

ADS® (circuit simulation)

Schematic

ADS® device models in which the temperature changes during the simulation process.

The thermal compact model is automatically linked to the circuit.

Self-heating & coupling effects.DC,AC, transient analysis.

Transient analysis can be done with selected accuracy.

Thermal modelingThermal Resistance Matrix

T1,P1T2,P2 T3,P3

� The temperature of each device is due to the power dissipated by thedevice itself (self-heating) and to the power due to the neighboringdevices (thermal coupling).

� This leads to the thermal resistance matrix

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T2

P2

R22

P3 R23

P1 R21

Ths

+

+

T3

P3

R33

P2 R32

P1 R31

+

+

T1

P1

R11

P3 R13

P2 R12

+

+

12 2 13 3

21 1 2

11 1

22 2

33

1

2

3

3 3

31 1 3 32 2

hs

hs

hs

R PR P

R P

R P R PR P R P

T

R

TTT R P

TT P

− = + +− = + +− = + +

⋅ ⋅⋅ ⋅ ⋅⋅ ⋅⋅

⋅

Structure of the Electrothermal tool (1)

Circuit

simulation

Thermal

analysis

P

T

[RTH/ZTH]

FEM/analytical

experimental

The RTH/ZTH matrix can be obtained from:a) Measurementsb) FEM thermal simulationsc) Analytical thermal models (easier to implement automatically, however the circuit

layout must be known)

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Structure of the Electrothermal tool (2)After RTH/ZTH matrix calculation (or measurement), we need to generate the thermalnetworks which calculates the temperature in each device and link it to the originalschematic -> “Electrothermal schematic” with electrothermal effects automaticallyembedded.

Layout

Rth Calculation routine (analytical models)

RTH /ZTH matrix for different technologies are automatically evaluated

from layout

ExperimentalRTH /ZTH matrix can be also provided externally

when evaluated from measurements or FEM

FEM

13

T1 T2

P1 P2

ADS® (circuit simulation including ET feedback block)

E-T schematic

(analytical models)

+R11

Ths

T1

P2R12

P2

R22

T2

P1R21

+ +P1

FEM

Structure of the Electrothermal tool (3)

P RTH CTH

TTh1

Th2

Th3

Pd1

Pd2

Pd3

ET feedback

In order to connect the devices of theschematic to the proper nodes of thethermal network, the device model ismodified by deactivating the default thermalnetwork, and adding a node where thedissipated power is accessible

14

T

P P

T

ET feedback

block

P RTH CTH

TB

IBB

VCC

Th1 Th2 Th3 Th4 Th5

Q1 Q2 Q3 Q4 Q5

Th3

Th4

Th5

Pd3

Pd4

Pd5

feedback block

Pd1 Pd2 Pd3 Pd4 Pd5

(a 5-finger example)

Structure of the Electrothermal tool (4)

Verilog-A SDD Equivalent network

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ET feedback block can be implemented by:• Equivalent network• Verilog-A: text file describing the ET-FB accepted

& compiled by simulators supporting Verilog-A.• SDD (Symbolically Defined Device): multiport

components where current on one port is definedas e.g., voltage on another port; possible directderivative calculation

SDD2PSDD3P1I[2,0]=_v1*R1

RR1R=50 Ohm

SDD_1_TH_SDD_TH1R1_1=1000

th1pd1

Verilog-A SDD Equivalent network

Structure of the Electrothermal tool (5)

The electrothermal simulation tool also includes a post-processing routine. After the ETsimulation is completed the routine imports the I-V ADS data, and plots the temperaturemap on the chip surface for a chosen bias condition (i.e., a simulation point)

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map on the chip surface for a chosen bias condition (i.e., a simulation point)

ET software user interface (UI):an example (1)

� User is guided with a simplifieduser interface step-by-step.

� Interface has been written inMatlab but it is portable to anyother programming language.

� User can choose to use a

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� User can choose to use aconfiguration file defined before orto proceed with “wizard”.

� This example simulates a step-by-step pre-processing task for a 3-finger case starting from layout.

ET software user interface (UI):an example (2)

� Thermal matrix is evaluated and a new schematic containing ET feedback block DC

DCV_DCSRC1Vdc=VCE V

VARVAR1VCE=1.0

EqnVar

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schematic containing ET feedback block is generated.

� After ADS simulation, data can beprovided to post-processor to evaluatetemperature maps.

AgilentHBT_ModelHBTM1

Pd3Pd2

Pd1

Th3Th2

Th1

SDD_3_TH_SDD_TH3

R3_3=343.9147

R3_2=52.2062 R3_1=25.9762 R2_3=52.2062R2_2=343.9147

R2_1=52.2062 R1_3=25.9762 R1_2=52.2062 R1_1=343.9147

th1

th2

th3

pd1

pd2

pd3

DCDC1

Pd2

Th2

AgilentHBT_NPN_Th_THHBT2

Model=HBTM1MatrixRow =2

pd

e

c

th

b

Pd3

Th3

AgilentHBT_NPN_Th_THHBT3

Model=HBTM1MatrixRow =3

pd

e

c

th

b

Pd1

Th1

AgilentHBT_NPN_Th_THHBT1

Model=HBTM1MatrixRow =1

pd

e

c

th

b

Vdc=VCE V

I_DCSRC2Idc=100 uA

(3-finger example)

Temperature distributions:an example (1)

380

400

420

440

460

Tem

pera

ture

[K

]

19

-500

50100

150200

250

-60

-40

-20

0

20

40

60300

320

340

360

x [µm]y [µm]

Tem

pera

ture

[K

]

Temperature distributions:an example (2)

320

320320

320

340

340 360

36010

20

30

40

50

2032

0

320320

320

340

340

340

340

3 4034

0

360

360360

360

380 3 8

0

380400

4 00

400420

440

x [µm]

y [ µ

m]

0 50 100 150 200

-50

-40

-30

-20

-10

0

10

Electrothermal simulation:an example (1)

Array of 3 horse-shoe shaped GaAs HBTs(fabricated by Skyworks Inc.) with a center-to-center spacing of 24 µm and typical fT=47 GHz.

PD=1 mW

Thermal

matrix file

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ADS®

� FEM simulations are used toevaluate thermal matrices fordifferent devices configurations.

� Matrices are then provided tosimulation tool in order to performET simulations.

Electrothermal simulation:an example (2)

40

60

80

100

120 IC measured

IC

SDD HBT

I C [m

A]

TB=300 K

40

60

80

100

120 IC measured

IC SDD HBT

I C [m

A]

TB=300 K

22

1 2 3 40

20

40

VCE [V]

An array of 3 devices with acenter-to-center spacing of24 µm.

An array of 3 devices with acenter-to-center spacing of72 µm.

1 2 3 40

20

40

VCE [V]

Extension to dynamical thermal models� The code will be also extended to include dynamic thermal models for large-signal/small-

signal analysis.� Similar to the thermal resistance, the thermal impedance matrix can be obtained by

measurements, FEM thermal simulations or analytical models� Once the ZTH vs. time or frequency data have been obtained, an appropriate model must be

created that can be included in the ADS environment.� The single-pole network is then replaced by an optimized multi-pole circuit to better mimic

the thermal evolution in time.� An in-house code has been developed to convert Foster network to Cauer network.

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10-10 10-8 10-6 10-4 10-2 1000

1x102

2x102

3x102

4x102

5x102

6x102

7x102

8x102

Numerical simulation

Zth [K

/W]

time [s]

device=q160b

� An in-house code has been developed to convert Foster network to Cauer network.

RTH1RTH2

RTHn

CTH1CTH2

CTHnT0

Tj

PD

( ) 1 TH THi i

tR C

THi

Z t e−

= −

∑

Thermal transient identification algorithm:

an application to silicon-on-glass BJTs

15000

20000 1-pole fit 2-pole fit 3-pole fit Measurements

The

rmal

impe

danc

e [K

/W] 20000

2

devA devA-2AlN devA-4AlN 3-pole fit

The

rmal

impe

danc

e [K

/W]

An algorithm has been developed for the automatic generation of thethermal network with a best-fit approach

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10-5 10-4 10-3 10-20

5000

10000

The

rmal

impe

danc

e [K

/W]

time [s]

10-4 10-3 10-20

10000

AE=1x20 µm2

The

rmal

impe

danc

e [K

/W]

time [s]

The identification software has been tested on several silicon-on-glass (SOG)devices measured with good results. These devices are fabricated by DIMES (Delft,The Netherlands)

Electrothermal simulation:a transient example (1)

10-3

A

Col

lect

or c

urre

nt I C

[A]

VBE=0.75 V

B0.20

0.25

0.30

0.35

VBE=0.75 V

no heatspreaders 2-µm-thick AlN layer 4-µm-thick AlN layer

Col

lect

or c

urre

nt [m

A] A

25

0 2 4 6 85x10-5

10-4 C no heatspreaders 2-µm-thick AlN layer 4-µm-thick AlN layer

Col

lect

or c

urre

nt I

Collector voltage VCE [V]10-6 10-5 10-4 10-3 10-2 10-1 100

0.10

0.15

0.20

Col

lect

or c

urre

nt [m

A]

Time [s]

C

B

SOG electrothermal simulationsperformed with constant base-emitter voltage by varyingcollector-emitter voltage.

Transient evolution of collectorcurrent applying a step of VCEwhile keeping constant VBE.

Conclusions• A novel electrothermal simulation tool relying on the fully automated

employment of the commercial simulator ADS® has been developed.• The thermal network can be either automatically calculated from the circuit

layout or included by the user (e.g., when the thermal resistances areevaluated numerically/experimentally).

• New in-house electrothermal models for active/passive components havebeen developed and made available in the program libraries.

• Transient analyses are enabled through the adoption of equivalent RCFoster networks, which can be automatically optimized via an in-houseroutine.

• Another in-house routine has been developed to convert RC Fosternetworks to RC Cauer networks seamlessly.

• The proposed code has been successfully applied to various bipolartechnologies (e.g., GaAs-based HBTs, multifinger SiGe HBTs, silicon-on-glass BJTs).

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