Unit:1 Number System and Arithmetic circuits: Decimal, Binary, Octal, Hexadecimal – Binary
addition, Multiplication, Division – Floating point representation, Complements, BCD, Excess3,
Gray Code. Arithmetic Circuits: Half adder, Full adder, Parallel binary adder, BCD adder, Half
subtractor, Full subtractor, Parallel binary subtractor - Digital Logic: The Basic Gates – NOR,
NAND, XOR Gates.
Unit:2 Combinational Logic Circuits: Boolean algebra – Karnaugh map – Canonical form
Construction and properties – Implementations – Don’t care combinations - Product of sum,
Sum of products, Simplifications. Sequential circuits: Flip-Flops: RS, D, JK, and T - Multiplexers –
Demultiplexers – Decoder Encoder – Shift Registers-Counters.
Unit:3 Input – Output Organization: Input – output interface – I/O Bus and Interface – I/O Bus
Versus Memory Bus – Isolated Versus Memory – Mapped I/O – Example of I/O Interface.
Asynchronous data transfer: Strobe Control and Handshaking – Priority Interrupt: Daisy-
Chaining Priority, Parallel Priority Interrupt. Direct Memory Access: DMA Controller, DMA
Transfer. Input – Output Processor: CPU-IOP Communication.
Unit:4 Memory Organization: Memory Hierarchy – Main Memory- Associative memory: Hardware
Organization, Match Logic, Read Operation, Write Operation. Cache Memory: Associative, Direct, Set-
associative Mapping – Writing into Cache Initialization. Virtual Memory: Address Space and Memory
Space, Address Mapping Using Pages, Associative Memory, Page Table, Page Replacement.
Unit:5 Case Studies 6 hours CASE STUDY: Pin out diagram, Architecture, Organization and addressing
modes of 80286- 80386-80486-Introduction to microcontrollers.
Unit:6 Contemporary Issues 2 hours Expert lectures, online seminars - webinars
Text Book(s)
1 Digital principles and applications, Albert Paul Malvino, Donald P Leach, TMH, 1996.
2 Computer System Architecture -M. Morris Mano , PHI.
3 Microprocessors and its Applications-Ramesh S. Goankar
Reference Books
2 Computer Architecture, M. Carter, Schaum‘s outline series, TMH.
Prepared By Dr.D.UMA MAHESWARI ASSISTANT PROFESSOR
DEPARTMENT OF COMPUTER SCIENCE GOVERNMENT ARTS AND SCIENCE COLLEGE, VALPARAI
UNIT I Number System and Binary Codes: -Decimal, Binary, Octal, Hexadecimal – Binary addition, Multiplication, Division – Floating point representation, Complements, BCD, Excess3, Gray Code. Arithmetic Circuits: -Half adder, Full adder, -Parallel binary adder ,Parallel binary Subtractor -BCD adder, -Half Subtractor, Full Subtractor Digital Logic: The Basic Gates NOR, NAND, XOR Gates
• NUMBER SYSTEM AND BINARY CODES:
– DECIMAL SYSTEM 0,1……9 radix or base 10
– BINARY SYSTEM-0,1 radix or base 2
– OCTAL SYSTEM 0,1…..7 – radix or base 8
– HEXADECIMAL SYSTEM 0,1…..15 – 10-A – radix or base 16
Digital System
• In digital system the terms bit, nibble, and byte are frequently used.
• Bit is an app of Binary digit.
• Bit is the basic unit of memory and the two binary digits are 0 and 1.
• Byte is a string of 8 bits eg:10011011,01010111 etc.
• Nibble is a string of 4 bits such as 1101,1011 etc.
• In digital systems a group of bits which is stored, operated and moved around is called a word.
• One word consists of 16 bits or two bytes such as 01110100,01010101.
• The first 8 bits represents upper byte and last 8 bits represents the longer byte.
• Chuncking means replacing a longer string of data by a shorter one.
• A Program is a sequence of instructions that tells the
computer,how to process the data. It is also known as
software.
hardware.
Integrated circuits or chips • Digital circuits - are constructed using Ics due to the
advantages of reduction in size, low cost, reduced power consumption, higher operating speed, higher reliability against failure thus less prone to repairs.
• Small Scale Integration (SSI): upto 10 logic gates in a single chip.
• Medium Scale Integration (MSI): 10 to 100 gates per chip .
• Large Scale Integration (LSI):
• Very Large Scale Integration (VLSI):
-More than 10000 gates but less than 100000 gates per chip.
• Ultra Large Scale Integration (ULSI):
-100000 or more gates per chip.
Convert Decimal to binary
332
2
2
2
2
338
10-A ,11-B,12-C,13-D,14-E,15-F
Rules 0+0=0 0+1=1 1+0=1
1+1=10 ie.. 0 with carry over of 1
Rules 0-0=0 1-0=1 1-1=0 0-1=1
ie.. 1 with borrowof 1
BINARY ADDITION • 100101 + 100101
COMPLEMENTS
BCD Adder • *BCD abbreviated as Binary Coded Decimal. • *Each decimal digit of any number lies between 0 to 9 will
be allowed in the BCD form,other combinations ie more than 9 like 1010,1011,1100,1101,1110,1111 (10,11,12,13,14,15)are not possible in BCD forms and are called forbidden groups.
• *Difficulty arises when the sum of the two numbers to added is more than 9
• Ex:9+3=12 in the binary addition we obtain 12 in binary form 1100.
• *But it is allowed in the BCD form. • *To allow BCD we have to add 6 (=0110) • Ex:For adding 9 (=1001)+3(=0011) to the sum is
10010=0001 0010 which is the correct answer in BCD form.
Arithmetic Circuits -Half adder, Full adder,
-Parallel binary adder ,Parallel binary Subtractor -BCD adder,
-Half Subtractor, Full Subtractor
It is a multiple output combinational logic network which
Subtracts two bits of binary data bits producing a different bit d and a borrow bit b as the two output signals.
A
B
Logic
Diagram:
This Logic Diagram using an XOR gate,a NOT gate and an AND gate .
Differnece bit output of a half subtractor is Exclusive OR(XOR) of the two inputs A and B ie., d=A B.
The combinational logic network which subtracts three inputs and two outputs. The two outputs produced are the different bit d and a borrow bit b as the two output signals.
FULL SUBTRACTOR
• Parallel binary adder
• We can add two binary numbers .Let the two binary number to be added be A3 A2 A1 A0 and B3 B2 B1 B0
and their sum C4 S3 S2 S1 S0 where C4 is the final carry.
Example to perform Binary addition of 1110 and 1011. Sol: The full adder on the right most is a half adder and it produces a sum bit of 1 and a carry bit of 0.The second adder which is a full adder as it ha three in outs produce a sum bit of 0 and carry bit of 1.The fourth and last adder which is again a full adder produces a sum bit of 1 and a carry output bit of 1,as it has three inputs which are all1. the binary adder output is 11001 by adding the 1110 and 1011.
Parallel binary Subtractor
A Parallel Subtractor is a digital circuit capable of finding the arithmetic difference of two binary numbers that is greater than one bit in length by operating on corresponding pairs of bits in parallel. The parallel Subtractor can be designed in several ways including combination of half and full Subtractor, all full Subtractor or all full adders with subtrahend complement input
Logic Gates
In Boolean Algebra, there are three basic operations, which are analogous to disjunction, conjunction, and negation in propositional logic. Each of these operations has a corresponding logic gate. Apart from these there are a few other logic gates .
AND gate(.) – The AND gate gives an output of 1 if both the two inputs are 1, it gives 0 otherwise.
OR gate(+) – The OR gate gives an output of 1 if either of the two inputs are 1, it gives 0 otherwise.
NOT gate(‘) – The NOT gate gives an output of 1 input is 0 and vice-versa.
NAND gate()- The NAND gate (negated AND) gives an output of 0 if both inputs
are 1, it gives 1 otherwise.
NOR gate()- The NOR gate (negated OR) gives an output of 1 if both inputs are 0, it
gives 0 otherwise.
NOR gate()- The NOR gate (negated OR) gives an output of 1 if both inputs are 0, it gives 0 otherwise.
XNOR gate()- The XNOR gate (negated XOR) gives an output of 1 both inputs are same and 0 if both are different.
UNIT II
computer circuits
• It can applied in digital circuit Designing and logical Derivations
will understand rules and laws.
• .Learn how to design simple logic circuits.
• Understand how digital circuits work together to form complex
computer systems.
• It is the branch of algebra in which the values of the variable are the truth values true or false, usually denoted 1 and 0 respectively.
• Boolean Algebra was introduced by George Boole in his first book ”The Mathematicla Analysis of Logic “(1987).
• Boolean algebra has been fundamental in the development of digital electronics and is provided for in all modern programming language
• Variable used can have only two values.
– Binary 1 for HIGH.
– -Binary 0 for LOW
BOOLEAN ALGEBRA
• Boolean algebra is a mathematical system for the manipulation of variables that can have one of two values. – In formal logic, these values are “true” and “false.” – In digital systems, these values are “on” and “off,” 1 and 0,
or “high” and “low.”
• Boolean expressions are created by performing operations on Boolean variables. – Common Boolean operators include AND, OR, and NOT.
• In Boolean Algebra here satisfying four properties for any elements.
i) a+b=b+a and a.b=b.a –Commutative Law
ii) a+1=1,a.1=a and a+0=a,a.0=0 –Identity Element
iii) a.(b+c)=a.b+a.c and- Demorgan’s Law
a+(b.c)=a+b.a+c
iv) a+a’=1 and a.a’=0- Complement
4
Karnaugh Map
• The map method first proposed and invented by E.W. Veitch and later modified by M.Karnaugh ,provides a simple set procedure for minimizing the switch function.
Cont..
• Karnaugh maps (K-maps) are made up of squares.Here each squares represents one term.
• The k-map is a systematic method for combining the terms and determining minimal expression.Each n variable map consists of 2n
cells or squares. • Thus a three variable map will consist of 23 or
8 cells or four-variable map will consist of 24
or 16 cells(squares).
Three-Variable K-Map
ee-Variable MapA Three –variable k-map for switching function f(A,B,C).It has 8 cells or squares. The first square has AB value of function=00 and C value=0,thus it represents the binary number ABC=000,which is equal to 0 in the decimal system.
Four-Variable Map
7
The Figure shows Four Variable k-map for a switching function f(A,B,C,D).It has 16 cells and squares. Each square, here again represents a particular decimal value of th function.
Canonical Form 1
• We need to consider formal techniques for the simplification of Boolean functions. – Identical functions will have exactly the same
canonical form.
8
9
Literal: A variable or its complement Product term: literals connected by • Sum term: literals connected by + Minterm: a product term in which all the variables appear exactly once, either complemented or uncomplemented. Maxterm: a sum term in which all the variables appear exactly once, either complemented or uncomplemented.
Definitions
Minterm
• Represents exactly one combination in the truth table.
• Denoted by mj, where j is the decimal equivalent of the minterm’s corresponding binary combination (bj).
• A variable in mj is complemented if its value in bj is 0, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3. Then, bj = 011 and its corresponding minterm is denoted by mj = A’BC
10
• Represents exactly one combination in the truth table.
• Denoted by Mj, where j is the decimal equivalent of the maxterm’s corresponding binary combination (bj).
• A variable in Mj is complemented if its value in bj is 1, otherwise is uncomplemented.
• Example: Assume 3 variables (A,B,C), and j=3. Then, bj
= 011 and its corresponding maxterm is denoted by Mj
= A+B’+C’
12
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
3 0 1 1 0
4 1 0 0 1
5 1 0 1 0
6 1 1 0 0
7 1 1 1 1
Ex:1 Find the Sum of Products(SOP) form of Switching function f(A,B,C) ,which is represented by the truth table given below..
From the table it is evident that the decimal values for which the function f assumes the value ‘1’ are 1,2,4,7. Thus the function f(A,B,C) is the sum of these product term ie=(1,2,4,7)
=(1,2,4,7) =001+010+100+111 f(A,B,C)=A’B’C+A’BC’+AB’C’+ABC WHICH IS THE PRODUCT OF SOP FORM OF THE FUNCTION.
f(A,B,C) ,which is represented by the above truth table .
From the truth table ,it is evident that the decimal values for which the function f assumes the value 0 are 0,3,5,6.Thus the functions f(A,B,C) is product of these sum terms.
14
=II(0,3,5,6) =000+011+101+110 f(A,B,C)=(A+B+C) (A+B’+C’) (A’+B+C’) (A’+B’+C) WHICH IS THE SUM OF POS FORM OF THE FUNCTION.
Construction and properties
- simplifications
The karnaugh map is a modified of the Venn diagram of the switching function with four or less variables in the canonical sum of products form. The switching function, by combining 1 cells into pairs, Quartets or Octets . The variables are represented by 0’s and 1’s . Complemented and uncomplemented variables are represented by 0’s and 1’s. If the switching function consist of 2 variables then the k- map has 4 squares. If the switching function consist of 3 variables then the k- map has 8 squares. If the switching function consist of 4 variables then the k- map has 16 squares.
IMPLICANTS • Any group of 1 can be considered as implicants i.e
combining the minterms set are called implicants. – Prime Implicants – Essential implicants
• Prime Implicants It is a largest possible group of 1’s.
• Essential Prime Implicants • In the group at least ,there is single 1 which cannot combine in
otherway.
Example
Don’t Care Combinations
• The combinations for which the value of the function is not specified with certinity are called don’t care combination .
The value denoted by or D on the karnaugh map.
EXAMPLE:8
Example:1
- Decoder, Encoder -shift register
• Sequential Logic:
– Output depends not only on current input but also on past input values.
Difference between combinational circuit and sequential circuit
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Synchronous vs. Asynchronous There are two types of sequential circuits: Asynchronous sequential circuit – These circuit do not use a clock
signal but uses the pulses of the inputs. These circuits are faster than synchronous sequential circuits because there is clock pulse and change their state immediately when there is a change in the input signal.
Synchronous sequential circuit – These circuit uses clock signal and level inputs (or pulsed) (with restrictions on pulse width and circuit propagation). The output pulse is the same duration as the clock pulse for the clocked sequential circuits. Since they wait for the next clock pulse to arrive to perform the next operation, so these circuits are bit slower compared to asynchronous. Level output changes state.
Synchronous Sequential Circuits: Flip flops as state memory
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The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time, as shown in the timing diagram.
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SR Latch (NAND version)
S
R
Q
Q’
R S 0
Qn+1 Q’n+1
Output CommentsInput
Latch is sensitive to input changes ONLY when C=1
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D Latch OR D FLIP FLOP
• One way to eliminate the undesirable indeterminate state in the RS flip flop is to ensure that inputs S and R are never 1 simultaneously. This is done in the D latch:
D Flip-Flop Table
0 0 1 Reset
1 1 0 Set
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Block Diagram Of Master Slave JK-Flip flop
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•Master Slave JK-Flip flop is a popular way avoiding race
condition or race around problem.
•It is a combination of two clocked latches, the first is called
master and the second is called slave.
•The master is positively clocked and the slave is negatively
clocked implying thereby that when clock is high ,master is
active and slave is inactive.
•When clock is low, master is inactive and slave is active
T Flip-Flop
Flip flop is abbreviated form of Toggle flip-flop here the flip flop changes
state or toggles whenever clock pulse occurs and input T is high.
T flip flop is a single input form of the JK Flip flop and is obtained if both J
and K inputs are tied together
Input Output Commen ts
O Qn Qn+1 No changes
I Qn Qn Toggles
What ever may be the present state of the output, when T is high or ’1’ the output
Qn+1 will change or toggle to the complement of the previous output.
Multiplexer also known as Data Selector,It is a combinational logic circuit which accepts several data inputs and selects only one output line.
Multiplexer
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Here there are four inputs I0, I1, I2, I3 each of which is applied to
one input of each of the four AND gates.
These inputs are transmitted to the output according to four possible
combinations of two select inputs s1 and s0.
The outputs of all the AND gates are applied to a single OR gate,
which gives a one line output.
The size of the multiplexer is given by 2n to 1 line, where 2n stands
for the number of its output lines, and n stands form number of
selection lines or select inputs.
Applications:
Multiplexer find wide variety of applications in digital systems. The
main applications of multiplexers in digital systems are data routing,
data selection, parallel to serial conversion, operation sequencing,
waveform generation and logic function generation.
Demultiflexer
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A Demultiflexer ,also known as data distributor ,It takes a single input and transmits information
on one of the 2n possible output lines.
From the above Truth table, we can directly write the Boolean functions for each output as
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DECODER Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines.
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block diagram
of 2 to 4 decoder is shown in the following figure.
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Decoders may be designed for any of the codes by using gates and also it is possible to display
the letters of the alphabet. Light emitting diodes are mostly used as light sources for the read
out display. Encoders
An Encoder is a reverse operation of decoder .It has 2n or less input lines and n output lines.
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Shift Registers
Serial In − Serial Out SISO Shift Register
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Serial In − Parallel Out SISO Shift Register
The shift register, which allows parallel input and produces serial output is known as
Parallel In − Serial Out PISO shift register. The block diagram of 3-bit PISO shift
register is shown in the following figure .
Parallel In − Serial Out SISO Shift Register
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-
flop is connected as the input of next D flip-flop. All these flip-flops are synchronous with each
other since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset
Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to
the next. So, we will get the serial output from the right most D flip-flop
Parallel In - Parallel Out PIPO Shift Register
The shift register, which allows parallel input and produces parallel output is known as Parallel In −
Parallel Out PIPO shift register. The block diagram of 3-bit PIPO shift register is shown in the
following figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop
is connected as the input of next D flip-flop. All these flip-flops are synchronous with each other
since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to
1. We can apply the parallel inputs through preset or clear. These two are asynchronous inputs. That
means, the flip-flops produce the corresponding outputs, based on the values of asynchronous inputs.
In this case, the effect of outputs is independent of clock transition. So, we will get the parallel
outputs from each D flip-flop.
•Shift register is used as Parallel to serial converter, which
converts the parallel data into serial data. I
•t is utilized at the transmitter section after Analog to Digital
Converter ADCADC block.
•Shift register is used as Serial to parallel converter, which
converts the serial data into parallel data.
•It is utilized at the receiver section before Digital to Analog
Converter DACDAC block.
•Shift register along with some additional gates generate the
sequence of zeros and ones. •Hence, it is used as sequence generator.
•Shift registers are also used as counters.
•There are two types of counters based on the type of output from
right most D flip-flop is connected to the serial input.
• Those are Ring counter and Johnson Ring counter.
COUNTERS
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A Counter is register, which is capable of counting the number of clock pulse, which have arrived at
its clock input. These counters are used for counting pulses in large variety of counting applications
such as control systems,computers,electronic and scientific instruments, etc.
Conters can be classified into following two types.
Asynchronous counters or ripple counter
Synchronous counters
A ripple counter is also called an asynchronous counter, because it is an asynchronous
sequential circuit.
UNIT-III
i)I /O Bus and interface Modules
-The I/O bus consists of data lines, address lines and control lines. -The magnetic disk, printer and terminal are employed in any general purpose computers. -The magnetic tape is used in some computers for backup storage. -Each interface decodes the address and control received from the I/O bus, intercepts them for the peripheral, and provides signal for the peripheral controller.
-Each peripheral has its own controller that operates the particular electromechanical device.
-The I/O bus from the processor is attached to all peripheral interfaces.
Control command- is used t activated the peripheral and to inform it what to do.
Status command- is used to test various status conditions in the interface and the peripheral.
Data Output command-causes the interface to respond by transferring data from the bus into one of its register.
Input Data command- is the opposite of the data output.
ii)I/O Bus versus Memory bus
ii)Isolated versus Memory-Mapped I/O
Parallel Priority Interrupt Direct Memory Access:
DMA Controller DMA Transfer
Priority interrupt
-Polling 2.Hardware Priority Interrupt -Serial Priority (Daisy Chaining)
-Parallel Priority
• A Priority interrupt is a system that Establishes a priority over various sources to determine which condition is to be serviced first when two or more request arrive simultaneously.
• The system may also determine which condition are permitted to interrupt the computer while another interrupt is being serviced.
• When two devices interrupt the computer at the same time, the computer services the device, with the higher priority first.
Priority Interrupt
• Devices with high-speed transfers such as magnetic disks are given
higher priority, and slow devices such as keyboard or mouse receive
low priority.
Polling is the software method of establishing priority of
simultaneous interrupt.
In this method when a processor detects an interrupt ,it branches
interrupt service routine.
The order in which they are tested determines the priority of each
interrupt.
The highest priority source is tested first, and if its interrupt signal is on,
control branches to a service routine for this source.
Disadvantage of polling:
If there are many interrupt sources the time required to poll them can be
exceed the time available to service the I/O device
It is very time consuming. 1 2 3 4 5 6 7 8 .
Hardware Priority Interrupt
It accepts interrupt requests from many sources, determines which of the incoming requests has the highest priority, and issues an interrupt request to the computer based on this determination. To speed up the operation ,each interrupt source has its own interrupt vector to access its own service routine directly. The hardware priority function can be established by either serial or parallel connection of interrupt lines.
It consist of serial connection of all devices that request an interrupt. The devices with highest priority is placed in the first position, followed by lower priority devices up to the device with the lowest priority which is placed last in the chain.
• The CPU responds to an interrupt request by enabling the interrupt acknowledge line.
• If any device has its interrupt signal in the low level state, the interrupt line goes to the low level state and enabled the interrupt input in the CPU.
• The signal is received by device 1 at its P1(priority in)input.
• The acknowledge signal passes on to the next device to through the PO(priority out)output only if device 1 is not requesting an interrupt.
• If device 1 has pending interrupt, it blocks the acknowledge signal from the next device by placing a 0 in the PO output.
• It then proceeds it to insert its own interrupt vector address into the data bus for the CPU to use during the interrupt cycle.
UNIT IV Memory Organization: -Memory Hierarchy – Main Memory Associative memory: -Hardware Organization -Match Logic -Read Operation -Write Operation Cache Memory:
-Associative -Direct -Set-associative Mapping -Writing into Cache
-Cache Initialization Virtual Memory: -Address Space and Memory Space -Address Mapping Using Pages -Associative Memory Page Table -Page Replacement
MEMORY HIERARCHY IN A COMPUTER SYSTEM
Magnetic tapes
Magnetic disks
I/O processor
Main Memory
Magnetic Disk
Magnetic Tape
Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system
Memory Hierarchy
MAIN MEMORY
CS1 CS2 RD WR
0 0 x x 0 1 x x 1 0 0 0 1 0 0 1 1 0 1 x 1 1 x x
Memory function
State of data bus
High-impedence High-impedence High-impedence Input data to RAM Output data from RAM High-impedence
Chip select 1
Chip select 2
Output
Memory