Digital Integrated Circuits - Študentski.net · 2019. 3. 20. · © Digital Integrated Circuits2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing

© Digital Integrated Circuits2nd

Sequential Circuits

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits

Jan M. RabaeyAnantha ChandrakasanBorivoje Nikolic

November 2002


Sequential Circuits

Sequential LogicSequential Logic

2 storage mechanisms

• positive feedback

• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

CLK

Q D

Current State

Inputs


Sequential Circuits

Naming ConventionsNaming Conventions

In our text: a latch is level sensitive a register is edge-triggered

There are many different naming conventions For instance, many books call edge-

triggered elements flip-flops This leads to confusion however


Sequential Circuits

Latch versus RegisterLatch versus Register Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Register

stores data when clock rises

Clk Clk

D D

Q Q


Sequential Circuits

LatchesLatches

In

clk

In

Out

Po sitive Latch

CLK

DG

Q

Out

Outs tab le

Outfollows In

In

clk

In

Out

Neg ative Latch

CLK

DG

Q

Out

Outs tab le

Outfollows In


Sequential Circuits

Latch-Based DesignLatch-Based Design

• N latch is transparentwhen φ = 0

• P latch is transparent when φ = 1

NLatch

Logic

Logic

PLatch

φ


Sequential Circuits

Timing DefinitionsTiming Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q


Sequential Circuits

Characterizing TimingCharacterizing Timing

Clk

D Q

tC 2 Q

Clk

D Q

tC 2 Q

tD 2 Q

Register Latch


Sequential Circuits

Maximum Clock FrequencyMaximum Clock Frequency

FF

’s

LOGIC

tp,comb

φ

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

tclkQ + tp,comb + tsetup = T


Sequential Circuits

Positive Feedback: Bi-StabilityPositive Feedback: Bi-StabilityV i1 Vo2

Vo2 = V i 1

Vo1 = V i 2

Vi1

A

C

B

Vo2

Vi1=Vo2

Vo1 Vi2

Vi2=Vo1


Sequential Circuits

Meta-StabilityMeta-Stability

Gain should be larger than 1 in the transition region

A

C

d

B

Vi2

5V

o1

V i1 5 Vo2

A

C

d

B

Vi2

5V

o1

V i1 5 Vo2


Sequential Circuits

Writing into a Static LatchWriting into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOSonly)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states


Sequential Circuits

Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=


Sequential Circuits

Mux-Based LatchMux-Based Latch

CLK

CLK

CLK

D

Q


Sequential Circuits

Mux-Based LatchMux-Based Latch

CLK

CLK

CLK

CLK

QM

QM

NMOS only Nonoverlapping clocks


Sequential Circuits

Master-Slave (Edge-Triggered) Master-Slave (Edge-Triggered) RegisterRegister

1

0D

CLK

Q M

Master

0

1

CLK

Q

Slave

Q M

Q

D

Two opposite latches trigger on edgeAlso called masterslave latch pair


Sequential Circuits

Master-Slave RegisterMaster-Slave Register

Q M

Q

D

CLK

T2I2

T1I1

I3 T4I5

T3I4

I6

Multiplexerbased latch pair


Sequential Circuits

Clk-Q DelayClk-Q Delay

D

Q

CLK

2 0.5

0.5

1.5

2.5

tc 2 q(lh)

0.5 1 1.5 2 2.50time, nsec

Vol

ts

tc 2 q(hl)


Sequential Circuits

Setup TimeSetup Time

D

Q

Q M

CLK

I2 2 T2

2 0.5

Vol

ts

0.0

0.2 0.4time (nsec)

(a) Tsetup5 0.21 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0

DQ

Q M

CLK

I2 2 T2

2 0.5V

olts

0.0

0.2 0.4time (nsec)

(b) Tsetup5 0.20 nsec

0.6 0.8 10

0.5

1.0

1.5

2.0

2.5

3.0


Sequential Circuits

Reduced Clock Load Reduced Clock Load Master-Slave RegisterMaster-Slave Register

D QT1 I1

CLK

CLK

T2

CLK

CLKI2

I3

I4


Sequential Circuits

Avoiding Clock OverlapAvoiding Clock OverlapCLK

CLK

A

B

(a) Schematic diagram

(b) Overlapping clock pairs

X

D

Q

CLK

CLK

CLK

CLK


Sequential Circuits

Overpowering the Feedback Loop ─Overpowering the Feedback Loop ─Cross-Coupled PairsCross-Coupled Pairs

Forbidden State

S

S

R

QQ

Q

QRS Q

Q00 Q

101 0

010 1

011 0RQ

NORbased setreset


Sequential Circuits

Cross-Coupled NANDCross-Coupled NAND

S

QR

Q

M1

M2

M3

M4

Q

M5S

M6CLK

M7 R

M8 CLK

VDD

Q

Crosscoupled NANDsAdded clock

This is not used in datapaths any more,but is a basic building memory cell


Sequential Circuits

Sizing IssuesSizing Issues

Output voltage dependence on transistor width

Transient response

4.03.53.0W/L5 and 6

(a)

2.52.00.0

0.5

1.0

1.5

2.0

Q (

Vo

lts)

time (ns)

(b)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

W = 1 mµ

3

Vo

lts

Q S

W = 0.9 mµW = 0.8 mµ

W = 0.7 mµW = 0.6 mµ

W = 0.5 m


Sequential Circuits

Storage MechanismsStorage Mechanisms

D

CLK

CLK

Q

Dynamic (chargebased)

CLK

CLK

CLK

D

Q

Static


Sequential Circuits

Making a Dynamic Latch Pseudo-StaticMaking a Dynamic Latch Pseudo-Static

D

CLK

CLK

D


Sequential Circuits

More Precise Setup TimeMore Precise Setup Time

tD 2 C

t

t

t

tC 2 Q1.05tC 2 Q

tSu

tH

Clk

D

Q


Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

Setup/Hold Time IllustrationsSetup/Hold Time Illustrations

Circuit before clock arrival (Setup1 case)

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1


Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1




Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

Timet=0

ClockDataTSetup-1



D

CN

QM

CP

D1SM

Inv1

Inv2TG1


Sequential Circuits

Clk-Q Delay

TSetup-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

ClockDataTSetup-1




Sequential Circuits

Timet=0

ClockDataTSetup-1

D

CN

QM

CP

D1SM

Inv1

Inv2TG1



Clk-Q Delay

TSetup-1

TClk-Q

Time


Sequential Circuits


Hold1 case

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1

0

Clk-Q Delay

THold-1

TClk-Q

Time


Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

Timet=0

DataClockTHold-1


Hold1 case

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

0


Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

DataClockTHold-1


Hold1 case

0


Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


Hold1 case

0


Sequential Circuits

Clk-Q Delay

THold-1

TClk-Q

Time

D

CN

QM

CP

D1SM

Inv1

Inv2TG1

Timet=0

Clock

THold-1

Data


Hold1 case

0

⇒


Sequential Circuits

Other Latches/Registers: COther Latches/Registers: C22MOSMOS

M1

D Q

M3CLK

M4

M2

CLK

VDD

CL1

X

CL2

Master Stage

M5

M7CLK

CLK M8

M6

VDD

“Keepers” can be added to make circuit pseudostatic


Sequential Circuits

Insensitive to Clock-OverlapInsensitive to Clock-Overlap

M1

D Q

M4

M2

0 0

VDD

X

M5

M8

M6

VDD

(a) (0-0) overlap

M3

M1

D Q

M2

1

VDD

X

M71

M5

M6

VDD

(b) (1-1) overlap


Sequential Circuits

PipeliningPipeliningR

EG

RE

G

RE

G

log

a

CLK

CLK

CLK

Out

b

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

RE

G

CLK

RE

G

CLK

Out

b

Reference Pipelined


Sequential Circuits

Other Latches/Registers: TSPCOther Latches/Registers: TSPC

CLKIn

VDD

CLK

VDD

In

Out

CLK

VDD

CLK

VDD

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)


Sequential Circuits

Including Logic in TSPCIncluding Logic in TSPC

CLKIn CLK

VDDVDD

QPUN

PDN

CLK

VDD

Q

CLK

VDD

In1

In1 In2

AND latchExample: logic inside the latch


Sequential Circuits

TSPC RegisterTSPC Register

CLK

CLK

D

VDD

M3

M2

M1

CLK

Y

VDD

Q

Q

M9

M8

M7

CLK

X

VDD

M6

M5

M4


Sequential Circuits

Pulse-Triggered LatchesPulse-Triggered LatchesAn Alternative ApproachAn Alternative Approach

Master-Slave Latches

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edgetriggered sequential cell:


Sequential Circuits

Pulsed LatchesPulsed Latches

CLKGD

VDD

M3

M2

M1

CLKG

VDD

M6

Q

M5

M4

CLK

CLKG

VDD

XMP

MN

(a) register (b) glitch generation


Sequential Circuits

Pulsed LatchesPulsed LatchesHybrid Latch – Flipflop (HLFF), AMD K6 and K7 :

P1

M3

M2D

CLK

M1

P3

M6

Qx

M5

M4

P2


Sequential Circuits

Hybrid Latch-FF TimingHybrid Latch-FF Timing

20.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.20.0 0.4

QD

time (ns)

Vo

lts

0.6 0.8 1.0

CLKDCLK


Sequential Circuits

Latch-Based PipelineLatch-Based Pipeline

F G

CLK

CLK

In Out

C1 C2

CLK

C3

CLK

CLK

Compute F compute G


Sequential Circuits

Non-Bistable Sequential Circuits─Non-Bistable Sequential Circuits─Schmitt TriggerSchmitt Trigger

In Out

Vin

VoutVOH

VOL

VM– VM+

•VTC with hysteresis•Restores signal slopes


Sequential Circuits

Noise Suppression using Schmitt Noise Suppression using Schmitt TriggerTrigger

Vin

t0

VM−

VM+

t

Vout

t0 + tp t


Sequential Circuits

CMOS Schmitt TriggerCMOS Schmitt Trigger

Moves switching thresholdof the first inverter

Vin

M2

M1

VDD

X Vout

M4

M3


Sequential Circuits

Schmitt Trigger Simulated VTCSchmitt Trigger Simulated VTC

2.5

VM2

VM1

Vin (V)

Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4 . The width isk* 0.5 m.m

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5

2.5

k = 2k = 3

k = 4

k = 1

Vin (V)

2.0

1.5

1.0

0.5

0.00.0 0.5 1.0 1.5 2.0 2.5


Sequential Circuits

CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)

VDD

VDD

OutIn

M1

M5

M2

X

M3

M4

M6


Sequential Circuits

Multivibrator CircuitsMultivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


Sequential Circuits

Transition-Triggered MonostableTransition-Triggered Monostable

DELAY

td

In

Outtd


Sequential Circuits

Monostable Trigger (RC-based)Monostable Trigger (RC-based)VDD

InOutA B

C

R

In

B

Outt

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


Sequential Circuits

Astable Multivibrators (Oscillators)Astable Multivibrators (Oscillators)

0 1 2 N-1

Ring Oscillator

simulated response of 5-stage oscillator

0.0

0.0

0.5

1.0

1.5

2.0

2.5V1 V3 V5

3.0

20.50.5

time (ns)

Vo

lts

1.0 1.5


Sequential Circuits

Relaxation OscillatorRelaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC


Sequential Circuits

Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (

nsec

)

propagation delay as a functionof control voltage


Sequential Circuits

Differential Delay Element and VCODifferential Delay Element and VCO

in 2

two stage VCO

v1

v2

v3

v4

Vctrl

Vo 2 Vo 1

in 1

delay cell

simulated waveforms of 2-stage VCO

0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

20.51.5

V1 V2 V3 V4

time (ns)2.5 3.5

Documents

Digital Integrated Circuits - Študentski.net · 2019. 3. 20. · © Digital Integrated Circuits2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing