86
Discussion of exam problems 1

Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

  • Upload
    leduong

  • View
    219

  • Download
    0

Embed Size (px)

Citation preview

Page 1: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Discussion of exam problems

1

Page 2: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Hint for Homework problem 72: Show how to connect three Full Adders to implement a 2-bit “ripple-carry” adder

2

Page 3: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

3

C D A B

X Y

Connect to ground (0)

Z

Page 4: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Chapter 5

Computing Components

Components

Circuits

Gates

Transistors

Yet another layer of

abstraction!

Page 5: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

5

5.1 Individual Computer Components

Consider the following ad: Insatavialion 640 Laptop Exceptional Performance and Portability!

It’s just a made-up example!

Page 6: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

6

What does all this jargon mean?

• Intel® Core™ 2 Duo (2.66GHz/1066Mhz FSB/6MB cache)

• 4GB Shared Dual Channel DDR2 at 800 MHz• 500 GB SATA Hard Drive at 5400RPM• 15.6” High Definition (1080p) LED Backlit

LCD Display (1366 x 768)• 8X Slot Load DL DVD+/- RW Drive • 14.8”W X 1.2”H X10.1” D, 5.6 lbs.• 512 MB ATI Mobility Radeon Graphics• 85 WHr Lithium Ion Battery• (2) USB 2.0, HDMI, 15-Pin VGA, Ethernet 10/100/1000 IEEE

1394 Firewire, Express Card, Audio line-in, line-out, mic-in

Be patient!You don't knowthem now, but you will getused to them.

Page 7: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Multipliers

7

When referring to computer memory, mega does not mean one million! (but it’s still close to that)

Page 8: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

8

Decimal vs. binary multipliers

1000 = 103 1,000,000 = 106 1,000,000,000 = 109

1024 = 210 1024*1024 = 220 1024*1024*1024 = 230

Rule:For memory capacities, the multipliers are binary, for everything else (speed, frequency, pixels, etc.) they are decimal

Page 9: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

9

Decimal vs. binary multipliersexamples

What is the meaning of:• 1.5 TB hard-disk • 54 Mbps wireless Ethernet• 6 GB of RAM• 8 Mega-pixel camera• 3.2 GHz CPU

Page 10: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Intel® Core™ 2 Duo (2.66GHz/1066Mhz, FSB/6MB cache)

10

Page 11: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: A CPU chip is rated 2.5 GHz.

What is the duration of one clock cycle? Use appropriate units!

11

Page 12: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: A CPU chip is rated 2.5 GHz. What is the duration of one clock cycle? Use appropriate units!

Solution: 2.5∙109 Hz = frequency = f == 1/(duration of one CLK cycle) = 1/T

T = 1/f = 1/2.5∙10-9 s = 0.4 ns

12

Page 13: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Quick work for next time:A CPU chip is rated 3.44 GHz.

What is the duration of one clock cycle? Use appropriate units!

13

Page 14: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

5.2 Stored-Program Concept

14

The von Neumann (a.k.a. Princeton) architecture is based on two fundamental ideas:1. Instructions and data are the same, so they are stored in the

same circuit (memory)2. Information processing is different from information storage,

so they are performed in different circuits (CPU, memory)

Page 15: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Are there any other architectures?

15

The Harvard architecture is based on two fundamental ideas:1. Instructions and data are not the same, so they are stored in

separate circuits (memories)2. Information processing is different from information storage,

so they are performed in different circuits (CPU, memory)

Image source: http://www.mikroe.com/chapters/view/74/pic-basic-book-chapter-1-world-of-microcontrollers/

Not in text

Page 16: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: Which of the diagrams depicts a von Neumann architecture?

16

Page 17: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: Which of the diagrams depicts a von Neumann architecture?

17

Page 18: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Main Memory (MM)

18

Remember that in the vN architecture there is only one MM, which stores both data and programs!

Page 19: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

19

ComponentsCircuitsGates

Transistors

Which hardware layer does memory belong to?

Image sources: http://www.mypcmobile.com/memory.phphttp://www.imagener.com/top-six-photo-enlargement-tips

Main Memory “Blades”

Page 20: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Main Memory =A collection of cells,each with a uniquephysical addressBoth addresses andcontents are in Binary (or hex)

Cells can be bits, nibbles, bytes, words

Page 21: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZThe address and contents of a memory cell are the following, in hex:

89AB FC

Translate them into decimal and binary.

Page 22: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Addressability = the # of bits in each cell

What is the addressabilityof the memory pictured?

Today, most computers’ memories are byte-addressable

Page 23: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ1. How many bytes of memory

are in the MM pictured?

2. Express the result using the

appropriate multiplier.

Page 24: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ

1. How many bits does the

address have in this memory?

2. What is the addressability?

0x789ABCDE 0x789A

EOHF1

Page 25: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: Connect each hardware item to the layer it belongs to:

Components

Circuits

Gates

Transistors

• mouse• XOR• Intel 8008• NTE 2996 MOSFET• MUX• motherboard• full adder• SR latch

Page 26: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: A CPU’s frequency is 12 KHz.

What is the duration of one clock cycle? Use appropriate units!

26

Page 27: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: A CPU’s clock cycle is 55 ns.

What is the frequency?Use appropriate units!

27

Page 28: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

28

ALU

Page 29: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

ALU

• basic arithmetic operations such as add, subtract, increment, decrement, change sign, multiply, integer division• logical operations such as AND, OR, XOR, NOT

29

Page 30: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The ALU also has a few very fast storage units called registers• The information in a register can be processed

quickly (in one CLK cycle), w/o waiting for a lengthy (~10 ns) memory transfer.

30Figure source: http://www10.edacafe.com/book/

Page 31: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

31

The von Neumann architecture

Input/Output devices

Page 32: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Input/Output devices

Input deviceA device through which data and programs fromthe outside world are entered into the computer;

Can you name three?

Output deviceA device through which results stored in thecomputer memory are made available to theoutside world

Can you name three?

32

Page 33: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

33

The von Neumann architecture

Control Unit

Page 34: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Control UnitIt is the organizing force in the computerImplements the fetch-execute cycleIncludes two important registers:• Instruction register (IR) →Contains the instruction that is being executed• Program counter (PC) → Contains the address of the next instruction to be executed

ALU + Control Unit = CPU

34

Page 35: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Flow of Information Bus = A set of wires that connect all major units in a computer

35

Data flow through a von Neumann architecture

Page 36: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Flow of Information Bus = A set of wires that connect all major units in a computer

36

Data flow through a von Neumann architectureHow can we tell that it’s a vN architecture?

Page 37: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Flow of Information Bus = A set of wires that connect all major units in a computer

37

Is there another kind of memory?

Page 38: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

FSB and BSB

38

Cache

Back-side Bus (BSB)

Front-side Bus (FSB)

Note: Although the CPU can access two memory circuits, this is still considered a vN architecture, b/c the cache is much smaller than the MM.

Page 39: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

39

Find the info about bus and cache in the ad!

Page 40: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The Fetch-Execute Cycle

Fetch the next instructionDecode the instructionGet data (if needed)Execute the instruction

Why is it called a cycle?40

Remember: In a vN machine, both instructions and data are stored in the same memory!

Page 41: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The Fetch-Execute Cycle

41

Read carefully pp.133-135 of text!

Page 42: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

RAM and ROM

The memory used for the main memory (MM) of a computer is of 2 types: RAM and ROM

• Both can be accessed directly , i.e. in constant time, by providing a memory address.• Both can be read.

• However, when it comes to writing …

Page 43: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

RAM and ROM

Random Access Memory (RAM):• can be changed (written)• is volatile

Read Only Memory (ROM):• cannot be changed (written) • is not volatile

Take this with a grain of salt: Today’s ROMs can be written, just not as fast as RAMs.

Page 44: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Secondary Storage

The size of the MM (RAM+ROM) in today’s computers ranges between …

44

The amounts of data we need to store are much larger!

• Example: Youtube video clips ≤ 20 GB

Secondary storage is a.k.a. mass/volume/bulk storage.

Page 45: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Secondary Storage technologies

• Magnetic: drum, tape, floppy disk, hard disk (internal or external)

• Semiconductors: flash drive , SD card• Optical: CD-R (WORM=Write Once Read Many

times), DVD-R, DVD-R DL, Blue-Ray• Emerging: spintronics (MRAM), Ferroelectric RAM, DNA

storage, etc.

45

Page 46: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Other benefits of Secondary Storage

Portability …Reliability (backups) …Modularity (add as you go) …

46

Page 47: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Magnetic TapeThe first truly mass storage device was the magnetic tape drive

Tape drives have amajor problem; canyou spot it?

Figure 5.4 A magnetic tape

Page 48: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The first high-volume auxiliary storage device was the magnetic tape drive

Image sources:http://museum.ipsj.or.jp/en/computer/device/magnetic_tape/0003.htmlhttp://www.computerhistory.org/revolution/memory-storage/8/258/1025http://wodumedia.com/large-hadron-collider-ready-to-restart/

1964

1993

2013

Page 49: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Magnetic Disk - HDD

• Amount of information (bits, bytes) is the same on all tracks• Disc rotates at the same angular velocity no matter which track is being read → same transfer rate on all tracks!• Tracks near center are more densely packed with information

Platter

Page 50: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: HDD

A HDD has 512 Bytes/sector, 256 sectors/track, and 10 platters.The diameter of each platter is 100 mm, and each track is 1 mm wide.

Calculate the total capacity of the drive in MB.

Use binary Mega!

Page 51: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Solution

125 MB

A HDD has 512 Bytes/sector, 256 sectors/track, and 10 platters.The diameter of each platter is 100 mm, and each track is 1 mm wide.

Calculate the total capacity of the drive in MB.

Page 52: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Seek timeTime it takes for read/write head to be over right trackLatencyTime it takes for sector to be in position under R/W head

Access time = Seek time + latency

Transfer rate (e.g. 100 MB/s)

52

Page 53: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: HDD

The arm of a HDD moves at an average velocity of 40 m/s. The platter diameter is 100 mm.

What are the minimum and maximum possible seek times?Calculate the average seek time.

53

Page 54: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The arm of a HDD moves at an average velocity of 40 m/s. The platter diameter is 100 mm.

What are the minimum and maximum possible seek times?Calculate the average seek time.

54

1.25 ms

Solution

Page 55: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: HDD

The spindle of a HDD rotates at 7200 RPM.What are the minimum and maximum possible latencies?Calculate the average latency.

55

Page 56: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

The spindle of a HDD rotates at 7200 RPM.What are the minimum and maximum possible latencies?

Calculate the average latency. 4.16 ms

56

Solution

Page 57: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: HDD

If the previous 2 quizzes refer to the same HDD, what is its average access time?

57

Page 58: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

If the previous 2 quizzes refer to the same HDD, what is its average access time?

4.16 ms + 1.25 ms = 5.41 ms

58

Solution

Page 59: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: HDD

A file is on the HDD, on 15 consecutive blocks of the same track. Each block stores 4 KB.

Average seek time = 10 ms, average latency = 5 ms.Once the first block is under the head, data is transferred at a rate

of 50 MB/s.Calculate the total time needed to transfer the file.

59

Page 60: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

60

Solution

A file is on the HDD, on 15 consecutive blocks of the same track. Each block stores 4 KB.

Average seek time = 10 ms, average latency = 5 ms.

Once the first block is under the head, data is transferred at a rate of 50 MB/s.

Total time needed to transfer the file: 16.23 ms

Page 61: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

61Source: http://nextshark.com/ibm-5mb-hard-drive/

Page 62: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Quick Work for next time

• Read text pages 131-139• Solve exercises 24 - 29

62EoHW2

Page 63: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ: Computer Components

Explain in your own words the functions of the following components:

• ALU• Control Unit• Input device• Main Memory• Cache

63

Page 64: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

What do the acronyms FSB and BSB stand for?

Compare and contrast them.

64

Page 65: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

What do the acronyms FSB and BSB stand for?

Compare and contrast them.

65

Page 66: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Magnetic Disks - RemovableFloppy disks (Why "floppy"?)Year when they first became commercially available:1969 (8-inch)1976 (5¼-inch)1982 (3½-inch)

66

1.44 MB87 KB-1.2 MB

80-500 KB

Page 67: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Magnetic Disks - Removable

Zip disks• Iomega, 1994• 100 MB, 250 MB, 750 MB

67

Page 68: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

68

Flash memory• IBM 1998• Nonvolatile!• Can be erased and rewritten

– But there’s a rub: Flash Endurance• No moving parts!

Thumb drives

Solid State Drives (SSD)

Page 69: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

To do in notebook for next time:Calculate the cost per gigabyte for HDD and SDD

69Source: www.newegg.com October 2013

Page 70: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Optical DisksCD (600 MB)A compact disk that uses a laser to read information stored optically on a plastic disk; data is evenly distributed around track

CD-ROM read-only memoryCD-DA digital audioCD-WORM or CD-R user can write once, read many timesCD-RAM or CD-RW user can both write and read many times

DVD (4.7 GB)Digital Versatile Disk, used for storing audio and videoDL = dual layer → 8.5 GB

Blu-Ray (25 GB)DL = dual layer → 50 GB

70

Page 71: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

CD (600 MB)

DVD (4.7 GB)

Blu-Ray (25 GB)

Hints: The average MP3 file is 4 MB.Use binary multipliers!

71

Your turn! How many songs can be stored on each type of optical disk?

Page 72: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

CD (600 MB)

DVD (4.7 GB)

Blu-Ray (25 GB)

Hints: The average MP3 file is 4 MB.Use binary multipliers!

72

How many songs can be stored on each type of optical disk?

Solution

Page 73: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Interesting difference between magnetic and optical drives/disks:

– On a magnetic disk, each track has the same amount on data, there is no accounting for length (center or periphery). The limiting track is the innermost one!

– On an optical disk, data is uniformly packed per sector length → Short tracks (near the center) have less datathan long tracks (near the periphery).

– In a HDD, the speed of rotation is constant, but in an optical drive rotation is faster on the inner tracks, resulting in Constant Linear Velocity (CLV)

73

Page 74: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Read and take notes: Touch Screens

74

Page 75: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

75

5.3 Embedded Systems

Computers that are dedicated to perform a narrow range of functions as part of a larger system.

“Every computer that doesn’t have a normal display and keyboard”

How many embedded systems do you think are in this room?

Page 77: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

77

5.4 Parallel Architectures

Remember that a vN architecture has one main memory and one CPU.There are two ways to evolve into non-vN architectures:1. Multiple main memories (Harward

arch.)2. Multiple CPUs, a.k.a. parallel arch.

Page 78: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

78

Parallel Arch.: Synchronous processing

One approach to parallelism is to have multiple processors apply the same program to multiple data sets:

Figure 5.8 Processors in a synchronous computing environment

Page 79: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

79

Synchronous processing example:

Image source: http://tatourian.com/2013/09/03/nvidia-gpu-architecture-cuda-programming-environment/

Not in text

GPU = Graphics Processing Unit • It was invented by NVIDIA in 1999

Page 80: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

80

Parallel Arch.: Pipelining

Processors are arranged in tandem, with each processor contributing one part to an overall computation

Figure 5.9 Processors in a pipeline

Page 81: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

81

Washer-dryer analogyNot in text

Page 82: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

82

Train analogyNot in text

Page 83: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Find the # of steps in terms of n and k

83

n k

# of steps is n+k-1

Hint: Concentrate on the last car!

Page 84: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

QUIZ Pipelining

A computer pipeline has 3 stages, as shown above.Each stage takes 8 ms to execute, and each instruction must go sequentially through all 3 stages.A program has 5 instructions. Calculate how long it takes to run it:• without pipelining• with pipelining

84

Page 85: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

85

Parallel Arch.: Parallel Processor

It’s made of a number of vN processors which communicate through shared memory• Unlike synchronous processing, there is no central control.• Each CPU participates in a distributed control protocol!

Figure 5.10 Shared memory configuration of processors

Page 86: Discussion of exam problems the info about bus and cache in the ad! The Fetch-Execute Cycle Fetchthe next instruction Decode the instruction Get data (if needed) Execute the instruction

Quick-work for next time:• Read pp.130-137 of our text and take notes• Answer end-of-chapter questions 30-38, 42-47

86

Homework:39, 40, 41, 48, 49, 54, 56, 63, 64, 66Due Tuesday, Oct.23 at beginning of class