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Division of Telecommunication Fundamentals Mariusz Rawski [email protected]

Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski [email protected]. ... emphasis on PLD

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Page 1: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Division of Telecommunication

Fundamentals

Mariusz [email protected]

Page 2: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Research and teaching activities

• Synthesis and design of digital circuits (with special emphasis on PLD and FPGA circuits) using computer tools for prototyping and industrial applications

• Design, evaluation and testing of cryptographic algorithms and techniques

• Logic synthesis for easily testable circuits,design of self testing circuits with built in circular test paths

• Issues of design of self-healing connections in broadband telecommunication networks which use asynchronous transfer mode (ATM) and the virtual path (VP) concept

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Page 3: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Novel Digital Signal and Image Processing Software and Hardware Novel Digital Signal and Image Processing Software and Hardware for Information Systemsfor Information Systems

DCD: Digital circuits development group

Current methodologies and productivity improvements are failing to keep pace with the rapid and ongoing increase in complexity and technology improvements

„FPGAs are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago.”Uwe Meyer-Baese, DSP with FPGAs, 2004.System on Programmable Chip

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Page 4: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Hardware-software co-design

affordable cost

satisfactoryperformance

Software

Advantages

• Easy and fast

implementation

Disadvantages

• Poor performance

Hardware

Advantages

• Good performance

Disadvantages

• Time-consuming

and complicated

design process

ASIC

Hardware-software co-design

Fast implementation

Good performance

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Page 5: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Our recent achievements

• In the frame of international grant with Nanyang

Technological University (Singapore) a logic synthesis

method targeted for FPGA architectures with

specialized embedded memory blocks has been

developed.

• A study of the efficiency of different implementation

methodologies of DSP algorithms targeted for modern

FPGA architectures has been performed.

• Many IP Cores for DSP, cryptography, data transmission

have been designed and tested

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Page 6: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Selected research topics

• „The Front-end driver’s firmware for data acquisition

system in the TOTEM experiment”

• „Heterogenic Distributed System for Cryptanalysis of

Elliptic Curve Based Cryptosystems”

• „FPGA Implementation of Feature Extraction Algorithm

for Speaker Verification”

• „Implementation of SpaceWire network protocol in

programmable structures”

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Page 7: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

� Journals1. C. C. Lozano, B. J. Falkowski, and S. Rahardja. Properties and relations for fast linearly independent arithmetic transforms. IET Signal Processing, 1(2):82−95, June

2007.

2. M. Rawski. Decomposition of Boolean function Sets, Electronics and Telecommunications Quarterly, vol. 53, No. 3, pp. 231-249, Warsaw 2007.

3. B. J. Falkowski, C. C. Lozano, and T. Łuba. Family of fastest linearly independent transforms over GF(3): generation, relations, and hardware implementation. Journal of Multiple-Valued Logic and Soft Computing, 13(4−6): 379−396, September 2007.

4. M. Rawski, B. J. Falkowski, and T. Łuba. Digital signal processing designing for FPGA architectures. Facta Universitatis, 20(3): 459−477, December 2007.

5. M. Rawski, H. Selvaraj, B. J. Falkowski, T. Łuba. Significance of Logic Synthesis in FPGA-Based design of Image and Signal Processing Systems, chapter in book Verma, B. and Blumenstein, M. (eds.) (2008). Pattern Recognition Technologies and Applications: Recent Advances, IGI Global Press, USA. (In Press).

6. B. J. Falkowski. Phase watermarking algorithm using hybrid multi-polarity Hadamard transform. Journal of Mathematical Imaging and Vision, 30(1): 13−21, January 2008.

� Conferences7. Falkowski B., Łuba T.: Analysis of Biomedical Images with Intracellular Fluorescent Dye Concentrations of Living cells. First Singaporean-French Biomedical Imaging

Workshop, pp. 64-65, 12-13 October 2006, Biopolis, Singapore.

8. G. Borowik, B. J. Falkowski, and T. Łuba. Cost-efficient synthesis for sequential circuits implemented using embedded memory blocks of FPGA’s. In Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pages 99−104, Krakow, Poland, April 2007.

9. M. Rawski, B. J. Falkowski, and T. Łuba. Decomposition-based synthesis in implementation of digital filters for wavelet transform application targeted FPGA devices. In Proceedings of the 2007 IEEE Instrumentation and Measurement Technology Conference, CD publication, Warsaw, Poland, May 2007.

10. B. J. Falkowski, C. C. Lozano, and T. Łuba. Efficient algorithm for calculation of quaternary fixed polarity arithmetic expansions. In Proceedings of the 37th IEEE International Symposium on Multiple-Valued Logic, CD Publication, Oslo, Norway, May 2007.

11. B. J. Falkowski, C. C. Lozano, and T. Łuba. New fastest linearly independent transforms over GF(3). In Proceedings of the 37th IEEE International Symposium on Multiple-Valued Logic, CD Publication, Oslo, Norway, May 2007.

12. P. Tomaszewicz, M. Nowicka, B. J. Falkowski, and T. Łuba. Logic synthesis importance in FPGA-based designing of image signal processing systems. In Proceedings of the 14th IEEE International Conference on Mixed Design of Integrated Circuits and Systems, pages 135−140, Ciechocinek, Poland, June 2007.

13. Rawski M., Wojtyński M., Wojciechowski T., Majkowski P.: Distributed Arithmetic Based Implementation of Fourier Transform Targeted at FPGA Architectures, In Proceedings of the 14th IEEE International Conference on Mixed Design of Integrated Circuits and Systems, pp. 152-156, Ciechocinek, Poland 21-23 June, 2007.

14. B. J. Falkowski, T. Sasao, and T. Łuba. Programmable hardware implementation based on four Walsh sequences. In Proceedings of the 14th IEEE International Conference on Mixed Design of Integrated Circuits and Systems, pages 141−146, Ciechocinek, Poland, June 2007.

15. B. J. Falkowski, C. C. Lozano, and T. Łuba. Properties and relations of new fastest linearly independent arithmetic transforms for ternary functions. In Proceedings of the 15th European Signal Processing Conference, pages 2129−2133, Poznan, Poland, September 2007.

16. Rawski M., Tomaszewicz P., Falkowski B.J., Łuba T.: Application of Advanced Logic Synthesis in FPGA-based Implementations of Digital Filters, DASIP 2007 - Design & Architectures for Signal and Image Processing, pp. 1-8, Grenoble, France, 27-20 November, 2007.

17. Falkowski B., Lozano C., Łuba T.: Properties and Relations of New Fastest Linearly Independent Arithmetic Transforms for Ternary Functions, Proceedings of the 15th European Signal Processing Conference, EUSIPCO 2007, Poznań, Poland, 3-4 September, 2007.

18. M. Rawski, B. Falkowski, T. Łuba. Logic Synthesis Method for FPGAs with Embedded Memory Blocks, IEEE International Symposium on circuits and systems, Seattle, May 2008.

19. C. C. Lozano, B. J. Falkowski, and T. Luba. Properties and computational algorithm for fastest Quaternary Linearly Independent Transforms. 38th ISMVL, May 22-23, Dallas 2008.

20. B. Falkowski, C. Lozano, T. Łuba. Reliability Analysis Based on Arithmetic and Boolean Representations. MIXDES Poznań, 19 – 21 June 2008. 21. C. Lozano, B. Falkowski, T. Łuba. Ternary Polynomial Expansions Based on Generalized Fastest Linearly Independent Arithmetic Transforms. . MIXDES Poznań, 19 – 21

June 2008.

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Publication list

[16] Rawski M., Tomaszewicz P., Falkowski B.J., Łuba T.: Application of Advanced Logic Synthesis in FPGA-based Implementations of Digital Filters, DASIP 2007 - Design & Architectures for Signal and Image Processing, pp. 1-8, Grenoble, France, 27-20 November, 2007.

[9] M. Rawski, B. J. Falkowski, and T. Łuba. Logic Synthesis Method for FPGAs with Embedded Memory Blocks. In Proceedings of IEEE International Symposium on Circuits and Systems, Seattle, May 2008.

[5] [5] M. M. RawskiRawski, H. , H. Selvaraj, Selvaraj, B. J. B. J. Falkowski, Falkowski,

T. T. ŁŁuba. Significance of Logic Synthesis uba. Significance of Logic Synthesis

in FPGAin FPGA--Based design of Image and Based design of Image and

Signal Processing Systems, Signal Processing Systems, chapter in chapter in

book Verma, B. and Blumenstein, M. book Verma, B. and Blumenstein, M.

(eds.) (200(eds.) (20088). Pattern Recognition ). Pattern Recognition

Technologies and Applications: Recent Technologies and Applications: Recent

AdvancesAdvances, IGI Global Press, USA. (In , IGI Global Press, USA. (In

Press). Press).

7

Page 8: Division of Telecommunication Fundamentals7pr.kpk.gov.pl/pliki/10952/Rawski.pdfDivision of Telecommunication Fundamentals Mariusz Rawski rawski@tele.pw.edu.pl. ... emphasis on PLD

Division of Telecommunication

Fundamentals

Mariusz [email protected]