DLD Ch 4 (Combinational Logic)

1

COMBINATIONA L LOGICDr. Abdul Sattar Malik

Combinational Circuits Output is function of input only i.e. no feedback

n inputs

Combinational Circuits

m outputs

When input changes, output may change (after a delay)

Combinational Circuits Design Given a desired function, determine its circuit Function may be expressed as:

?

Boolean function Truth table

Analysis Given a circuit, find out its function Function may be expressed as:

A B C A B C A B A C B C

F1

??

Boolean function Truth table

F2

Design Procedure The problem is stated The number of available input variables and required output

variables is determined The input & output variables are assigned letter symbols The truth table that defines the required relationship between inputs and outputs is derived The simplified Boolean function for each output is obtained The logic diagram is drawn

ADDERS Digital computers perform a variety of information-processing tasks. Among the basic functions Encountered are the various arithmetic operations.

The most basic arithmetic operation, no doubt, is the addition of two binary

digits. This simple addition consists of adding two binary bits (0+0=0, 0+1=1, 1+0=1, &

1+1 =10). The first three operations produce a sum whose length is one digit, but when both augend and addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is called a CARRY. When the augend and addend numbers contain more significant digits, the carry obtained from the addition of two bits is added to the next higher-order pair of significant bits.

A combinational circuit that performs the addition of two bits is called a half-

adder. One that performs the addition of three bits (two significant bits and a previous carry) is a full-adder.

HALF ADDER Half Adder Adds 1-bit plus 1-bit Produces Sum and Carryx y

HA x + y C S

S C

x y

0 0 1 1

0 1 0 1

C 0 0 0 1

S 0 1 1 0

x

SC

y

HALF ADDER

FULL ADDER Full Adder Adds 1-bit plus 1-bit plus 1-bit Produces Sum and Carryx y z S C

FA

x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

z 0 1 0 1 0 1 0 1

C 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

x + y + z C Sy0 0 1 z C = xy + xz + yz 1 1 0 1

y0 x 1 1 0 z S = xy'z'+x'yz'+x'y'z+xyz =xyz 0 1 1 0 x 0

FULL ADDERx y z x y z x y z x y z

S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yzx y zx y x z y z

x

S x y z C

S

y

x y

C

z

x z y z

FULL ADDERx y z x S y z C HA HA S

C

HALF SUBTRACTOR Half Subtractor Subtracts 1-bit from 1-bit Produces Difference and Borrowx y

HS B x - y D

D B

x y

0 0 1 1

0 1 0 1

B 0 1 0 0

D 0 1 1 0

x

DB

y

FULL SUBTRACTOR Full Subtractor Subtracts 1-bit from 1-bit and from another 1-bit Produces Difference and Borrow

x y z

FS

D B

x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

z 0 1 0 1 0 1 0 1

B 0 1 1 1 0 0 0 1

D 0 1 1 0 1 0 0 1

x - y - z B Dy0 1 0 z 1 1 1 0

y0 x 1 1 0 z D = xy'z'+x'yz'+x'y'z+xyz =xyz 0 1 1 0 x 0

D = x'y + x'z + yz

FULL SUBTRACTORx y z x y z x y z x y z

D = xy'z'+x'yz'+x'y'z+xyz = x y z B = x'y + x'z + yzx y zx y x z y z

x

D x y z B

D

y

x y

B

z

x z y z

FULL SUBTRACTORx y z x D y z B HS HS D

B

BCD TO EXCESS-3 CODE CONERTERA B 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 w 0 0 0 0 0 1 1 1 1 1 x x x x x x x 0 1 1 1 1 0 0 0 0 1 x x x x x x y 1 0 0 1 1 0 0 1 1 0 x x x x x x z 1 0 1 0 1 0 1 0 1 0 x x x x x x

C1 x 1 1 x 1 1 x x 1 x x 1 x x

C1 x x

B A

A

1 x

x 1

B

D

D

w = A+BC+BDC1 1 x 1 1 1 x x

x = BC+BD+BCDC B A1 1 x 1 1 1 x x

A

x

x x

x

x x

B

D y = CD+CD z = D

D

BCD TO EXCESS-3 CODE CONERTERA B 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 w 0 0 0 0 0 1 1 1 1 1 x x x x x x x 0 1 1 1 1 0 0 0 0 1 x x x x x x y 1 0 0 1 1 0 0 1 1 0 x x x x x x z 1 0 1 0 1 0 1 0 1 0 x x x x x xA

w

xB

C

y zw = A + B(C+D) x = B(C+D) + B(C+D) y = (C+D) + CD z = D

D

SEVEN SEGMENT DECODERw 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 abcdefg 1111110 0110000 1101101 1111001 0110011 1011011 1011111 1110000 1111111 1111011 xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx

w x y z

?BCD codey1 x 1 1 x 1 1 1 x x 1 1 x x

a b c d e f g

af e g b c

dx b=... c=... d=...

w

z a = w + y + xz + xz

DESIGN PROBLEMS1. Design a combinational circuit with three inputs and one output. The

2.

3.

4.

5.

output is equal to logic-1 when the binary value of the input is less than 3. The output is logic-0 otherwise. Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input. A majority function is generated in a combinational circuit when the output is equal to 1 if the input variables have more 1's than 0's. The output is 0 otherwise. Design a 3-input majority function. Design a combinational circuit that adds one to a 4-bit binary number, A3A2A1A0. For example, if the input of the circuit is A3A2A1A0 = 1101, the output is 11 10. The circuit can be designed using four half-adders. A combinational circuit produces the binary sum of two 2-bit numbers, X1X0 and Y1Y0. The outputs are C, S1, and S0. Provide a truth table of the combinational circuit.

DESIGN PROBLEMSDesign the circuit of Problem 4-5 using two full-adders. 7. Design a combinational circuit that multiplies two 2-Bit numbers, A1A0 and B1B0, to produce a 4-bit product, C3C2C1C0. Use AND gates and half-adders. 8. Show that a Full-Subtractor can be constructed with two half-Subtractors and an OR gate. 9. Design a combinational circuit with three inputs and six outputs. The output binary number should he the square of the input binary number. 10. Design a combinational circuit with four inputs that represent a decimal digit in BCD and four outputs that produce the 9's complement of the input digit. The six unused combinations can be treated as don't-care conditions. 11. Design a combinational circuit with four inputs and four outputs. The output generates the 2's complement of the input binary number.6.

DESIGN PROBLEMS12. Design a combinational circuit that detects an error in the

representation of a decimal digit in BCD. The output of the circuit must he equal to Logic -1 when the input contains any one of the six unused bit combinations in the BCD code. 13. 4-13 Design a code converter that converts a decimal digit from the 8 4 -2 -1 code to BCD 14. Design a combinational circuit that converts a decimal digit from the 2 4 2 1 code to the 8 4 -2 - 1 code 15. Design a combinational circuit that converts a binary number of four bits to a decimal number in BCD. Note that the BCD number is the same as the binary number as long as the input is less than or equal to 9. The binary number from 1010 to 1111 converts into BCD numbers from 1 0000 to 1 0101.21

ANALYSIS PROCEDURE(BOOLEAN EXPRESSION APPROACH)1. Label with arbitrary symbols all gate outputs that are a function

of the input variables.

Obtain the Boolean functions for each gate.

2. Label with other arbitrary symbols those gates that are a

function of input variables and/or previously labeled gates.

Find the Boolean functions for these gates.

3. Repeat the process outlined in step 2 until the outputs of the

circuit are obtained. 4. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables only.

ANALYSIS PROCEDURE(BOOLEAN EXPRESSION APPROACH)A B C A B C A B A C B CAB+AC+BC

F1ABC A+B+C AB'C'+A'BC'+A'B'C

(A+B)(A+C)(B+C)

F2

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC

ANALYSIS PROCEDURE(TRUTH TABLE APPROACH)1. Determine the number of input variables to the circuit. For n

inputs, form the 2n possible input combinations of 1's and 0's by listing the binary numbers from 0 to 2n - 1. 2. Label the outputs of selected gates with arbitrary symbols. 3. Obtain the truth table for the outputs of those gates that are a function of the input variables only. 4. Proceed to obtain the truth table for the outputs of those gates that are a function of previously defined values until the columns for all outputs are determined.

ANALYSIS PROCEDURE(TRUTH TABLE APPROACH)

A=0 B=0 C= 0 A=0 B=0 C= 0 A=0 B=0 A=0 C =0 B C= 0 =0

0

0

F1

F1 F2 A B C 0 0 0 0 0

0 1 0 0 0 0

0

F2


A=0 B=0 C= 1 A=0 B=0 C= 1 A=0 B=0 A=0 C =1 B C= 0 =1

0

1

F1

1 1 0 0 0 0

1

F1 F2 A B C 0 0 0 0 0 0 0 0 1 1

F2


A=0 B=1 C= 0 A=0 B=1 C= 0 A=0 B=1 A=0 C =0 B C= 1 =0

0

1

F1

1 1 0 0 0 0

1

A 0 0 0

B 0 0 1

F1 F2 C 0 0 0 1 1 0 0 0 1

F2


A=0 B=1 C= 1 A=0 B=1 C= 1 A=0 B=1 A=0 C =1 B C= 1 =1

0

0

F1

1 0 0 0 1 1

0

A 0 0 0 0

B 0 0 1 1

F1 F2 C 0 0 0 1 1 0 0 1 0 1 1 0

F2


A=1 B=0 C= 0 A=1 B=0 C= 0 A=1 B=0 A=1 C =0 B C= 0 =0

0

1

F1

1 1 0 0 0 0

1

A 0 0 0 0 1

B 0 0 1 1 0

F1 F2 C 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1

F2


A=1 B=0 C= 1 A=1 B=0 C= 1 A=1 B=0 A=1 C =1 B C= 0 =1

0

0

F1

1 0 0 1 0 1

0

F2

A 0 0 0 0 1 1

B 0 0 1 1 0 0

F1 F2 C 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0


A=1 B=1 C= 0 A=1 B=1 C= 0 A=1 B=1 A=1 C =0 B C= 1 =0

0

0

F1

1 0 1 0 0 1

0

F2

A 0 0 0 0 1 1 1

B 0 0 1 1 0 0 1

F1 F2 C 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0

ANALYSIS PROCEDURE(TRUTH TABLE APPROACH)A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1

A=1 B=1 C= 1 A=1 B=1 C= 1 A=1 B=1 A=1 C =1 B C= 1 =1

1

1

F1

1 0 1 1 1 1

0

F2

F1 F2 C 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1

B 0 A 1 1 0 C 0 1 1 0 A 0 0 0 1 C 1 1

B 0 1

F1=AB'C'+A'BC'+A'B'C+ABC

F2=AB+AC+BC

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DLD Ch 4 (Combinational Logic)