double litho, double etch (LELE) process challenges for ... · PDF fileDouble litho, double etch (LELE) process challenges for 22nm HP and beyond M. Maenhoudt, V. Wiaux, S. Cheng,

Double litho, double etch (LELE) process challenges for 22nm HP and beyond

M. Maenhoudt, V. Wiaux, S. Cheng, G. Vandenberghe, K. Ronse

M. Maenhoudt© imec 2008 2

Approaching the Optical Limit: Practical Methods for Patterning 22nm HP and Beyond

ITRS roadmap

data data extrapolation



scope of the presentation

• litho-etch-litho-etch has been demonstrated for 32nm hp– can be used for logic, DRAM and Flash– SADP = alternative for Flash, DRAM: not discussed here

• what is extendibility of LELE towards 22nm HP and beyond using same NA water based immersion scanners?– only process challenges are discussed



Outline

• Assumptions• CD target

– litho

– etch

• CDU• pitch• overlay• LWR/LER• summary



Assumptions

• Double Line scheme for BF layers (STI, Poly)• Double Trench scheme for DF layers (Metal, CH)

• Logic: – Metal1 most critical pitch– 2D patterns (gaps, cuts, jogs, … after design split)– annular illumination– other layers more feasible with single patterning and DFM

• Flash:– 4 critical layers (STI, Gate, Contact, Metal)– 1D patterns most critical– annular illumination: allows simultaneous printing of periphery– dipole illumination: better resolution, but separate mask/exposure

needed for periphery



Outline

• Assumptions

• CD target– litho

– etch

• CDU• pitch• overlay• LWR/LER• summary



CD target active/poly: etch

• target CD determined by litho + subsequent etch steps, trim possible– pop1: litho (+ trim) + etch1 + etch2– pop2: litho (+ trim) + etch2

constant litho-etch bias through dose allows larger litho target below 20nm is easiest with LELE (L1 and L2 decoupled)



CD target active/poly: trim

• line trim (after BARC etch, before HM etch)– allows to print larger line (optimum half pitch per pass: 44nmL on

88nm pitch for 22nm node) larger PW better CDU– but will induce some extra CD variation across wafer

trade-off?Litho1 44MCD/22HP Exp Dose Dependence

15

20

25

30

35

40

45

50

15 16 17 18 19 20 21 22 23 24 25

Exp Dose (mJ/cm2)

Line

CD

(nm

)

44MCD/22HP Line CD

non-linear behaviour

CD after trim (MCD 56, pitch128nm)

0

5

10

15

20

25

30

35

40

45

Litho 0 sec 10 sec 15 sec 20 sec 25 sec

trim time

CD (n

m)

trim allows larger litho target below 20nm is easiest with LELE (L1 and L2 decoupled)



CD target M1: shrink needed

• trench at 1:3 ratio has very small PW, at ratio 1:2 largest– shrink technique (chemical, plasma assisted) needed, adds to CDU

budget

Motif Plasma-assisted shrink

SubstrateDielectric

deposition etchshrink process cycle

20

25

30

35

40

Jun/29 Jul/23 Aug/15 Sep/7 Sep/30 Oct/23Date

Stability of Motif shrinkmore shrink needed for 22nm hp better control necessary



CD target challenges: etch crosstalk

• pop1 impacted by CD1 (litho target) + etch/strip1 + etch/strip2 + etch3 contribution– reason: insufficient planarization?

• pop2 impacted by CD2 + etch/strip2 + etch3 contribution– topo for Litho2– effect of pattern1 density on CD2 target? both litho and etch can be affected

After HM etch L139.25nm

After HM etch L238.26nm

After HM etch L1/L242.13nm /34.41nm

1

2

Images in HM

no topo no topo on topo E1

extra variation to be included in OPC modeling



CD target: overlapping areas

• overlapping areas: etch stop needed (double HM?)

more complex stack with DP, not necessarily more complex for smaller hp



Outline

• Assumptions• CD target

• CDU

• pitch• overlay• LWR/LER• summary



CDU challenge

• CDU total pop. determined by 2 pop. each with own CDU

• CDU needs to be 10% 3σ, DPT has extra contributors compared to SE better control needed for each contributor

SE DPT schemeA DPT schemeBlitho Litho Litho

Etch +strip Shrink etch+strip

Etch+strip Litho

Litho etch+strip

Shrink etch

Etch + strip

Etch

e.g. 32nm HP:3.2nm CDU litho 2.26nm 3σ+etch 2.26nm 3σ

e.g. 32nm HP:3.2nm CDU each litho 1.43nm 3σ+each etch 1.43nm 3σ

SP DP



CDU poly/active

• 32nm hp CDU applying Dosemapper™: CD’s after final etch– intrafield + interfield data– no difference L1 and L2: good topo planarization

NA=1.35ann. ill. 0.8/0.5k1f =0.22

Process corrections have potential to reduce CDU, 22nm hp within reach but process control (matching populations) and

stability is crucial!

Line1:Mean=34.93σ=2.2nm

Line 2Mean=34.63σ=2.3nm

Space 2Mean=28.53σ=3.8nm

Space 1Mean= 30.03σ=3.7nm



CDU data M1: effect of shrink

• 30nm hp M1 CDU data on 1700i (grid only)

25 30 35 40 45 50 55 60 65

Trench CD (nm)

Cou

nts

(a.u

.)

After Motif + MHM etch3σ=2.6nm

After Litho3σ=2.5nm

shrink step for M1 does not impact CDU



Outline

• Assumptions• CD target• CDU

• pitch

• overlay• LWR/LER• summary



Flash minimum pitch

• DP pitch is double of SP pitch

minimum pitch at NA=1.35 is below 20nm



logic Metal1 pitch challenges

• annular illumination is preferred– allows best through pitch and 2D patterning

– will limit k1f to 0.3 for ‘random DP’– will limit k1f to 0.25 for ‘DP + design compliance’

• process variation used for experimental data at NA=1.2

DO

SE

BE

-3.5%

+3.5%

BF 40-40

Mask bias +0.5nm

Mask nominal

Mask bias -0.5nm



min. pitch after split: experimental data

• 44nm HP at NA=1.2 : minimum pitch after split for logic limited by gap:

B2A6JPitch 106nm (k1f =0.33) Gap 46nm

Pitch 90nm (k1f =0.28)Gap 70nm

Aggressive gaps Aggressive pitch



towards 22nm HP logic?

• 45nm HP 2D DP at NA=1.35– 100nm pitch, gap 46 for k1f = 0.35– 88nm pitch , gap 66nm for k1f = 0.3

design compliance needed

• stitching robustness is determined by line end control smaller CD at same NA will become more difficult more design compliance needed

•32nm HP logic M1 possible if strong design compliance and good process control

•22nm HP logic M1: unlikely if randomness is maintained (regularity needed!)



Outline

• Assumptions• CD target• CDU• pitch

• overlay

• LWR/LER• summary



overlay challenge

• Overlay Metrology Complexity w.r.t DPT Processing

IBMK. Ausschnitt, Overlay Metrology Panel, SPIE 2007

Active Active

Gate Gate

Contact Contact

Metal Metal

Mask A Mask B



overlay challenges for Flash

• mask/process/scanner contributions• alignment L1 to previous layer and L2 to previous layer

L2 to L1 overlay on ASML XT:1700i:

X Error-10.0 0.0 +10.0

nm Y Error nmX Error-10.0 0.0 +10.0

nm Y Error nm

|m|+3σ: X = 5.5nm, Y = 5.8nm

30 points per field, 87 fields per wafer, 20 wafers.

target 2-2.5nm 3s improvements needed/planned



overlay challenges for Logic

• overlay L2-L1 less critical for robust stitching in 2D patterns than variations due to line/trench- end shape and position through process variations

0

10

20

30

40

50

60

MAS

K ST

ITC

HIN

G

OVE

RLA

P (n

m)

Compensate for trench-end pull-back and rounding

Compensate for overlay error

+10nm Overlay

overlay is less issue than LES



Outline

• Assumptions• CD target• CDU• pitch• overlay

• LWR/LER

• summary



LWR/LER

• same problems as for SP, but smaller absolute values needed for smaller CD

• process optimization needed/possible?

litho BARC opening

MHM etch + strip

BTMotif

4.9nm 6.9nm 9.5nm 6.9nm 5.0nm

30nm hp M1 3σ

LWR:(~200 images)



Outline

• Assumptions• CD target• CDU• pitch• overlay• LWR/LER

• summary



Summary: LELE towards 22nm hp and beyond

• General findings for 22nm hp using LELE:– CD targets are within reach – Process corrections required to meet CDU requirements– Tool overlay needs further improvement (especially for

flash, keep an eye on process overlay contributions)– minimum pitch (flash) requirements are within reach

• Logic will require more regularity in designs– LWR/LER: not LELE specific but big concerns (resist, etch

solutions ?)

• Compared to 32nm hp :– Development of integrated process control mandatory

• Fast in-line metrology with clever sampling plans• Feedback and feedforward corrections



Acknowledgements

• Litho: D. Vangoidsenhoven, A. Miller, J. Versluijs, D. Laidler, P. Leray, S. Verhaegen

• Etch: S. Locorotondo, M. Demand, J-F de Marneffe

• IMEC Pline



Thank you!

Documents

double litho, double etch (LELE) process challenges for ... · PDF fileDouble litho, double etch (LELE) process challenges for 22nm HP and beyond M. Maenhoudt, V. Wiaux, S. Cheng,