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EC-2254 LINEAR INTEGRATED CIRUITS

II YEAR / IV SEMESTER ECE

SUBJECT NOTES

SYLLABUS

EC 2254 LINEAR INTEGRATED CIRCUITS 3 0 0 3

AIM:

To teach the basic concepts in the design of electronic circuits using linear integrated circuits and theirapplications in the processing of analog signals.

OBJECTIVES

To introduce the basic building blocks of linear integrated circuits.

To teach the linear and non-linear applications of operational amplifiers.

To introduce the theory and applications of analog multipliers and PLL.

To teach the theory of ADC and DAC

To introduce the concepts of waveform generation and introduce some special function Cs.

UNIT - I IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR ICS

9

Advantages of Cs over discrete components ! "anufacturing process of monolithic cs ! Construction of

monolithic bipolar transistor ! "onolithic diodes ! ntegrated #esistors ! "onolithic Capacitors !nductors. Current mirror and current sources$ Current sources as active loads$ %oltage sources$ %oltage

#eferences$ &'T Differential amplifier with active loads$ (eneral operational amplifier stages -and internal

circuit diagrams of C )*+$ DC and AC performance characteristics$ slew rate$ ,pen and closed loop

configurations.

UNIT - II APPLICATIONS OF OPERATIONAL AMPLIFIERS 9

ign Changer$ cale Changer$ Phase hift Circuits$ %oltage ollower$ %-to- and -to-% converters$ adder$

subtractor$ nstrumentation amplifier$ ntegrator$ Differentiator$ Logarithmic amplifier$ Antilogarithmic

amplifier$ Comparators$ chmitt trigger$ Precision rectifier$ peak detector$ clipper and clamper$ Low-pass$

high-pass and band-pass &utterworth filters.

UNIT - III ANALOG MULTIPLIER AND PLL 9

Analog "ultiplier using /mitter Coupled Transistor Pair - (ilbert "ultiplier cell - %ariable

transconductance techni0ue$ analog multiplier Cs and their applications$ ,peration of the basic PLL$

Closed loop analysis$ %oltage controlled oscillator$ "onolithic PLL C 121$ application of PLL for A"

detection$ " detection$ 3 modulation and demodulation and re0uency synthesi4ing.

UNIT - IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS 8

+

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Analog and Digital Data Conversions$ D5A converter ! specifications - weighted resistor type$ #-6# Ladder

type$ %oltage "ode and Current-"ode R2R Ladder types - switches for D5A converters$ high speedsample-and-hold circuits$ A5D Converters ! specifications - lash type - uccessive Appro7imation type -ingle lope type - Dual lope type - A5D Converter using %oltage-to-Time Conversion - ,ver-sampling

A5D Converters.

UNIT - V AVEFORM GENERATORS AND SPECIAL FUNCTION IC! 9

ine-wave generators$ "ultivibrators and Triangular wave generator$ aw-tooth wave generator$ CL89:8

function generator$ Timer C 111$ C %oltage regulators - Three terminal fi7ed and ad;ustable voltage

regulators - C )6: general purpose regulator - "onolithic switching regulator$ witched capacitor filter C

"+9$ re0uency to %oltage and %oltage to re0uency converters$ Audio Power amplifier$ %ideo

Amplifier$ solation Amplifier$ ,pto-couplers and fibre optic C.

TOTAL : 45 PERIODS

TE"T BOO#S:

+. ergio ranco$ Design with operational amplifiers and analog integrated circuits$ : rd/dition$ Tata

"c(raw-

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UNIT -I

IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR IC!

I$%&'()%&* C+(,+%! :

An integrated circuit CB is a miniature$ low cost electronic circuit consisting of active and

passive components fabricated together on a single crystal of silicon. The active components are

transistors and diodes and passive components are resistors and capacitors.

A*.)$%)'&! +$%&'()%&* ,+(,+%!:"iniaturi4ation and hence increased e0uipment density.

Cost reduction due to batch processing.

ncreased system reliability due to the elimination of soldered ;oints.

mproved functional performance.

"atched devices.

ncreased operating speeds.

#eduction in power consumption

C1)!!++,)%+$:

ntegrated circuits can be classified into analog$ digitaland mi7ed signal both analog and digital

on the same chipB. &ased upon above re0uirement two different C technology namely "onolithic

Technology and

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Digital integrated circuits can contain anything from one to millions of logic gates$ flip-flops$

multiple7ers$ and other circuits in a few s0uare millimeters. The small si4e of these circuits allows

high speed$ low power dissipation$ and reduced manufacturing cost compared with board-level

integration. These digital Cs$ typically microprocessors$ DPs$ and micro controllers work using

binary mathematics to process one and 4ero signals.

Analog Cs$ such as sensors$ power management circuits$ and operational amplifiers$ work by

processing continuous signals. They perform functions like amplification$ active filtering$

demodulation$ mi7ing$ etc. Analog Cs ease the burden on circuit designers by having e7pertly

designed analog circuits available instead of designing a difficult analog circuit from scratch.

Cs can also combine analog and digital circuits on a single chip to create functions such as A5D

convertersand D5A converters. uch circuits offer smaller si4e and lower cost$ but must carefully

account for signal interference

C1)!!++,)%+$ IC!:

ntegrated Circuits

"onolithic Circuits

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G&$&()%+$!

SSI MSI )$* LSI

The first integrated circuits contained only a few transistors. Called mall-cale ntegration

B$ digital circuits containing transistors numbering in the tens provided a few logic gates for

e7ample$ while early linear Cs such as the PlesseyL69+ or thePhilipsTAA:69 had as few as

two transistors. The term Large cale ntegration was first used by &" scientist #olf Landauer

when describing the theoretical concept$ from there came the terms for $ "$ %L$ and L.

They began to appear in consumer products at the turn of the decade$ a typical application being

"inter-carrier sound processing in televisionreceivers.

The ne7t step in the development of integrated circuits$ taken in the late +?29s$ introduced devices

which contained hundreds of transistors on each chip$ called "edium-cale ntegration "B.

They were attractive economically because while they cost little more to produce than devices$

they allowed more comple7 systems to be produced using smaller circuit boards$ less assembly

work because of fewer separate componentsB$ and a number of other advantages.

VLSI

The final step in the development process$ starting in the +?89s and continuing through the present$

was very large-scale integration %LB. The development started with hundreds of thousands of

transistors in the early +?89s$ and continues beyond several billion transistors as of 699).

n +?82 the first one megabit #A"chips were introduced$ which contained more than one million

transistors. "icroprocessor chips passed the million transistor mark in +?8? and the billion

transistor mark in 6991

ULSI SI SOC )$* 3D-IC

To reflect further growth of the comple7ity$ the term L that stands for ltra-Large cale

ntegration was proposed for chips of comple7ity of more than + million transistors.

1

http://en.wikipedia.org/wiki/Plesseyhttp://en.wikipedia.org/wiki/Philipshttp://en.wikipedia.org/wiki/FMhttp://en.wikipedia.org/wiki/Televisionhttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Random_Access_Memoryhttp://en.wikipedia.org/wiki/Plesseyhttp://en.wikipedia.org/wiki/Philipshttp://en.wikipedia.org/wiki/FMhttp://en.wikipedia.org/wiki/Televisionhttp://en.wikipedia.org/wiki/VLSIhttp://en.wikipedia.org/wiki/Random_Access_Memory

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>afer-scale integration>B is a system of building very-large integrated circuits that uses an

entire silicon wafer to produce a single super-chip. Through a combination of large si4e and

reduced packaging$ > could lead to dramatically reduced costs for some systems$ notably

massively parallel supercomputers. The name is taken from the term %ery-Large-cale ntegration$

the current state of the art when > was being developed.

ystem-on-a-ChipoC or ,CB is an integrated circuit in which all the components needed for a

computer or other system are included on a single chip. The design of such a device can be

comple7 and costly$ and building disparate components on a single piece of silicon may

compromise the efficiency of some elements.

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C$!%(,%+$ ) M$1+%+, B+1)( T()$!+!%(:

The fabrication of a monolithic transistor includes the following steps.

+. /pita7ial growth

6. ,7idation

:. Photolithography

*. solation diffusion

1. &ase diffusion

2. /mitter diffusion

). Contact mask

8. Aluminium metalli4ation

?. Passivation

The letters P and = in the figures refer to type of doping$ and a minus -B or plus FB with P and =

indicates lighter or heavier doping respectively.

6 E+%)7+)1 '(%:

The first step in transistor fabrication is creation of the collector region. >e normally

re0uire a low resistivity path for the collector current. This is due to the fact that$ the collector

contact is normally taken at the top$ thus increasing the collector series resistance and the % C/atB of

the device.

)

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The higher collector resistance is reduced by a process called buried layer as shown in figure. n

this arrangement$ a heavily doped G=H region is sandwiched between the =-type epita7ial layer and

P ! type substrate. This buried =F layer provides a low resistance path in the active collector

region to the collector contact C. n effect$ the buried layer provides a low resistance shunt path for

the flow of current.

or fabricating an =P= transistor$ we begin with a P-type silicon substrate having a

resistivity of typically +I-cm$ corresponding to an acceptor ion concentration of +.* J +9+1

atoms5cm: . An o7ide mask with the necessary pattern for buried layer diffusion is prepared. This is

followed by masking and etching the o7ide in the buried layer mask.

The =-type buried layer is now diffused into the substrate. A slow-diffusing material such

as arsenic or antimony us used$ so that the buried layer will stay-put during subse0uent diffusions.

The ;unction depth is typically a few microns$ with sheet resistivity of around 69I per s0uare.

Then$ an epita7ial layer of lightly doped =-silicon is grown on the P-type substrate by

placing the wafer in the furnace at +6999 C and introducing a gas containing phosphorus donor

impurityB. The resulting structure is shown in figure.

The subse0uent diffusions are done in this epita7ial layer. All active and passive

components are formed on the thin =-layer epita7ial layer grown over the P-type substrate.,btaining an epita7ial layer of the proper thickness and doping with high crystal 0uality is perhaps

the most formidable challenge in bipolar device processing.

26 O7+*)%+$:

8

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As shown in figure$ a thin layer of silicon dio7ide i, 6B is grown over the =-type layer by

e7posing the silicon wafer to an o7ygen atmosphere at about +9999 C.

36 P%1+%'():

The prime use of photolithography in C manufacturing is to selectively etch or remove the

i,6 layer. As shown in figure$ the surface of the o7ide is first covered with a thin uniform layer of

photosensitive emulsion Photo resistB. The mask$ a black and white negative of the re0uied

pattern$ is placed over the structure. >hen e7posed to ultraviolet light$ the photo resist under the

transparent region of the mask becomes poly-meri4ed. The mask is then removed and the wafer is

treated chemically that removes the une7posed portions of the photoresist film. The polymeri4ed

region is cured so that it becomes resistant to corrosion. Then the chip is dipped in an etching

solution of hydrofluoric acid which removes the o7ide layer not protected by the polymeri4ed

?

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photoresist. This creates openings in the i,6 layer through which P-type or =-type impurities can

be diffused using the isolation diffusion process as shown in figure. After diffusion of impurities$

the polymeri4ed photoresist is removed with sulphuric acid and by a mechanical abrasion process.

46 I!1)%+$ D+!+$:

The integrated circuit contains many devices. ince a number of devices are to be

fabricated on the same C chip$ it becomes necessary to provide good isolation between various

components and their interconnections.

The most important techni0ues for isolation areE

+. P= ;unction solation

6. Dielectric solation

n P= ;unction isolation techni0ue$ the PF type impurities are selectively diffused into the =-type

epita7ial layer so that it touches the P-type substrate at the bottom. This method generated =-type

isolation regions surrounded by P-type moats. f the P-substrate is held at the most negative

potential$ the diodes will become reverse-biased$ thus providing isolation between these islands.

The individual components are fabricated inside these islands. This method is very economical$

and is the most commonly used isolation method for general purpose integrated circuits.

n dielectric isolation method$ a layer of solid dielectric such as silicon dio7ide or ruby surrounds

each component and this dielectric provides isolation. The isolation is both physical and electrical.

This method is very e7pensive due to additional processing steps needed and this is mostly used

for fabricating CHs re0uired for special application in military and aerospace.

The P= ;unction isolation diffusion method is shown in figure. The process take place in a furnace

using boron source. The diffusion depth must be atleast e0ual to the epita7ial thickness in order to

obtain complete isolation. Poor isolation results in device failures as all transistors might get

shorted together. The =-type island shown in figure forms the collector region of the =P=

transistor. The heavily doped P-type regions marked PF are the isolation regions for the active and

passive components that will be formed in the various =-type islands of the epita7ial layer.

5 B)!& *+!+$:

ormation of the base is a critical step in the construction of a bipolar transistor. The base must be

aligned$ so that$ during diffusion$ it does not come into contact with either the isolation region or

the buried layer. re0uently$ the base diffusion step is also used in parallel to fabricate diffused

resistors for the circuit. The value of these resistors depends on the diffusion conditions and the

+9

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width of the opening made during etching. The base width influences the transistor parameters

very strongly. Therefore$ the base ;unction depth and resistivity must be tightly controlled. The

base sheet resistivity should be fairly high 699- 199I per s0uareB so that the base does not in;ect

carriers into the emitter. or =P= transistor$ the base is diffused in a furnace using a boron source.

The diffusion process is done in two steps$ pre deposition of dopants at ?999 Cand driving them in

at about +6999 C. The drive-in is done in an o7idi4ing ambience$ so that o7ide is grown over the

base region for subse0uent fabrication steps. igure shows that P-type base region of the transistor

diffused in the =-type island collector regionB using photolithography and isolation diffusion

processes.

6 E;+%%&( D+!+$:

/mitter Diffusion is the final step in the fabrication of the transistor. The emitter opening must lie

wholly within the base. /mitter masking not only opens windows for the emitter$ but also for the

contact point$ which provides a low resistivity ohmic contact path for the emitter terminal.

The emitter diffusion is normally a heavy =-type diffusion$ producing low-resistivity layer

that can in;ect charge easily into the base. A Phosphorus source is commonly used so that the

diffusion time id shortened and the previous layers do not diffuse further. The emitter is diffused

into the base$ so that the emitter ;unction depth very closely approaches the base ;unction depth.

The active base is then a P-region between these two ;unctions which can be made very narrow by

ad;usting the emitter diffusion time. %arious diffusion and drive in cycles can be used to fabricate

the emitter. The #esistivity of the emitter is usually not too critical.

The =-type emitter region of the transistor diffused into the P-type base region is shown below.

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material. ntroducing a high concentration of =F dopant caused the i lattice at the surface semi-

metallic. Thus the =F layer makes a very good ohmic contact with the Aluminium layer. This is

done by the o7idation$ photolithography and isolation diffusion processes.

86 M&%)11+>)%+$:

The C chip is now complete with the active and passive devices$ and the metal leads are to

be formed for making connections with the terminals of the devices. Aluminium is deposited over

the entire wafer by vacuum deposition. The thickness for single layer metal is +K m. "etalli4ation

is carried out by evaporating aluminium over the entire surface and then selectively etching away

aluminium to leave behind the desired interconnection and bonding pads as shown in figure.

"etalli4ation is done for making interconnection between the various components

fabricated in an C and providing bonding pads around the circumference of the C chip for later

connection of wires

.

96 P)!!+.)%+$/ A!!&;?1 )$* P),=)'+$':

"etalli4ation is followed by passivation$ in which an insulating and protective layer is

deposited over the whole device. This protects it against mechanical and chemical damage during

subse0uent processing steps. Doped or undoped silicon o7ide or silicon nitride$ or some

combination of them$ are usually chosen for passivation of layers. The layer is deposited by

chemical vapour deposition C%DB techni0ue at a temperature low enough not to harm the

metalli4ation.

T()$!+!%( F)?(+,)%+$:

P=P TransistorE

The integrated P=P transistors are fabricated in one of the following three structures.

+. ubstrate or %ertical P=P

6. Lateral or hori4ontal P=P and

:. Triple diffused P=P

ubstrate or %ertical P=PE

+6

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The P-substrate of the C is used as the collector$ the =-epita7ial layer is used as the base

and the ne7t P-diffusion is used as the emitter region of the P=P transistor. The structure of a

vertical monolithic P=P transistor + is shown in figure. The base region of an =P= transistor

structure is formed in parallel with the emitter region of the P=P transistor.

The method of fabrication has the disadvantage of having its collector held at a fi7ed

negative potential. This is due to the fact that the P-substrate of the C is always held at a negative

potential normally for providing good isolation between the circuit components and the substrate.

Triple diffused P=PE

This type of P=P transistor is formed by including an additional diffusion process over the

standard =P= transistor processing steps. This is called a triple diffusion process$ because it

involves an additional diffusion of P-region in the second =-diffusion region of a =P= transistor.

The structure of the triple diffused monolithic P=P transistor 6 is also shown in the below figure.

This has the limitations of re0uiring additional fabrication steps and sophisticated fabrication

assemblies.

L)%&()1 ( @(+>$%)1 PNP:

This is the most commonly used form of integrated P=P transistor fabrication method. This

has the advantage that it can be fabricated simultaneously with the processing steps of an =P=

transistor and therefore it re0uires as the base of the P=P transistor. During the P-type base

diffusion process of =P= transistor$ two parallel P-regions are formed which make the emitter and

collector regions of the hori4ontal P=P transistor.

Comparison of monolithic =P= and P=P transistorE

+:

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=ormally$ the =P= transistor is preferred in monolithic circuits due to the following reasonsE

+. The vertical P=P transistor must have his collector held at a fi7ed negative voltage.

6. The lateral P=P transistor has very wide base region and has the limitation due to the lateral

diffusion of P-type impurities into the =-type base region. This makes the photographic mask

making$ alignment and etching processes very difficult. This reduces the current gain of lateral

P=P transistors as low as +.1 to :9 as against 19 to :99 for a monolithic =P= transistor.

:. The collector region is formed prior to the formation of base and emitter diffusion. During the

later diffusion steps$ the collector impurities diffuse on either side of the defined collector ;unction.

ince the =-type impurities have smaller diffusion constant compared to P-type impurities the =-

type collector performs better than the P-type collector. This makes the =P= transistor preferable

for monolithic fabrication due to the easier process control.

Transistor with multiple emittersE The applications such as transistor- transistor logic TTLB

re0uire multiple emitters. The below figure shows the circuit sectional view of three =-emitter

regions diffused in three places inside the P-type base. This arrangement saves the chip area and

enhances the component density of the C.

+*

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S,%%= B)((+&( D+*&:

The metal contacts are re0uired to be ohmic and no P= ;unctions to be formed between the

metal and silicon layers. The =Fdiffusion region serves the purpose of generating ohmic contacts.

,n the other hand$ if aluminium is deposited directly on the =-type silicon$ then a metal

semiconductor diode can be said to be formed. uch a metal semiconductor diode ;unction e7hibits

the same type of %- Characteristics as that of an ordinary P= ;unction.

+1

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The cross sectional view and symbol of a chottky barrier diode as shown in figure.

Contact + shown in figure is a chottky barrier and the contact 6 is an ohmic contact. The contact

potential between the semiconductor and the metal generated a barrier for the flow of conducting

electrons from semiconductor to metal. >hen the ;unction is forward biased this barrier is lowered

and the electron flow is allowed from semiconductor to metal$ where the electrons are in large

0uantities.

The minority carriers carry the conduction current in the chottky diode whereas in the P=

;unction diode$ minority carriers carry the conduction current and it incurs an appreciable time

delay from ,= state to , state. This is due to the fact that the minority carriers stored in the

;unction have to be totally removed. This characteristic puts the chottky barrier diode at an

advantage since it e7hibits negligible time to flow the electron from =-type silicon into aluminum

almost right at the contact surface$ where they mi7 with the free electrons. The other advantage of

this diode is that it has less forward voltage appro7imately 9.*%B. Thus it can be used for

clamping and detection in high fre0uency applications and microwave integrated circuits.

S,%%= %()$!+!%(:

The cross-sectional view of a transistor employing a chottky barrier diode clampedbetween its base and collector regions is shown in figure. The e0uivalent circuit and the symbolic

representation of the chottky transistor are shown in figure. The chottky diode is formed by

allowing aluminium metalli4ation for the base lead which makes contact with the =-type collector

region also as shown in figure.

+2

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>hen the base current is increased to saturate the transistor$ the voltage at the collector C

reduces and this makes the diode Ds conduct. The base to collector voltage reduces to 9.*%$ which

is less the cut-in-voltage of a silicon base-collector ;unction. Therefore$ the transistor does not get

saturated.

M$1+%+, *+*&!:

The diode used in integrated circuits are made using transistor structures in one of the five possible

connections. The three most popular structures are shown in figure. The diode is obtained from a

transistor structure using one of the following structures.

+. The emitter-base diode$ with collector short circuited to the base.

6. The emitter-base diode with the collector open and

:. The collector !base diode$ with the emitter open-circuited.

The choice of the diode structure depends on the performance and application desired. Collector-

base diodes have higher collector-base arrays breaking rating$ and they are suitable for common-

cathode diode arrays diffused within a single isolation island. The emitter-base diffusion is very

popular for the fabrication of diodes$ provided the reverse-voltage re0uirement of the circuit does

not e7ceed the lower base-emitter breakdown voltage.

+)

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I$%&'()%&* R&!+!%(!:

A resistor in a monolithic integrated circuit is obtained by utili4ing the bulk resistivity of

the diffused volume of semiconductor region. The commonly used methods for fabricating

integrated resistors are +. Diffused 6. epita7ial :. Pinched and *. Thin film techni0ues.

D+!&* R&!+!%(:

The diffused resistor is formed in any one of the isolated regions of epita7ial layer during

base or emitter diffusion processes. This type of resistor fabrication is very economical as it runs in

parallel to the bipolar transistor fabrication. The =-type emitter diffusion and P-type base diffusion

are commonly used to reali4e the monolithic resistor.

The diffused resistor has a severe limitation in that$ only small valued resistors can be

fabricated. The surface geometry such as the length$ width and the diffused impurity profiledetermine the resistance value. The commonly used parameter for defining this resistance is called

the sheet resistance. t is defined as the resistance in ohms5s0uare offered by the diffused area.

n the monolithic resistor$ the resistance value is e7pressed by

# M #s +5w where #M resistance offered in ohmsB

#s M sheet resistance of the particular fabrication process involved in ohms5s0uareB

+8

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l M length of the diffused area and

w M width of the diffused area.

The sheet resistance of the base and emitter diffusion in 699I50uare and 6.6I5s0uare

respectively. or e7ample$ an emitter-diffused strip of 6mil wide and 69 mil long will offer a

resistance of 66I. or higher values of resistance$ the diffusion region can be formed in a 4ig-4ag

fashion resulting in larger effective length. The poly silicon layer can also be used for resistor

reali4ation.

E+%)7+)1 R&!+!%(:

The =-epita7ial layer can be used for reali4ing large resistance values. The figure shows the cross-

sectional view of the epita7ial resistor formed in the epita7ial layer between the two = F aluminium

metal contacts.

P+$,&* (&!+!%(:

The sheet resistance offered by the diffusion regions can be increased by narrowing down

its cross-sectional area. This type of resistance is normally achieved in the base region. igure

shows a pinched base diffused resistor. t can offer resistance of the order of mega ohms in a

comparatively smaller area. n the structure shown$ no current can flow in the =-type material

+?

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since the diode reali4ed at contact 6 is biased in reversed direction. ,nly very small reverse

saturation current can flow in conduction path for the current has been reduced or pinched.

Therefore$ the resistance between the contact + and 6 increases as the width narrows down and

hence it acts as a pinched resistor.

T+$ +1; (&!+!%(:

The thin film deposition techni0ue can also be used for the fabrication of monolithic

resistors. A very thin metallic film of thickness less than +Km is deposited on the silicon dio7ide

layer by vapour deposition techni0ues. =ormally$ =ichrome =iCrB is used for this process.

Desired geometry is achieved using masked etching processes to obtain suitable value of resistors.

,hmic contacts are made using aluminium metalli4ation as discussed in earlier sections.The cross-sectional view of a thin film resistor as shown in figure. heet resistances of *9

to *99I5 s0uare can be easily obtained in this method and thus 69kI to 19kI values are very

practical.

The advantages of thin film resistors are as followsE

+. They have smaller parasitic components which makes their high fre0uency behaviour

good.

6. The thin film resistor values can be very minutely controlled using laser trimming.

:. They have low temperature coefficient of resistance and this makes them more stable.

The thin film resistor can be obtained by the use of tantalum deposited over silicon dio7ide layer.

The main disadvantage of thin film resistor is that its fabrication re0uires additional processing

steps.

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CURRENT MIRROR AND CURRENT SOURCES:

C$!%)$% ,((&$% !(,&C((&$% M+(((:

A constant current source makes use of the fact that for a transistor in the active mode of

operation$ the collector current is relatively independent of the collector voltage. n the basic

circuit shown in fig +

Transistors +@6are matched as the circuit is fabricated using C technology. &ase and

emitter of +@6are tied together and thus have the same %&/. .n addition$ transistor + is

connected as a diode by shorting it s collector to base. The input current refflows through the

diode connected transistor + and thus establishes a voltage across +.

This voltage in turn appears between the base and emitter of 6.ince 6is identical to

+$ the emitter current of 6will be e0ual to emitter current of +which is appro7imately e0ual to

ref

As long as 6 is maintained in the active region $its collector current C6Mo will be

appro7imately e0ual to ref .

ince the output current o is a reflection or mirror of the reference current ref$ the circuit is

often referred to as a current mirror.

A$)1!+!:

The collector current C+ and C6 for the transistor + and 6 can be appro7imately

e7pressed as

IC t FIES eV

BE+

VT

ffffffffffff

---------

IC2t F

IES

eV

BE6

VT

fffffffffffff

------------2

rom e0uation +B@6B

66

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IC6IC+

fffffffff= e

VBE6

@VBE+

VT

ffffffffffffffffffffffffffffffffffffffffffffffff

-----------------3

ince %&/+M%&/6 we obtain

C6MC+MCM,

Also since both the transistors are identical $ + =6 = 3CL at the collector of + gives

refM C+F&+F&6

=IC+ +IC+

+

ffffffff+

IC6

6

ffffffff=IC ++

6

ffff

----------*B

solving /0 *B.

C may be e7pressed as

IC=

+ 6ffffffffffffffff

Iref------------1B

>here reffrom fig can be seen to beIref=VCC @

VBER+

ffffffffffOO

VCCR+

ffffffffff as %&/M9.)% is smallB

rom /0.1 for +,

+ 6fffffffffffffff

is almost unity and the output current 9is e0ual to the reference

current$ refwhich for a given #+ is constant. Typically ovaries by about :Q for 19 R R699.

t is possible to obtain current transfer ratio other than unity simple by controlling the area

of the emitter-base ;unction /&'B of the transistor 6 . or e7ample$ if the area of /&' of 6is *

times that of +$then

,M* Iref

The output resistance of the current source is the output resistance$r9of 6$

#9M96MVAI

O

ffffffffOM

VAIref

fffffffffS%A is the /arly voltage

The circuit however operates as a constant current source as long as 6 remains in the activeregion.

6:

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+*1)( ,((&$% !(,&:

>idlar current source which is particularly suitable for low value of currents. The circuit

differs from the basic current mirror only in the resistance #/that is included in the emitter lead of

6.t can be seen that due to #/the base-emitter voltage %&/6is les than %&/+and conse0uently

current o is smaller than C+

The ratio of collector currents C+@C6using

IC6IC+

fffffffff= e

VBE6

@VBE+

VT

ffffffffffffffffffffffffffffffffffffffffffffffff

------------

Taking natural logarithm of both sides$ we get

VBE-VBE2VT lnI

C+

IC6

ffffffffj k -------2

>riting 3%L for the emitter base loop

%&/+M%&/6F&6FC6B#/ ----------------:B

or %&/+-%&/6M+5 F+BC6#/-----------*B

rom e0n 6B@*B we obtain

+

ffff

++g

Ic6

RE

= VTln

IC+

IC6

ffffff--------------5

O(

RE= V

T

+++

ffff

d e

IC6

fffffffffffffffffffffffffffffffffflnIC+IC6

ffffff--------------

A relation between C+and the reference current ref is obtained by writing 3CL at the

collector point of +

refM C+F&+F&6

6*

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IC+ +++

ffff

+I

C6

fffffff

----------------idlar current source C6UUC+$therefore the termIC6

ffffff

may be neglected in )B

Thus Ireft IC+ +++

ffffg

C+M

++ffffffffffffffff

Iref

>here Iref=Vcc @VBE

R+

ffffffffffffffffffffffffffff

or + IC+ Iref

+1!$ ,((&$% !(,&:

The >ilson current source shown in fig

t provides an output current o$ which is very nearly e0ual to % refand also e7hibits a very

high output resistance.

A$)1!+!:

ince %&/+M%&/6C+MC6 and &+M&6M&

At nodeHbH

/:M6&FC6M6

ffff

++g

IC6 -----------+B

/:is e0ual to

/:MC:F&:MC:

+++

ffff

g

-----------6Brom /0n +B@6B we obtain

61

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IC: +++

ffff

=IC6

++6

ffff

IC:

=Io = +6

++ffffffffffffffff

g

IC6

ince C+MC6

Io = +6

++ffffffffffffffffg

IC+

At node GaH

Iref

=IC+

+IB:

= ++

+6ffffffffffffffff

Io +Ioffffff

=

6+6 +6

6

+6

ffffffffffffffffffffffffffffffffffffIo

or

Io =

6+6

6

+6 +6

ffffffffffffffffffffffffffffffffffffI

ref

whereIref=

VCC @6VBER

+

ffffffffffffffffffffffffffffffffff

The difference IO @Iref= 6

6

+6 +6

ffffffffffffffffffffffffffffffffffffI

ref is e7tremely small error for modest

values of

The output resistance of a >ilson current mirror is substantially greater t ro

6ffffff

than simple current mirror or >idlar current mirror.

C((&$% !(,&! )! A,%+.& 1)*!:

The current source can be used as an active load in both analog and digital CHs. The active

load reali4ed using current source in place of the passive load i.e. a resistorB in the collector arm

of differential amplifier makes it possible to achieve high voltage gain without re0uiring large

power supply voltage. The active load so achieved is basically r9 of a P=P transistor.

V1%)'& S(,&!:

A voltage source is a circuit that produces an output voltage %9 $ which is independent of

the load driven by the voltage source$ or the output current supplied to the load. The voltage source

is the circuit dual of the constant current source.

A number of C applications re0uire a voltage reference point with very low ac impedance

and a stable dc voltage that is not affected by power supply and temperature variations. There are

two methods which can be used to produce a voltage source$ namely$

62

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+. using the impedance transforming properties of the transistor$ which in turn determines the

current gain of the transistor and

6. using an amplifier with negative feedback.

V1%)'& !(,& ,+(,+% !+$' I;&*)$,& %()$!(;)%+$:

The voltage source circuit using the impedance transforming property of the transistor is

shown in figure. The source voltage % s drives the base of the transistor through a series resistance

# and the output is taken across the emitter. rom the circuit$ the output ac resistance looking into

emitter is given by

dV9

dI9

fffffffffffff=R

9=

RS ++ffffffffffffffff

+reb

with values as high as+99for, RSis transfored to a value ofRS

++ffffffffffffffff

t is to be noted that$ e0n is applicable only for small changes in the output current. The

load regulation parameter indicates the changes in %9 resulting from large changes in output

current 9 $ #eduction in %9 occurs as 9 goes from no-load current to full-load current and this

factor determines the output impedance of the voltage sources.

6)

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E;+%%&( 11&( ( C;;$ C11&,%( T& V1%)'& !(, &:

The figure shows an emitter follower or common collector type voltage source. This voltage

source is suitable for the differential gain stage used in op-amps. This circuit has the advantages of

+. Producing low ac impedance and6. resulting in effective decoupling of ad;acent gain stages.

The low output impedance of the common-collector stage simulates a low impedance voltage

source with an output voltage level of %9 represented by

V9 =VccR6

R+

+R6

ffffffffffffffffffffffj k

The diode D+ is used for offsetting the effect of dc value %&/ $ across the /-& ;unction of the

transistor$ and for compensating the temperature dependence of %&/ drop of +. The load VL shown

in dotted line represents the circuit biased by the current through +.

The impedance #9 looking into the emitter of + derived from the hybrid W model is given by

R9 =V

T

I+

fffffffff+

R+R

6

R+ +R6

b cffffffffffffffffffffffffffffffff

V1%)'& S(,& !+$' T&;&()%(& ,;&$!)%&* A.)1)$,& D+*&:

The voltage source using common collector stage has the limitations of its vulnerability for

changes in bias voltage %= and the output voltage %9 with respect to changes in supply voltage

%cc. This is overcome in the voltage source circuit using the breakdown voltage of the base-

emitter ;unction shown below.

68

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The emitter ! follower stage of common ! collector is eliminated in this circuit$ since the

impedance seen looking into the bias terminal = is very low. The current source + is normally

simulated by a resistor connected between %cc and node n. Then$ the output voltage level % 9 at

node = is given by

%9 M %& F%&/

>here %& is the breakdown voltage of diode D& and %&/ is the diode drop across D+. The

breakdown diode D& is normally reali4ed using the base-emitter ;unction of the transistor. The

diode D+provides partial compensation for the positive temperature coefficient effect of %&. n a

monolithic C structure$ D& and D+ can be conveniently reali4ed as a single transistor with two

individual emitters as shown in figure.

T&;&()%(& C;&$!)%&* ).)1)$,& *+*& V1%)'& !(,& !+$'

?(&)=*$ .1%)'& %&

?)!&- &;+%%&( $,%+$

The structure consists of composite connection of two transistors which are diode-

connected back-to back. ince the transistors have their base to collector terminals common$ they

can be designed as a single transistor with two emitters.

The output resistance #9 looking into the output terminal in figure is given by

6?

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R9 =RB+V

T

I+

fffffffff>here #& and %T 5+ are the ac resistances of the base !emitter resistance of diode

D& and D+ respectively. Typically #& is in the range of *9I to +99I$ and %9 in the range of 2.1% to

?%.

V1%)'& S(,& !+$' VBE )! ) (&&(&$,&:

The output stage of op-amp re0uires stabili4ed bias voltage source$ which can be obtained using a

forward-biased diode connected transistor.

The forward voltage drop for such a connection is appro7imately 9.)%$ and it changes slightly with

current. >hen a voltage level greater than 9.)%$ is needed$ several diodes can be connected in

series$ which can offer integral multiples of 9.)%. Alternatively$ the figure shows a multiplier

circuit$ which can offer voltage levels$ that need not be integral multiplied of 9.)%. The drop

across #6 e0uals %&/ drop of +. Considering negligible base current for + $ current through #6 is

the same as that flowing through #+ . Therefore$ the output voltage %9 can be e7pressed as

V9 =I6 R+ +R6

b c=

VBER6

ffffffffffffR+ +R6

b c=VBE

R+R6

fffffff+ +j k

VBE ;1%+1+&( C+(,+%

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R9

=dV

9

dIo

ffffffffffffft R

++R

6

++ gR6

fffffffffffffffffffffffffffff

when gR6PP +, we have R9 =R

++R

6

R6

ffffffffffffffffffffffA+

g

fffffff

!sing this e"n we have,

V9V

BE

ffffffffffff=

R+ +R6R

6

ffffffffffffffffffffff

Therefore,

R9 = V

9

VBE

ffffffffffff +

g

ffffffff=

V9

VBE

ffffffffffffV+I

C

fffffff

V1%)'& R&&(&$,&!:

The circuit that is primarily designed for providing a constant voltage independent of

changes in temperature is called a voltage reference. The most important characteristic of a voltage

reference is the temperature coefficient of the output reference voltage TC# $ and it is e7pressed as

TCR=dVRdT

ffffffffff

The desirable properties of a voltage reference areE

+. #eference voltage must be independent of any temperature change.

6. #eference voltage must have good power supply re;ection which is as independent of the

supply voltage as possible and

:. output voltage must be as independent of the loading of output current as possible$ or in

other words$ the circuit should have low output impedance.

The voltage reference circuit is used to bias the voltage source circuit$ and the combination can

be called as the voltage regulator. The basic design strategy is producing a 4ero TC# at a given

temperature$ and thereby achieving good thermal ability. Temperature stability of the order of

+99ppm59 C is typically e7pected.

:+

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V1%)'& R&&(&$,& ,+(,+% !+$' %&;&()%(& ,;&$!)%+$ !,&;&:

The voltage reference circuit using basic temperature compensation scheme is shown

below. This design utili4es the close thermal coupling achievable among the monolithic

components and this techni0ue compensates the known thermal drifts by introducing an opposing

and compensating drift source of e0ual magnitude.

:6

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A constant current is supplied to the avalanche diode D& and it provides a bias voltage of

%& to the base of +. The temperature dependence of the %&/ drop across + and those across D+ and

D6 results in respective temperature coefficients.

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igure depicts a current reference circuit using avalanche diode reference. The base bias for

transistor + is provided through register #+ and it also provides the dc current needed to bias D&$ D+

and D6 .

The voltage at the base of + is e0ual to the 4ener voltage %& added with two diode drops

due to D+ and D6 . The voltage across #6 is e0ual to the voltage at the base of + less the sum of the

base ! emitter voltages of + and 6 .

:*

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:. closely matched components.

The above figure shows the basic block diagram of a differential amplifier$ with two input

terminals and one output terminal. The output signal of the differential amplifier is proportional to

the difference between the two input signals.

That is %9 M Adm %+! %6 B

f %+ M %6 $ then the output voltage is 4ero. A non-4ero output voltage % 9 is obtained when %+ and

%6 are not e0ual. The difference mode input voltage is defined as % m M%+! %6 and the common

mode input voltage is defined as

Vc=V+ +V6

6ffffffffffffffff

These e0uation show that if %+ M %6 $ then the differential mode input signal is 4ero and common

mode input signal is %cm M %+ M%6 .

D+&(&$%+)1 A;1++&( +% A,%+.& 1)*:

Differential amplifier are designed with active loads to increase the differential mode

voltage gain.

The open circuit voltage gain of an op-amp is needed to be as large as possible. This is achieved by

cascading the gain stages which increase the phase shift and the amplifier also becomes vulnerable

to oscillations. The gain can be increased by using large values of collector resistance. or such a

circuit$ the voltage gain is given byA

d =@g R

C=

ICRC

VT

ffffffffffff

To increase the gain the C #Cproduct must be made very large.

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6. for large #C$ the 0uiescent drop across the resistor increase and a large power supply will be

re0uired to maintain a given operating current.

:. Large monolithic resistor introduces large parasitic capacitances which limits the fre0uency

response of the amplifier.

*. for linear operation of the differential pair$ the devices should not be allowed to enter into

saturation. This limits the ma7 input voltage that can be applied to the bases of transistors

+ and 6 the base-collector ;unction must be allowed to become forward-biased by more

than 9.1 %. The large value of load resistance produces a large dc voltage drop // 5 6B#C$

so that the collector voltage will be %C M %cc -// 5 6B#C and it will be substantially less

than the supply voltage %cc. This will reduce the input voltage range of the differential

amplifier. Due to the reasons cited above$ an active load is preferred in the differential

amplifier configurations.

BJT D+&(&$%+)1 A;1++&( !+$' ),%+.& 1)*!:

A simple active load circuit for a differential amplifier is the current mirror active load as

shown in figure. The active load comprises of transistors : and * with the transistor : connected

as a diode with its base and collector shorted. The circuit is shown to drive a load #L. >hen an ac

input voltage is applied to the differential amplifier$ the various currents of the circuit are given by

IC*=IC:=IC+ =g Vid

6fffffffffffffff . >here IC*=IC:due to current mirror action. e know that the load current L entering the ne7t stage is I%=IC6 @IC*

.Therefore$ I%= @gVid

6

ffffffffffffffff@

gVid6

ffffffffffffffff=@gVid. Then$ the output voltage from the differential

amplifier is given by V9=@I% R% =@ @gVid R%=g R% Vid. The ac voltage gain of

the circuit is given by AV=V9Vid

ffffffff=

g R% VidVid

ffffffffffffffffffffffff=g R% .The differential amplifier can amplify

the differential input signals and it provides single-ended output with a ground reference since the

load #Lis connected to only one output terminal. This is made possible by the use of the current

:)

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mirror active load.The output resistance #9of the circuit is that offered by the parallel combination

of transistors 6=P=B and *P=PB. t is given by #rM r96YY r9*

:8

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A$)1!+! BJT *+&(&$%+)1 );1++&( +% ),%+.& 1)*:

:?

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AssuingVid6

ffffffff= 9for transistor #+ and#6 and = 1 , then the bias current IEE

is divided e"uall& between #+ and#6and

hence, IC+ =IC6=IEE6

ffffffffffAThe current IC+su''lied b& #:is

irrored as IC*at the out'ut of transitor #*A

therefore, IC:=IC*=IEEand the dc current in the collector of #*is e(actl&

the current needed to satisf 6A

when is ver& large andVEC*=VEC: =VBE , the current irror ratio becoes e(actl&

unit& AThen , the differential a'lifier is co'letl& balanced , and the out'ut voltage

isV9=VCC@VBE# @'ointsEThe collector currents of all the transitors are e"ualA

that is, IC+

=IC6

=IC:

=IC*

=IEE

6

ffffffffA

The Collector@eitter voltages of#+ and#6are given b&

VCE+ =VCE6=VC @VE= VCC@VEB @ @VEB =VCC

The collector eitter voltages of #:and #

*are given b&,

VCE: =VCE*=VEBThe in'ut offset voltagesVOSof the differential a'lifier arises fro the isatches

in the in'ut devices #+, #

6and load drives #

:, #

*and fro the base current of the

%oad devices Aan a''ro(iaate e('ression forVOS is given b&

VOS=VTIS)IS)

ffffffffffff@

IS*IS*

fffffffffffff+6

ffff

f g

where re'resents the gain of )*) transistor and it is assued that

IS)=IS: @IS*

IS) =IS:+IS*

6

ffffffffffffffffffff

IS*

=IS+

@IS6

and

IS*=IS+ +IS6

6

ffffffffffffffffffff

assuing a worst case value ofF *QforIs

Is

fffffffffandof69,

*9

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VOS=VT 9.9*+ 9.9*+ 9.+ = 62B +9@: B 9.+8= *.28VA

E"n shows that, the offset is higher than that of a resistive loaded differential a'lifier

This can be reduced b& the use of eitter resistors

for#:and #*, and a transitor # 1in the current irror

load as shown in figure A

CMRR %& *+&(&$%+)1 );1++&( !+$' ),%+.& 1)*:

The differential amplifier using active load provides high voltage gain to the differential

input signal and a single ! ended output that is referenced to the ground is obtained. The

differential amplifier which provides conversion for a differential signal to a single ended signal is

necessary in differential input signal ended output amplifiers. The op-amp is one such circuit. The

changes in the common-mode signal of the bias current source. This induces a change in C6 and an

identical change in C+. The change in C+ will then produce a change in the P=P load devices$ andthereby a change in C*$ which is the collector current *$ The current C* is in such a direction as to

cancel the change in C6. As a result of this$ any common mode input does not cause a change in

output.

*+

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The voltage gain of the differential amplifier is independent of the 0uiescent current //.

This makes it possible to use very small value of // as low as 69Ka$ while still maintaining a large

voltage gain. mall value of // is preferred$ since it results in a small value of bias current and a

large value for the input resistance. A limitation in choosing a small // is$ however$ the fact that$ it

will result in a poor fre0uency response of the amplifier.

>hen a small value of bias current is re0uired$ the best approach is to use a '/T or

",/T differential amplifier that is operated at comparatively higher values of //.

*6

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D+&(&$%+)1 M*& !+'$)1 )$)1!+!:

The ac analysis of the differential amplifier can be made using the circuit model as shown

below. The differential input transistor pair produces e0ual and opposite currents whose amplitude

us given by gm6 %id 56 at the collector of + and 6 . The collector current ic+ is fed by the transistor

: and it is mirrored at the output of *. Therefore$ the total current i9 flowing through the load

resistor #L is given by

i9=6

g6

Vid

6

ffffffffffffffffff=g6 V id

Then the out'ut voltage isV

9=i

9R

% = g

6R

%

b cV

id

and the differential ode gain A ddof the differential a'lifier is given b&

Add =v9

Vd

ffffffffff=g6 R%

This current mirror provides a single ended output which has a voltage e0ual to the

ma7imum gain of the common emitter amplifier.

*:

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The power of the current mirror can be increased by including additional common collector stages

at the o5p of the differential input stage. A bipolar differential amplifier structure with additional

stages is shown in figure. The resistance at the output of the differential stage is now given by the

parallel combination of transistors 6 and * and the input resistance is offered by 1. Then$ the

e0uivalent resistance is e7pressed by #e0 M ro6YY r9* YY ri1M ri1 . The gain of the differential stage then

becomes Ad =g6R e" =g6ri1 = 91IC6IC1

fffff.

**

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B+1)( *+&(&$%+)1 );1++&( +% ,;;$ ;*& +$% !+'$)1!:

The common mode input signal induces a common mode current iic in each of the differential

transistor pair + and 6 . The common current iic is given by

iic = g6

++ 6g6REE

fffffffffffffffffffffffffffffffVic

Vic6REE

ffffffffffff

The current flow through the transistor + is supplied by the reference current of transistor :. This

current is replicated or mirrored in the transistor * and it produces e7actly the same current

needed at the collector of 6. Therefore$ the output current and hence the output voltage and

common mode conversion gain Acd are all 4ero.

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G&$&()1 O&()%+$)1 A;1++&(:

An operational amplifier generally consists of three stages$ anmely$+. a differential

amplifier 6. additional amplifier stages to provide the re0uired voltage gain and dc level shifting :.

an emitter-follower or source follower output stage to provide current gain and low output

resistance.

A low-fre0uency or dc gain of appro7imately +9* is desired for a general purpose op-amp

and hence$ the use of active load is preferred in the internal circuitry of op-amp. The output voltage

is re0uired to be at ground$ when the differential input voltages is 4ero$ and this necessitates the

use of dual polarity supply voltage. ince the output resistance of op-amp is re0uired to be low$ a

complementary push-pull emitter ! follower or source follower output stage is employed.

"oreover$ as the input bias currents are to be very small of the order of picoamperes$ an /T input

stage is normally preferred. The figure shows a general op-amp circuit using '/T input devices.

*2

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I$% !%)'&:

The input differential amplifier stage uses p-channel '/Ts "+ and "6. t employs a three-transistor

active load formed by : $ * $ and 1 . the bias current for the stage is provided by a two-transistor

current source using P=P transistors 2 and ). #esistor #+ increases the output resistance seen

looking into the collector of * as indicated by #9*. This is necessary to provide bias current

stability against the transistor parameter variations. #esistor #6 establishes a definite bias current

through 1 . A single ended output is taken out at the collector of * .

",/THs are used in place of '/Ts with additional devices in the circuit to prevent any damage

for the gate o7ide due to electrostatic discharges.

G)+$ !%)'&:

The second stage or the gain stage uses Darlington transistor pair formed by 8 and ? as shown in

figure. The transistor 8 is connected as an emitter follower$ providing large input resistance.

*)

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Therefore$ it minimi4es the loading effect on the input differential amplifier stage. The transistor

?provides an additional gain and +9 acts as an active load for this stage. The current mirror

formed by ) and +9 establishes the bias current for ? . The %&/ drop across ? and drop across #1

constitute the voltage drop across #* $ and this voltage sets the current through 8 . t can be set to a

small value$ such that the base current of 8 also is very less.

O%% !%)'&:

The final stage of the op-amp is a class A& complementary push-pull output stage. ++ is an emitter

follower$ providing a large input resistance for minimi4ing the loading effects on the gain stage.

&ias current for ++ is provided by the current mirror formed by ) and +6$ through +: and +* for

minimi4ing the cross over distortion. Transistors can also be used in place of the two diodes.

The overall voltage gain A% of the op-amp is the product of voltage gain of each stage as given by

A% M YAd Y YA6YYA:Y

>here Ad is the gain of the differential amplifier stage$ A 6 is the gain of the second gain stage and

A: is the gain of the output stage.

IC

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reference bias current #/ also provides mirrored and proportional current at the collector of the

double !collector lateral P=P transistor +:. The transistor +: and +6 thus form a two-output

current mirror with +:Aproviding bias current for output stage and +:&providing bias current for

+). The transistor +8 and +?provide dc bias for the output stage. ormed by +* and 69 and they

establish two %&/ drops of potential difference between the bases of +* and +8 .

I$% !%)'&:

The input differential amplifier stage consists of transistors + through ) with biasing provided by

8 through +6. The transistor + and 6form emitter ! followers contributing to high differential

input resistance$ and whose output currents are inputs to the common base amplifier using :and

*which offers a large voltage gain.

The transistors 1$ 2 and ) along with resistors #+$ #6 and #: from the active load for input

stage. The single-ended output is available at the collector of 2. the two null terminals in the input

stage facilitate the null ad;ustment. The lateral P=P transistors : and * provide additional

protection against voltage breakdown conditions. The emitter-base ;unction : and * have higher

emitter-base breakdown voltages of about 19%. Therefore$ placing P=P transistors in series with

=P= transistors provide protection against accidental shorting of supply to the input terminals.

G)+$ S%)'&:

The econd or the gain stage consists of transistors +2 and +)$ with +2 acting as an emitter !

follower for achieving high input resistance. The transistor +) operates in common emitter

configuration with its collector voltage applied as input to the output stage. Level shifting is done

for this signal at this stage.

nternal compensation through "iller compensation techni0ue is achieved using the feedback

capacitor C+ connected between the output and input terminals of the gain stage.

O%% !%)'&:

The output stage is a class A& circuit consisting of complementary emitter follower transistor pair

+* and 69 .

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gain stage. t is biased by transistor +:A which also drives +8 and +?$ that are used for establishing

a 0uiescent bias current in the output transistors +* and 69.

I*&)1 -); ,)(),%&(+!%+,!:

+. nfinite voltage gain A.

6. nfinite input resistance #i$ so that almost any signal source can drive it and there is no

loading of the proceeding stage.

:. Vero output resistance #o$ so that the output can drive an infinite number of other devices.

*. Vero output voltage$ when input voltage is 4ero.

1. nfinite bandwidth$ so that any fre0uency signals from o to [

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There is one pole due to #9 C and one -69d&5decade. The open loop voltage gain of an op-amp

with only one corner fre0uency is obtained from above fig.

V9= @+C

R9 @+C

ffffffffffffffffffffffffA

O%Vd @@@@ 62

` a

or A =V9Vd

fffffff=

AO%

++ 6+ + R9C

b c

or A = A

O%

++ + f

f+

fffffffff g

fffffffffffffffffffffffffffffff @@@@@ 6)` a

where f +

= +

6R9C

fffffffffffffffffffffff @@@ 68` a

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

f+ is the corner fre0uency or the upper : d& fre0uency of the op-amp. The magnitude and phase

angle of the open loop volt gain are fu of fre0uency can be written as$

A

L

L

M

M=

AO%

++ f

f+

ffffffff g6vuu

ut

wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww

ffffffffffffffffffffffffffffff

@@@@@@@ 6?

` a

=@tan@+ f

f+

ffffff

h

j

i

k

The magnitude and phase angle characteristics from e0n 6?B and :9B

+. or fre0uency fUU f+ the magnitude of the gain is 69 log A,L in d&.

6. At fre0uency f M f+ the gain in : d& down from the dc value of A,L in d&. This fre0uency f+

is called corner fre0uency.

:. or f f + the fain roll-off at the rate off -69d&5decade or -2d&5decade.

1+

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rom the phase characteristics that the phase angle is 4ero at fre0uency f M9.

At the corner fre0uency f+ the phase angle is -*19 lagging and a infinite fre0uency the phase angle

is -?99 . t shows that a ma7imum of ?99phase change can occur in an op-amp with a single

capacitor C. Vero fre0uency is taken as te decade below the corner fre0uency and infinite

fre0uency is one decade above the corner fre0uency. The voltage transfer in a -domain can be

written as

A = AO%

+++ f

f+

ffffffff g

fffffffffffffffffffffffff=

AO%

+++ w

w+

fffffffd e

fffffffffffffffffffffff

A =AO% @w++w+ w+

fffffffffffffffffffff=

AO% A-+S+ -+

ffffffffffffffffffff

The transfer f9 of as op-amp with : break fre0uency can be assumed as$

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A= AO%

+++ f

f+

ffffffff g

+++ f

f6

fffffffff g

+++ f

f:

fffffffff g

fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff9Uf

+Uf

6Uf

: @@@@ :+

` a

A=

AO%w+ w6w:

s+ w+` a

s+ w6` a

s+ w:` a

fffffffffffffffffffffffffffffffffffffffffffffffffffffffff

@@@ :6

` a

with9Uw+ Uw6Uw:

C+(,+% S%)?+1+%:

A circuit or a group of circuit connected together as a system is said to be stable$ if its

o5p reaches a fi7ed value in a finite time. orB A system is said to be unstable$ if its o5p increases

with time instead of achieving a fi7ed value. n fact the o5p of an unstable sys keeps on increasing

until the system break down. The unstable system are impractical and need be made stable. The

criterian gn for stability is used when the system is to be tested practically. n theoretically$ always

used to test system for stability $ e7E &ode plots.

&ode plots are compared of magnitude %s re0uency and phase angle %s fre0uency. Any system

whose stability is to be determined can represented by the block diagram.

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The block between the output and input is referred to as forward block and the block between the

output signal and f5b signal is referred to as feedback block. The content of each block is referred

\Transfer fre0uencyH rom fig we represented it by A,L fB which is given by

A,L fB M %9 5%in if %f M 9. -----+B

where A,L fB M open loop volt gain. The closed loop gain Af is given by

A M %9 5%in

A M A,L 5 +FA,L B &B ----6B

& M gain of feedback circuit.

& is a constant if the feedback circuit uses only resistive components. ,nce the magnitude %s

fre0uency and phase angle %s fre0uency plots are drawn$ system stability may be determined as

follows6 M&%*::

Determine the phase angle when the magnitude of A,L B &B is 9d& orB +. f phase angle is .-

+899 $ the system is stable.

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or )*+ C$ the ma7imum internal capacitor charging current is limited to about +1KA. o the slew

rate of )*+ C is

# M d%c5dt Yma7 M ma75C .

or a sine wave input$ the effect of slew rate can be calculated as consider volt follower - The

input is large amp$ high fre0uency sine wave .

f %s M %m inwt then output %9M %m sinwt . The rate of change of output is given by

d%95dt M %m w coswt.

The ma7 rate of change of output across when coswt M+

i.eB # M d%95dt Yma7 M w%m.

# M 6]f%m %5s M 6]f%m v5ms.

Thus the ma7imum fre0uency fma7 at which we can obtain an undistorted output volt of peak

value %m is given by

fma7

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called the full power response. t is ma7imum fre0uency of a large amplitude sine wave with

which op-amp can have without distortion.

DC C)(),%&(+!%+,! -);:

Current is taken from the source into the op-amp inputs respond differently to current andvoltage due to mismatch in transistor.

DC output voltages are$

+. nput bias current

6. nput offset current

:. nput offset voltage

*. Thermal drift

I$% ?+)! ,((&$%:The op-ampHs input is differential amplifier$ which may be made of &'T or /T.

n an ideal op-amp$ we assumed that no current is drawn from the input terminals.

The base currents entering into the inverting and non-inverting terminals &- @ &

F

respectivelyB.

/ven though both the transistors are identical$ &- and &

F are not e7actly e0ual due to

internal imbalance between the two inputs.

"anufacturers specify the input bias current &

o$ I B =I B

+

+ I B@

6fffffffffffffffffffffffQ +

` a

f input voltage %iM 9%. The output %oltage %oshould also be %oM 9B &M 199nA

>e find that the output voltage is offset by$

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Vo= I B@

Rf

Q 6a

,p-amp with a +" feedback resistor

%oM 1999nA ^ +" M 199m%

The output is driven to 199m% with 4ero input$ because of the bias currents.

n application where the signal levels are measured in m%$ this is totally unacceptable. This can be

compensated. >here a compensation resistor #comphas been added between the non-inverting input

terminal and ground as shown in the figure below.

Current &Fflowing through the compensating resistor #comp$ then by 3%L we get$

-%+F9F%6-%oM 9 orB

%oM %6! %+ __:B

&y selecting proper value of #comp$ %6can be cancelled with %+and the %oM 9. The value of #comp

is derived a

%+M &F#comp orB

&FM %+5#comp __*B

The node GaH is at voltage -%+B. &ecause the voltage at the non-inverting input terminal is -% +B.

o with %iM 9 we get$

+M %+5#+ __1B

6M %65#f __2B

or compensation$ %oshould e0ual to 4ero %oM 9$ %iM 9B. i.e. from e0uation :B %6M %+. o that$

6M %+5#f __)B

3CL at node GaH gives$

&-M 6F +

1)

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I B@

=V+R

f

ffffffff+

V+R +

fffffff

I B@= V

+

R++ R

f

R +R f

ffffffffffffffffffffffffffffffQ 8

` a

Assume &-M &

Fand using e0uation *B @ 8B we get

V+

R++ Rf

R+Rf

ffffffffffffffffffffffffffffff=

V+R co'

fffffffffffff

R co' =R +Rf

R + + Rf

ffffffffffffffffffffff

#compM #+ YY #f ___?B

i.e. to compensate for bias current$ the compensating resistor$ #compshould be e0ual to the parallel

combination of resistor #+and #f.

I$% !&% ,((&$%:

&ias current compensation will work if both bias currents &Fand &

-are e0ual.

ince the input transistor cannot be made identical. There will always be some small

difference between &Fand &

-. This difference is called the offset current

YosY M &F-&

- __+9B

,ffset current osfor &'T op-amp is 699nA and for /T op-amp is +9pA. /ven with bias current

compensation$ offset current will produce an output voltage when %i M 9.

%+M &F #comp __++B

And +M %+5#+ __+6B3CL at node GaH gives$

6M &_+B

I 6 =I B@

@ I B+ R co'

R+

ffffffffffffffj k Q +:` a

Again%9M 6 #f! %+%oM 6#f- &

F#comp

Vo= I B@

@I B+ R co'

R +

ffffffffffffffJ KRf@I B

+R co' Q +*

` a

ubstitute e0uation ?B and after algebraic manipulation $

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I$% !&% .1%)'&:

nspite of the use of the above compensating techni0ues$ it is found that the output voltage

may still not be 4ero with 4ero input voltage S% o 9 with %iM 9. This is due to unavoidable

imbalances inside the op-amp and one may have to apply a small voltage at the input terminal to

make output %oB M 9.

This voltage is called input offset voltage % os. This is the voltage re0uired to be applied at

the input for making output voltage to 4ero %oM 9B.

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Let us determine the %oson the output of inverting and non-inverting amplifier. f % iM 9 ig bB

and cBB become the same as in figure dB. The voltage %6at the negative input terminal is given by

V6=

R+

R + + R f

fffffffffffffffffffffffj kV o Q

69` a

orB

Vo =R+ + R f

R+

fffffffffffffffffffffffj k V6 = + +R

f

R+

ffffffffj k V6 Q 6+` a

ince$ Vos = Vi @V6LL

MM@V i = 9

V os = 9 @V 6LL

MM=V 6 Q 66

aor

a

V o = + +R

f

R +

ffffffffj k V os Q 6:` a

Thus$ the output offset voltage of an op-amp in closed loop is given by e0uation 6:B.

T%)1 %% !&% .1%)'&:

The total output offset voltage %,Tcould be either more or less than the offset voltage

produced at the output due to input bias current &B or input offset voltage alone%osB.

This is because & and %os could be either positive or negative with respect to ground.

Therefore the ma7imum offset voltage at the output of an inverting and non-inverting amplifier

figure b$ cB without any compensation techni0ue used is given by many op-amp provide offsetcompensation pins to nullify the offset voltage.

+93 potentiometer is placed across offset null pins +@1. The wipes connected to the

negative supply at pin *.

The position of the wipes is ad;usted to nullify the offset voltage.

2+

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>hen the given belowB op-amps does not have these offset null pins$ e7ternal balancing

techni0ues are used.

VOT= + +R

f

R +

ffffffffJ KVos + Rf I B Q 6*` a

>ith #comp$ the total output offset voltage

VOT= + +R

f

R +

ffffffffJ KVos+ Rf Ios Q 61` a

B)1)$,+$' ,+(,+%:

I$.&(%+$' );1++&(:

N$-+$.&(%+$' );1++&(:

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T&(;)1 *(+%:

&ias current$ offset current$ and offset voltage change with temperature.

A circuit carefully nulled at 61C may not remain. o when the temperature rises to :1C.

This is called drift.

,ffset current drift is e7pressed in nA5C.

These indicate the change in offset for each degree Celsius change in temperature.

O&$ 1 -); C$+'()%+$:

The term open-loop indicates that no feedback in any form is fed to the input from the output.

>hen connected in open ! loop$ the op-amp functions as a very high gain amplifier. There are

three open ! loop configurations of op-amp namely$+. differential amplifier

6. nverting amplifier

:. =on-inverting amplifier

The above classification is made based on the number of inputs used and the terminal to which

the input is applied. The op-amp amplifies both ac and dc input signals. Thus$ the input signals can

be either ac or dc voltage.

O&$ 1 D+&(&$%+)1 A;1++&(:

n this configuration$ the inputs are applied to both the inverting and the non-inverting

input terminals of the op-amp and it amplifies the difference between the two input voltages.

igure shows the open-loop differential amplifier configuration.

The input voltages are represented by %i+ and %i6. The source resistance #i+ and #i6 are

negligibly small in comparison with the very high input resistance offered by the op-amp$ and thus

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the voltage drop across these source resistances is assumed to be 4ero. The output voltage % 9 is

given by

%9 M A%i+! %i6 B

where A is the large signal voltage gain. Thus the output voltage is e0ual to the voltage gain A

times the difference between the two input voltages. This is the reason why this configuration is

called a differential amplifier. n open ! loop configurations$ the large signal voltage gain A is also

called open-loop gain A.

I$.&(%+$' );1++&(:

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n this configuration the input signal is applied to the inverting input terminal of the op-

amp and the non-inverting input terminal is connected to the ground. igure shows the circuit of an

open ! loop inverting amplifier.

The output voltage is +899 out of phase with respect to the input and hence$ the output voltage % 9 is

given by$

%9 M -A%i

Thus$ in an inverting amplifier$ the input signal is amplified by the open-loop gain A and in phase

! shifted by +899.

N$-+$.&(%+$' A;1++&(:

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igure shows the open ! loop non- inverting amplifier. The input signal is applied to the

non-inverting input terminal of the op-amp and the inverting input terminal is connected to the

ground.

The input signal is amplified by the open ! loop gain A and the output is in-phase with input

signal.

%9M A%i

n all the above open-loop configurations$ only very small values of input voltages can be applied.

/ven for voltages levels slightly greater than 4ero$ the output is driven into saturation$ which is

observed from the ideal transfer characteristics of op-amp shown in figure. Thus$ when operated in

the open-loop configuration$ the output of the op-amp is either in negative or positive saturation$ or

switches between positive and negative saturation levels. This prevents the use of open ! loop

configuration of op-amps in linear applications.

L+;+%)%+$! O&$ 1 O ); ,$+'()%+$:irstly$ in the open ! loop configurations$ clipping of the output waveform can occur when the

output voltage e7ceeds the saturation level of op-amp. This is due to the very high open ! loop

gain of the op-amp. This feature actually makes it possible to amplify very low fre0uency signal of

the order of microvolt or even less$ and the amplification can be achieved accurately without any

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distortion.

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A virtual ground is a ground which acts like a ground . t may not have physical connection to

ground. This property of an ideal op ! amp indicates that the inverting and non ! inverting

terminals of the op !amp are at the same potential. The non ! inverting input is grounded for the

inverting amplifier circuit. This means that the inverting input of the op !amp is also at ground

potential. Therefore$ a virtual ground is a point that is at the fi7ed ground potential 9%B$ though it

is not practically connected to the actual ground or common terminal of the circuit.

The open ! loop gain of an op ! amp is e7tremely high$ typically 699$999 for a )*+. or e7$ when

the output voltage is +9%$ the input differential voltage %id is given by

Vid =V

9

A

fffffff=

+9

699$999

ffffffffffffffffffff= 9.91V

urther more$ the open ! loop input impedance of a )*+ is around 6"I. Therefore$ for an input

differential voltage of 9.91m%$ the input current is only

Ii=VidRi

ffffffff=9.91V

6.fffffffffffffffffffff

= 9.61nA

ince the input current is so small compared to all other signal currents$ it can be appro7imated as

4ero. or any input voltage applied at the inverting input$ the input differential voltage % id is

negligibly small and the input current is ideally 4ero.

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e0uals I+ =ViR

+

ffff. The current must flow through #fbecause the virtual ground accepts negligible

current. The left end of #f is ideally grounded$ and hence the output voltage appears wholly across

it. Therefore$ V9=@I6 Rf=@Rf

R+fffffffVi . The closed !loop voltage gain A% is given by

Av =V9Vi

fffffff=@

Rf

R+

ffffff.

The input impedance can be set by selecting the input resistor #+ . "oreover$ the above e0uation

shows that the gain of the inverting amplifier is set by selecting a ratio of feedback resistor #f to

the input resistor #+ . The ratio #f 5#+ can be set to any value less than or greater than unity. This

feature of the gain e0uation makes the inverting amplifier with feedback very popular and it lends

this configuration to a ma;ority of applications.

P(),%+,)1 C$!+*&()%+$!:

+. etting the input impedance #+ to be too high will pose problems for the bias current$ and it

is usually restricted to +93I.

6. The gain cannot be set very high due to the upper limit set by the fain ! bandwidth (&> M

Av J fB product. The Av is normally below +99.:. The peak output of the op ! amp is limited by the power supply voltages$ and it is about 6%

less than supply$ beyond which$ the op ! amp enters into saturation.

*. The output current may not be short ! circuit limited$ and heavy loads may damage the op

! amp. >hen short ! circuit protection is provided$ a heavy load may drastically distort the

output voltage.

P(),%+,)1 I$.&(%+$' );1++&(:

The practical inverting amplifier has finite value of input resistance and input current$ its

open voltage gain A9 is less than infinity and its output resistance #9 is not 4ero$ as against the ideal

inverting amplifier with finite input resistance$ infinite open ! loop voltage gain and 4ero output

resistance respectively.

igure shows the low fre0uency e0uivalent circuit model of a practical inverting amplifier. This

circuit can be simplified using the TheveninHs e0uivalent circuit shown in figure. The signal source

2?

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%i and the resistors #+ and #i are replaced by their TheveninHs e0uivalent values. The closed ! loop

gain A% and the input impedance #if are calculated as follows.

The input impedance of the op- amp is normally much larger than the input resistance #+.

Therefore$ we can assume %e0O %i and #e0 O #+ . rom the figure we get$

V9=IR

9+ AV id

andVid+IR f+V9= 9

Substituting the value ofVid fro above e"n , we get,

V9 ++A` a

=I R9 @ARfb c

Also using the /V% , we get

Vi =I R+ +R f

b c+V

9

Substituting the value of I derived fro above e"n and obtaining the closed

loo' gain Av, we get

Av =V

9

Vi

fffffff=

R9

@ARfR

9+R f+R+ ++A

` affffffffffffffffffffffffffffffffffffffffffffffff

t can be observed from above e0n that when A +$ #9 is negligibly small and the product A#+

#9 F#f $ the closed loop gain is given by

Av =@Rf

R+

fffff

>hich is as the same form as given in above e0n for an ideal inverter.

I$% R&!+!%)$,&:

)9

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rom figure we get$

Rif=VidI

+

ffffffff

!sing /V%, we get,

Vid+I+ R f+R9

b c

+AV id = 9

which can be si'lified for Rifas

Rif=Vif

I+

ffffffff=

R f+R9++A

fffffffffffffffffff

O%% R&!+!%)$,&:

)+

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igure shows the e0uivalent circuit to determine #of . The output impedance #of without the load

resistance factor #L is calculated from the open circuit output voltage %oc and the short circuit

output current C . rom the figure$ when the output is short circuited$ we get

I+ =

Vi @9R

+ +R f

fffffffffffffffffff

and I9=

AVidR

9

fffffffffffff

we 0now that Vid= @I+R f

Therefore, I9=@

AI+R f

R9

fffffffffffffffff

The short circuit current is

ISC= I+ +I9=ViR

9@ARf

R9

R+ +R fb c

fffffffffffffffffffffffffffffff

The out'ut resistance Rof=Voc

Isc

ffffffffand the closed o'en loo' gain Av =

Voc

Vi

ffffffff

Therefore,

Rof =

Av Vi

Vi

R9

@ARf

R9

R++R

f

b cfffffffffffffffffffffffffffffffffffffffffffff

H

J

I

K

fffffffffffffffffffffffffffffffffffffffffffffffff

Substituting the value of Av fro above e"n, we get

Rof =

R9

R++R

f

b c

R9+Rf +R+ + +A

` affffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

=

R9

R++R

f

b c

R9+

R++

Rf

fffffffffffffffffffffffffffffffffffffffffffff

+ +R

+A

R9+R

++R

f

ffffffffffffffffffffffffffffffffffffffffffffF G

fffffffffffffffffffffffffffffffffffffffffffffffffff

n the above e0uation$ the numerator contains the term #9 YY #+ F#f B and it is smaller than #9 . The

output resistance #of is therefore always smaller than #9 and from above e0n for Av - [$ the

output resistance #of - 9.

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N$ I$.&(%+$' A;1++&(:

The non ! inverting Amplifier with negative feedback is shown in figure. The input signal drives

the non ! inverting input of op-amp. The op-amp provides an internal gain A. The e7ternal

resistors #+ and #f form the feedback voltage divider circuit with an attenuation factor of . ince

the feedback voltage is at the inverting input$ it opposes the input voltage at the non ! inverting

input terminals$ and hence the feedback is negative or degenerative.

The differential voltage %id at the input of the op-amp is 4ero$ because node a is at the same voltage

as that of the non- inverting input terminal. As shown in figure$ #f and #+ form a potential divider.

Therefore$

Vi = R

+

R+

+Rf

fffffffffffffffffffBV

9

ince no current flows into the op-amp.

/0n can be written asV9Vi

fffffff=

R+ +RfRf

fffffffffffffffffff= ++

Rf

R+

fffff

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Vi @Vid 1+ +Vid1i+ Vi @Vid@V9 1f = 9

That is,

@1+@1i+ 1f

b cVid+ 1+ + 1f

b cVi= 1fV9

Siilarl& /C% at the out'ut node gives,

Vi @Vid@V9b c

1f+ AVis@V9b c

19= 9

That gives @1 f@A19b c

Vid+ 1fVi= 1f+ 19b c

V9

!sing this e"n forV

9

Vi

fffffffwe get

Av =V

9

Vi

fffffff=

A19

1+ + 1f

b c@1f1i

A + +` a

19

1f+ 1+@1ib c

1f+ 19b c

ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff

when the o'en @loo' gain A a''roaches infinit&, the e"n becoes

Av =A1

9 1

++ 1f

b c

A19

1f

ffffffffffffffffffffffffffffffffffff=

1+

+ 1f1f

fffffffffffffffffff= ++

1+

1f

fffffff

F&&*?),= );1++&(:

)1

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An op-amp that was feedback is called as feedback amplifier. A feedback amplifier is sometimes

referred to as closed loop amplifier because the feedback forms a closed loop between the input

and output. A closed loop amplifier can be represented by using 6 blocks.

+. ,ne for an op-amp

6. another for an feedback circuit.

There are * ways to con