EC7451: MICROPROCESSOR AND … I - 8085...2. Receiving a data byte from an input port or from memory 3. Sending out a byte to an output port or to memory. EC7451: MICROPROCESSOR AND

EC7451: MICROPROCESSOR AND MICROCONTROLLER

Dr. V. SATHIESH KUMAR Department of Electronics Engg., MIT1

Presentation Slides:

www.sathieshkumar.com/tutorials

Unit I : 8-BIT MICROPROCESSOR1. Architecture and pin details of 80852. Instruction Set3. Addressing Modes4. Interrupts5. Timing Diagrams6. Memory and I/O Interfacing

TEXT BOOKRamesh S. Gaonkar, "Microprocessor Architecture, Programming and Applications with 8085". Sixth edition, Penram International Publishing 2012.

Presented By,

Dr. V. Sathiesh Kumar Department of Electronics Engg.,

MIT-Anna University

EC7451: MICROPROCESSOR AND MICROCONTROLLER UNIT I – 8085


Introduction to Microprocessor:

•Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip

capable of performing ALU (Arithmetic Logical Unit) operations and communicating

with the other devices connected to it.

•Microprocessor consists of an ALU, register array, and a control unit.

•ALU performs arithmetical and logical operations on the data received from the

memory or an input device.

•Register array consists of registers identified by letters like B, C, D, E, H, L and

accumulator.

•The control unit controls the flow of data and instructions within the computer.



Introduction to Microprocessor: Operation

•The microprocessor follows a sequence: Fetch, Decode, and then Execute.

•Initially, the instructions are stored in the memory in a sequential order.

•The microprocessor fetches those instructions from the memory, then decodes it and

executes those instructions till STOP instruction is reached.

•Later, it sends the result in binary to the output port.

•Between these processes, the register stores the temporarily data and ALU performs

the computing functions.



Introduction to Microprocessor: List of terms used in microprocessors

•Here is a list of some of the frequently used terms in a microprocessor:

1. Instruction Set − It is the set of instructions that the microprocessor can understand.

2. Bandwidth − It is the number of bits processed in a single instruction.

3. Clock Speed − It determines the number of operations per second the processor

can perform. It is expressed in megahertz (MHz) or gigahertz (GHz).It is also known

as Clock Rate.

4. Word Length − It depends upon the width of internal data bus, registers, ALU, etc.

An 8-bit microprocessor can process 8-bit data at a time. The word length ranges

from 4 bits to 64 bits depending upon the type of the microcomputer.

5. Data Types − The microprocessor has multiple data type formats like binary, BCD,

ASCII, signed and unsigned numbers.



Introduction to Microprocessor: Features

•Here is a list of some of the most prominent features of any microprocessor −

1. Cost-effective − The microprocessor chips are available at low prices and results its

low cost.

2. Size − The microprocessor is of small size chip, hence is portable.

3. Low Power Consumption − Microprocessors are manufactured by using metal

oxide semiconductor technology, which has low power consumption.

4. Versatility − The microprocessors are versatile as we can use the same chip in a

number of applications by configuring the software program.

5. Reliability − The failure rate of an IC in microprocessors is very low, hence it is

reliable.



8085 Microprocessor Features:

1. It is a 8-bit microprocessor.

2. 40-pin ceramic DIP.

3. It is manufactured with N-MOS technology.

4. It has 16 bit address bus and hence can address up to 216=65536 bytes of memory

locations through A0-A15 address lines.

5. The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0-AD7.

6. Data bus is a group of 8 lines D0-D7.

7. It supports external interrupt request.

8. A 16-bit program counter (PC) and 16-bit Stack pointer (SP).

9. Six 8-bit general purpose registers arranged in pairs: BC, DE, HL.

10. It requires a signal +5 V power supply and operates at 6.144 MHz single phase

clock.

11. Program, data and stack memories occupy the same memory space. The total

addressable memory size is 64 KB.

7

8085 Microprocessor Features:

12. The processor always uses 16-bit addresses, so that data can be placed anywhere.

13. Stack memory is limited only by the size of memory. Stack grows downward.

14. First 64 bytes in a zero memory page should be reserved for vectors used by RST

instructions.

15. It is used in washing machines, microwave ovens, mobile phones, etc.


Dr. V. SATHIESH KUMAR Department of Electronics Engg., MIT

8

8085 Microprocessor Pin Details:



9




10


RESET IN* (Active Low): When this signal goes low, the program counter (PC ) is set

to zero, microprocessor is reset and resets the interrupt enable and HLDA flip-flops.

RESET OUT: This signal indicates the microprocessor is reset. This signal can be

used to reset other devices. The signal is synchronized to the processor clock and lasts

an integral number of clock periods.

8085 Microprocessor has two Serial Input/Output pins that are used to read/write one

bit data to and from peripheral devices.

SID (Serial Input Data Line): The data on this line is loaded into accumulator (bit 7)

whenever a RIM instruction is executed.



11


SOD (Serial Output Data Line): The SIM instruction loads the value of the accumulator

(bit 7) into SOD latch if bit 6 (SOE) of the accumulator is 1.

HOLD: Indicates that another master is requesting the use of the address and data

busses. The CPU, upon receiving the hold request, will relinquish the use of the bus as

soon as the completion of the current bus transfer. Internal processing can continue. The

processor can regain the bus only after the HOLD is removed. When HOLD is

acknowledged, the Address, Data, RD, WR and IO/M lines are tristated.



12


HLDA* (Hold Acknowledge, Active Low): Indicated that the CPU has received the

HOLD request and that it will relinquish the bus in the next clock cycle. HLDA* goes low

after the HOLD request is removed.

READY: This signal synchronizes the fast CPU and the slow memory, peripherals. If

READY is high during a read or write cycle, it indicates that the memory or peripheral is

ready to send or receive data. If READY is low, the CPU will wait an integral number of

clock cycle for READY to go high before completing the read or write cycle.

ADDRESS BUS : A15-A8, it carries the most significant 8-bits of memory/IO address.

ADDRESS/DATA BUS : AD7-AD0, it carries the least significant 8-bit address and data

bus. These pins are used for:

1. Receiving the program code from memory 8 bits at a time.

2. Receiving a data byte from an input port or from memory

3. Sending out a byte to an output port or to memory.



13




14


•CONTROL AND STATUS SIGNALS : These signals are used to identify the nature of

operation. There are 3 control signal and 3 status signals.

Three control signals are RD, WR & ALE.

1. RD* (Active Low) − This signal indicates that the selected IO or memory device is to

be read and is ready for accepting data available on the data bus.

2. WR* (Active Low)− This signal indicates that the data on the data bus is to be written

into a selected memory or IO location.

3. ALE − It is a positive going pulse generated when a new operation is started by the

microprocessor. When the pulse goes high, it indicates address. When the pulse

goes down it indicates data.



15


•CONTROL AND STATUS SIGNALS : Three status signals are IO/M*, S0 & S1.

1.IO/M* - This signal is used to differentiate between IO and Memory operations, i.e.

when it is high indicates IO operation and when it is low then it indicates memory

operation.

• Microprocessor does not directly communicate with an I/O device. It only

communicates with I/O ports.

•If there are number of I/O ports in the system, each port must have a unique address,

just like each memory location has a unique address.

•When IO/M* is logic 0, it means that the address sent out by the processor is for

addressing a memory location.

•When IO/M* is logic 1, it means that the address sent out by the processor is for

addressing an I/O port.



16


•CONTROL AND STATUS SIGNALS : Three status signals are IO/M*, S0 & S1.

2. S0 and S1 - These signals are used to identify the type of current operation.



17


•POWER SUPPLY : There are 2 power supply signals − VCC & VSS. VCC indicates

+5V power supply and VSS indicates ground signal.

•CLOCK SIGNALS : There are 3 clock signals, i.e. X1, X2, CLK OUT.

1. X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set

frequency of the internal clock generator. This frequency is internally divided

by 2.

2. CLK OUT − This signal is used as the system clock for devices connected with

the microprocessor.

•INTERRUPTS : Interrupts are the signals generated by external devices to request the

microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,

RST 6.5, RST 5.5, and INTR.

•INTA* (Active Low) − It is an interrupt acknowledgment signal.



18

8085 Microprocessor Architecture:



19


Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and

load/store operations. It is connected to internal data bus & ALU.

In an arithmetic operation involving two operands, one operand has to be in this

register. The result of the arithmetic operation is stored or accumulated in this register.

ALU : It performs arithmetic and logical operations like Addition, Subtraction, AND, OR,

etc. on 8-bit data.

FLAG Register : It is an 8-bit register having five 1-bit flip-flops, which holds either

0 or 1 depending upon the result stored in the accumulator.

1. Sign flag (S): Set if the MSB of the result is set(1 -> Negative, 0 -> Positive Result).

2. Zero flag (Z): Set if the result is zero.

3. Auxiliary carry (AC): Set if there was a carry out from bit 3 to bit 4 of the result.

4. Parity (P): Set if the parity (the number of set bits in the result) is even.

5. Carry flag (C): Set if there was a carry during addition or borrow during

subtraction/comparison/rotation.



20




21


•General Purpose Registers : There are 6 general purpose registers in 8085

processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data. These registers can

work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L.

•It is possible to use these registers as pairs to store 16-bit information.

• Only BC, DE and HL can form register pairs. The information in these register pairs can

be interpreted as 16-bit data or 16-bit address of a memory location, depending on the

instruction being executed.

•When they are used as register pairs in an instruction, the left register is understood

to have the MS byte and the right register the LS byte.

•HL is the most important register pair.

•Although 8085 is a 8-bit processor, the designers have provided for 16-bit addition in

the instruction set. In such a 16-bit addition, one of the operands has to be in the HL

pair.

• MOV C, M – The address of memory location is specified in HL register pair.



22


Temporary Registers : It is an 8-bit register, which holds the temporary data of

arithmetic and logical operations.

Stack pointer (SP): It is a 16-bit register, points to the top of the stack. This

register is always decremented/incremented by 2 during push and pop

instructions.

Program counter (PC): It is a 16-bit register used to store the memory address

location of the next instruction to be executed. Microprocessor increments the

program whenever an instruction is being executed, so that the program counter points

to the memory address of the next instruction that is going to be executed.

Instruction Register and Decoder : It is an 8-bit register. When an instruction is

fetched from memory then it is stored in the Instruction register. Instruction

decoder decodes the information present in the Instruction register.



23


•Timing and Control Unit : It provides timing and control signal to the microprocessor

to perform operations.

•Following are the timing and control signals, which control external and internal circuits:

1. Control Signals: READY, RD*, WR*, ALE

2. Status Signals: S0, S1, IO/M*

3. DMA Signals: HOLD, HLDA*

4. RESET Signals: RESET IN*, RESET OUT

•Interrupt Control : As the name suggests it controls the interrupts during a process.

When a microprocessor is executing a main program and whenever an interrupt occurs,

the microprocessor shifts the control from the main program to process the incoming

request. After the request is completed, the control goes back to the main program.

•There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST

5.5, TRAP.



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•Serial Input/output Control : It controls the serial data communication by using

these two lines: SID (Serial input data) and SOD (Serial output data).

•Address Buffer and Address/Data Buffer : The content stored in the stack pointer

and program counter is loaded into the address buffer and address-data buffer to

communicate with the CPU. The memory and I/O chips are connected to these buses;

the CPU can exchange the desired data with the memory and I/O chips.

•Address Bus and Data Bus : Data bus carries the data to be stored. It is

bidirectional, whereas address bus carries the location to where it should be stored

and it is unidirectional. It is used to transfer the data and Address I/O devices.



25

8085 Microprocessor Instruction Set:

• Instruction can be as large as 3 bytes.

• First byte will be opcode. With 8-bits for opcode, 28 = 256 distinct opcodes (00H

to FFH) are possible.

• However, only 246 opcodes are implemented in 8085.

• Of the 246 opcodes we have: 202 opcodes are 1-byte long, 18 opcodes are 2-

byte long and 26 opcodes are 3-byte long.



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8085 Microprocessor Instruction Set: Data Transfer Instructions

MVI r, d8 –MoVe Immediate 8-bit data to register r, where r= A, B, C, D, E, H, L or M

• Instruction uses immediate addressing for specifying the data.

• As r can have any of the eight values, there are eight opcodes are possible.

• It occupies 2-bytes in the memory

• Eg: MVI E, 8DH

• Flags are not affected by this instructions.



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MVI M, d8 –MoVe Immediate 8-bit data to memory location pointed by HL pair.

• Instruction uses immediate addressing for specifying the data.

• It occupies 2-bytes in the memory

• Eg: MVI M, 8DH

• Flags are not affected by this instructions.



28


MOV r1, r2–MOVe the 8-bit data from register r2 to r1.

First operand specifies the destination and second the source.

Instruction uses register addressing for specifying the data.

Where r1, r2 = A, B, C, D, E, H, L or M

As r1 can have any of the eight values, and r2 can have any of the eight values,

there are 8 X 8 =64 opcodes for this type of instruction.

It occupies only one byte in memory.

Eg: MOV E, H

Flags are not affected by this instructions.



29


MOV r, M– Load register r with the 8-bit value in memory location pointed by HL.

The address of the memory location is provided by HL register pair.

This instruction uses register-indirect addressing for specifying the data.

As r= A, B, C, D, E, H or L, there are seven opcodes for this type of instruction.

It occupies 1 byte in memory.

Eg: MOV E, M




30


MOV M, r– Load the memory location with a 8-bit value from r register.

The address of the memory location is provided by HL register pair.

This instruction uses register addressing for specifying the data.

As r= A, B, C, D, E, H or L, there are seven opcodes for this type of instruction.


Eg: MOV M, E




31




32


LXI rp, d16– Load eXtended register Immediate – Loads the register pair rp with the

16-bit data as denoted as d16.

This instruction uses immediate addressing for specifying the data.

As rp= BC, DE or HL, there are three opcodes for this type of instruction.

It occupies 3 byte in memory. First byte specifies the opcode, and the next two

bytes provide the 16-bit data.

Eg: LXI H, F850H

Notice that when specifying the register pair, we specify only the MS register in the

instruction mnemonic.




33


LDA a16– LoaD Accumulator content from memory location specified in instruction.

This instruction uses absolute or direct addressing for specifying the data.


bytes provide the 16-bit address.

Eg: LDA F850H




34


STA a16– STore Accumulator content in memory location specified in instruction.

This instruction uses absolute or direct addressing for specifying the destination.


bytes provide the 16-bit address.

Eg: STA F850H




35


XCHG– eXCHanGe – exchange contents of HL pair with DE pair.

This instruction uses implied addressing.


Eg: XCHG




36


LDAX rp– LoaD Accumulator from memory pointed by eXtended register denoted as rp.

This instruction uses register-indirect addressing for specifying the data.


Eg: LDAX B


Only other instruction of this type is LDAX D.



37


STAX rp– STore Accumulator contents in memory pointed by eXtended register

denoted as rp.

This instruction uses register-indirect addressing for specifying the destination.


Eg: STAX B


Only other instruction of this type is STAX D.



38


LHLD a16 – Load HL pair using Direct addressing from memory location whose 16-bit

address is denoted as a16.

As HL pair has to be loaded, the data comes from two consecutive locations

starting at the address a16.

This instruction uses absolute or direct addressing for specifying the data.


Eg: LHLD F2BCH




39


SHLD a16 – Store HL pair using Direct addressing in memory location whose 16-bit

address is denoted as a16.

As HL pair has to be stored, it has to be stored in two consecutive locations

starting at the address a16.

This instruction uses absolute or direct addressing for specifying the destination.


Eg: SHLD F2BCH




40

8085 Microprocessor Instruction Set: Arithmetic Group of Instructions

It has only add and subtract instructions.

In addition of two numbers, 8085 imposes the restriction that one of the operands

must be in the Accumulator.

The other operand can be one of the following:

1. Contents of an 8-bit register

2. Contents of memory location pointed by HL pair

3. Eight bit immediate data.



41


ADD R– ADD contents of R to accumulator, where R = A, B, C, D, E, H, L, or M

The result of the addition will be stored in the accumulator.

As R can be any of eight values, there are eight opcodes.



Eg: ADD E

Flags are affected by this instructions.

The correct answer is 38H with carry of 1.



42


ADC R– ADd with Carry, where R = A, B, C, D, E, H, L, or M.

It is needed to add the following two 16-bit numbers.

The result of the addition (contents of R and Accumulator along with a carry of

1) will be stored in the accumulator.

As R can have any of the eight values, there are eight opcodes.


It occupies 1 byte in memory. Flags are affected by this instructions.

Eg: ADC E



43


ADI d8– ADd Immediate to Accumulator, where d8 stands for any 8-bit data.




Eg: ADI F3H


The correct answer is 38H with carry of 1.



44


ACI d8– Add with Carry Immediate to Accumulator, where d8 stands for any 8-bit data.




Eg: ACI F3H




45


SUB R– SUBtract contents of R from Accumulator, where R = A, B, C, D, E, H, L, or M

The result of the subtraction (A <- A-R) will be stored in the accumulator.

As R can be any of eight values, there are eight opcodes.



Eg: SUB E


The carry generated in addition is complemented and stored as the C flag value.



46


SBB R– SuBtract with Borrow, where R = A, B, C, D, E, H, L, or M.

It is needed to subtract the following two 16-bit numbers.

The result of the subtraction (contents of R from Accumulator along with a carry

value) will be stored in the accumulator.



It occupies 1 byte in memory. Flags are affected by this instructions.

Eg: SBB E




SUI d8– SUbtract Immediate from Accumulator, where d8 stands for any 8-bit data.

The result of the subtraction (8-bit immediate value from the accumulator) will be

stored in the accumulator.



Eg: SUI F3H



47




SBI d8– Subtract with Borrow Immediate from Accumulator, where d8 stands for any 8-

bit data.

The result of the subtraction (8-bit immediate value from the accumulator along

with the carry value) will be stored in the accumulator.



Eg: SBI F3H



48



49


INR R– INcRement, where R = A, B, C, D, E, H, L, or M.

The result of the incrementation (add 1 to the contents of R) will be stored in the

R.


Many times a register content is used as a counter.



Eg: INR M

All Flags are affected, except C flag by this instructions.



50


DCR R– DeCRement, where R = A, B, C, D, E, H, L, or M.

The result of the decrementation (subtract 1 from the contents of R) will be

stored in the R.


Many times a register content is used as a down counter.



Eg: DCR M

All Flags are affected, except C flag by this instructions.



51


INX rp– INcrement eXtended register, where rp = BC, DE, or HL.

The result of incrementation (add 1 to the contents of rp) will be stored in the rp.

As rp can have any of the three values, there are three opcodes.

Many times a register content is used to store a memory address.



Eg: INX B


Basically, INX instruction increments a 16-bit quantity, whereas INR increments

a 8-bit quantity.



52


DCX rp– DeCcrement eXtended register, where rp = BC, DE, or HL.

The result of decrementation (subtract 1 from the contents of rp) will be stored

in the rp.


Many times a register content is used to store a memory address.



Eg: DCX B


Basically, DCX instruction decrements a 16-bit quantity, whereas DCR

increments a 8-bit quantity.



53


DAD rp– Double ADd, where rp = BC, DE, or HL.

Perform a 16-bit addition

The result of addition (add contents of rp to HL) will be stored in the HL.




Eg: DAD B

Only carry flag is affected by this instructions.



54


DAA – Decimal Adjust after Addition.

Let us consider we want to add two decimal numbers 38 and 45.

They will be represented in BCD as 0011 1000 and 0100 0101.

The addition results in 0111 1101.

But the answer will be incorrect if we want to interpret this result as a BCD number.

Here, in such situations, we can use DAA to have the BCD sum as outcome.

Performs BCD addition

This instruction uses implied addressing for specifying the data.


Eg: DAA

Only carry flag is affected by this instructions.



55



The working of DAA instruction depends on the contents of the AL register, Cy,

and AC flags.

In effect, it adds 00H, 06H, 60H, or 66H to Accumulator so as to get the correct

BCD answer in the Accumulator.



56



As the summary of all related rules are listed below −

1. If the LS hex digit in A is <= 9 and AC flag is 0, the LS hex digit value will not be

altered.

2. If the LS hex digit is >9, or if AC flag is set to 1, it adds 6 to the LS hex digit of A. If

carry results, then it increments the MS hex digit if this addition resulted in a carry to

the MS digit position. In this process, the C flag will be set to 1 if the MS hex digit

was incremented from F to 0.

3. If the MS hex digit is <= 9 and C flag is 0, the MS hex digit will not be altered, and C

flag is reset to 0.

4. If the MS hex digit is > 9, or if C flag is set to 1, it adds 6 to the MS hex digit of A and

sets C flag to 1.



57

8085 Microprocessor Instruction Set: Logical Group of Instructions

8085 has instructions to perform AND, OR, Ex-OR and NOT operations.

For AND instruction, 8085 imposes the restriction that one of the operands must be

in the Accumulator.

The other operand can be one of the following,




The AND operation is used for selectively resetting to 0 some bits of the

Accumulator.

The AND instruction affects the flags as follows,

1. S, P and Z flags are updated based on the result

2. C flag is reset to 0

3. AC flag is set to 1



58


ANA R – ANd Accumulator and R, where R = A, B, C, D, E, H, L, or M

AND contents of R with Accumulator. The result will be stored in Accumulator.

As R can have any of the eight values, there are eight opcodes for this type of

instruction.



Eg: ANA E



59


ANI d8 – ANd Immediate with Accumulator, where d8 stands for any 8-bit data.

AND 8-bit immediate data with the Accumulator. The result will be stored in

Accumulator.



The S, P and Z flags are affected based on the result. C is reset to 0 and AC is set

to 1.

Eg: ANI F3H



60


For OR instruction, 8085 imposes the restriction that one of the operands must be in

the Accumulator.





The OR operation is used for selectively setting some bits of the Accumulator.

The OR instruction affects the flags as follows,


2. C flag and AC flags are reset to 0



61


ORA R – OR Accumulator and R, where R = A, B, C, D, E, H, L, or M

OR contents of R with the Accumulator. The result will be stored in Accumulator.


instruction.



Eg: ORA E



62


ORI d8 – OR Immediate with Accumulator, where d8 stands for any 8-bit data.

OR 8-bit immediate data with the Accumulator. The result will be stored in

Accumulator.



The S, P and Z flags are affected based on the result. C and AC are reset to 0.

Eg: ORI F3H



63


For Ex-OR instruction, 8085 imposes the restriction that one of the operands must be

in the Accumulator.





The Ex-OR operation is used for selectively complementing some bits of the

Accumulator.

The Ex-OR instruction affects the flags as follows,


2. C flag and AC flags are reset to 0



64


XRA R – eXclusive OR Accumulator and R, where R = A, B, C, D, E, H, L, or M

Ex-OR contents of R with the Accumulator. The result will be stored in

Accumulator.


instruction.



Eg: XRA E



65


XRI d8 – eXclusive OR Immediate with Accumulator, where d8 stands for any 8-bit

data.

Ex-OR 8-bit immediate data with the Accumulator. The result will be stored in

Accumulator.



The S, P and Z flags are affected based on the result. C and AC are reset to 0.

Eg: XRI F3H



66


CMA – CoMplement Accumulator.

It performs 1’s complement operation on the contents of the Accumulator. The

result will be stored in Accumulator.



Flags are not affected by the execution of this instruction.

Eg: CMA



67


CMC – CoMplement the Carry flag.

It performs complement operation on the carry flag. The result will be stored back

in C flag.



Eg: CMC



68


STC – SeT the Carry flag.

It performs setting of carry flag. The result will be stored back in C flag.



Eg: STC



69


A compare instruction compares two operands, and affects the status flags,

depending on the result of the comparison.

For compare instruction, 8085 imposes the restriction that one of the operands must

be in the Accumulator.





The compare operation actually computes the value of the Accumulator contents

minus other operand.

The original values of the operands are not changed.

Based on the result, all the flags are affected.



70


CMP R – CoMPare Accumulator and R, where R = A, B, C, D, E, H, L, or M

Compare contents of Accumulator with R. The result will be stored in Temp

Register.


instruction.



Eg: CMP E



71


CPI d8 – ComPare Immediate with Accumulator, where d8 stands for any 8-bit data.

Compare Accumulator with 8-bit immediate data. The result will be stored in

Temp register.



The all flags are affected based on the result.

Eg: CPI F5H



72


Intel 8085 provides instructions to rotate Accumulator contents left or right.

Rotate operation can be performed only on Accumulator contents.

RLC– Rotate Left Accumulator – It rotates the Accumulator contents to the left by 1-bit

position.

The instruction is useful in the following ways:

1. To check the value of the MS bit of the Accumulator, perform rotate left, and note the

C flag value.

2. To perform multiplication by 2. It works correctly for unsigned numbers, as long as

the MS bit of Accumulator is a 0 before rotation.



73


RAL– Rotate Accumulator Left involving C flag in rotation .

It is 9-bit rotation of Accumulator and C contents.

Carry flag is affected by this instruction execution.


1. To check the value of the MS bit of the Accumulator, perform rotate left, and note the

C flag value.

2. To perform multiplication by 2. It works correctly for unsigned numbers, as long as

the MS bit of Accumulator and C flag are 0 before rotation.

3. To introduce a new bit value to the LS bit position, put this bit value in the C flag and

execute the instruction.



74


RRC– Rotate Right Accumulator. – It rotates the Accumulator contents to the right

by 1-bit position.



1. To check the value of the LS bit of the Accumulator, perform rotate right, and note

the C flag value.

2. To perform division by 2. It works correctly for unsigned numbers, as long as the LS

bit of Accumulator is 0 before rotation.



75


RAR– Rotate Accumulator Right involving C flag in rotation.

It is 9-bit rotation of Accumulator and C contents.



1. To check the value of the LS bit of the Accumulator, perform rotate right, and note

the C flag value.

2. To perform division by 2. It works correctly for unsigned numbers, as long as the LS

bit of Accumulator and C flag are 0 before rotation.

3. To introduce a new bit value to the MS bit position, put this bit value in the C flag and

execute the instruction.



76

8085 Microprocessor Instruction Set: NOP and Stack Group of Instructions

Stack and the Stack Pointer

Stack is a LIFO (Last In First Out) data structure implemented in the RAM area and

is used to store addresses and data, when the microprocessor branches to a

subroutine.

SP is a special purpose 16-bit register. It contains a memory address.

SP specify the top most useful location in the stack. In other words, it indicates the

memory location with the smallest address having useful information.



77


Reading from the stack

The 8085 reads from the top of the stack of useful information.

The 8085 is designed to read always 2 bytes useful information from the top of the

stack.

As such, in this case it reads from locations FC78H and FC79H.

This information, which is read can only be loaded into a register pair.

This operation of loading a register pair by reading information from the stack top is

called a POP operation.

After POP operation, the content of FC78H and FC79H are treated as useless by the

8085.

To indicate this, the SP contents are changed to FC7AH. This is done automatically by

8085 by incrementing SP contents by 2.



78


Writing to the stack

The 8085 is designed to write always into two locations of useless information just

above the top of stack.

In 8085, this information, which is written can only be coming from a register pair.

This operation of storing a register pair by writing information above the stack

top is called a PUSH operation.

Suppose we store register pair BC when SP contents were FC7AH, then, information

from BC pair is stored in memory locations FC79H and FC78H.

To indicate this, the SP contents are changed to FC78H. This is done automatically by

8085 by decrementing SP contents by 2.



79


POP rp – Instruction loads register pair rp by popping out 2 bytes from the top of

the stack. rp stands for one of the following register pairs. rp = BC, DE, HL or PSW.

PSW – Processor Status Word (Accumulator is the MS byte, and Flags register is the

LS byte).

Two bits are used in an opcode to specify a register pair.

As rp can have any of the four values, there are four opcodes.

It occupies only 1 byte in memory.

Eg: POP PSW



80


PUSH rp – Instruction stores the contents of register pair rp by pushing it into two

locations above the top of the stack. rp stands for one of the following register pairs.

rp = BC, DE, HL or PSW.

PSW – Processor Status Word (Accumulator is the MS byte, and Flags register is the

LS byte).

Two bits are used in an opcode to specify a register pair.

As rp can have any of the four values, there are four opcodes.


Eg: PUSH B



81


Summary: SP is a 16-bit register inside 8085.

Its contents specify the topmost filled memory location in the stack.

Stack is a LIFO data structure implemented in RAM.

In push or pop operation the data transfer is between a register pair and the stack.

The stack grows towards the address 0000H, as PUSH operations are performed.

The SP content is decremented by 2 for every PUSH operation.

It shrinks towards the address FFFFH, as POP operations are performed. The SP

contents are incremented by 2 for every POP operation.

SP is generally loaded with the highest RAM address+1.

For example, if we have RAM from C000H to C7FFH, then SP is loaded with C800H at

the beginning of the user program.

The program is generally loaded on a kit starting from the lowest RAM address. This

allows the user program to expand towards the higher addresses and the stack to grow

towards lower addresses, without overlapping.



82


LXI SP, d16 – Used to load 16-bit immediate data to the SP.

Only one opcode.

It occupies 3 bytes in memory.

Example: LXI SP FC06H

SPHL – Loads the stack pointer with the contents of register pair HL.

It occupies one byte in memory, compared to LXI SP instruction, which is 3 bytes long.

Because of this advantage, SPHL can be useful when SP is required to be initialized to

a specific value a number of times in a program.

Example: SPHL



83


XTHL– eXchange Top of stack with HL – instruction exchanges the contents of the

top two locations of the stack with the contents of register pair HL.

Only one opcode.


Note: SP contents remain unchanged. It is neither decremented or incremented.

Example: XTHL



84


INX SP– instruction is used to increment the SP contents by 1.

Only one opcode.


Example: INX SP

DCX SP – instruction is used to decrement the SP contents by 1.

Only one opcode.


Example: DCX SP

DAD SP – instruction is used to add SP contents to HL contents, and the result in HL.


Only carry flag is affected.



85


NOP– No OPeration - instruction does not do anything.

Only one opcode 00H.


Example: NOP

It is useful in the following cases:\

1. For generating small time-delays of the order of a few microseconds.

2. When we are required to delete a few instructions in our program.

3. When we are required to insert a few instructions in our program

• Thus, it is a good programming practice to have a few NOP instructions in the

program at regular intervals, especially during program development.

• Alternatively, the user can make use of ‗insert‘ and ‗delete‘ keys provided on the kit,

which help in inserting new instructions to the program, or deleting existing

instructions.



86

8085 Microprocessor Instruction Set: Branch Group of Instructions

Changes in program flow is needed when a sequence of instructions is to be

executed repeatedly.

It is also needed when it is required to choose between two or more sequences of

actions based on some conditions.

The branch instructions can be used for effecting a forward branch or a backward

branch.

The jump instructions are classified into:

1. Unconditional jump instruction

2. Conditional jump instruction



87


JMP a16 – JuMP and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided in the instruction.

It is a 3-byte instruction.

Example: JMP F950H

Functionally, JMP F950H can be treated as,

JMP F950H = LXI PC, F950H



88


PCHL– Load PC with the contents of HL.

This instruction is used to jump to the address provided in HL register pair.

This is an unconditional indirect jump instruction


Example: PCHL



89


Conditional Jump Instructions – Jump based on the value of a single flag.

The jump takes place based on the value of carry flag, zero flag, parity flag or sign

flag.

There is no jump instruction based on the value of auxiliary carry flag.

JNC a16– Jump if Not Carry and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if carry flag

value is 0.

If carry flag value is 1, program flow continues sequentially.


Example: JNC F950H



90


JC a16– Jump if Carry and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if carry flag

value is 1.

If carry flag value is 0, program flow continues sequentially.


Example: JC F950H



91


JNZ a16– Jump if Not Zero result and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if zero flag value

is 0 (result is not zero).

If zero flag value is 1, program flow continues sequentially.


Example: JNZ F950H



92


JZ a16– Jump if Zero result and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if zero flag value

is 1 (result is zero).

If zero flag value is 0, program flow continues sequentially.


Example: JZ F950H



93


JPO a16– Jump if Parity Odd and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if parity flag

value is 0 (odd parity).

If parity flag value is 1, program flow continues sequentially.


Example: JPO F950H

JPE a16– Jump if Parity Even and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if parity flag

value is 1 (even parity).

If parity flag value is 0, program flow continues sequentially.


Example: JPE F950H



94


JP a16– Jump if Positive and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if sign flag value

is 0 (positive result).

If sign flag value is 1, program flow continues sequentially.


Example: JP F950H

JM a16– Jump if Minus and a16 stands for any 16-bit address.

This instruction is used to jump to the address a16 provided, only if sign flag value

is 1 (negative result).

If sign flag value is 0, program flow continues sequentially.


Example: JM F950H



95


Unconditional CALL and RETURN instructions

Very often a particular sequence of instructions have to be used at several points in the

program. Writing the same sequence of instructions at these various points can be

avoided by writing this series of instructions as a subprogram. Such subprograms are

also variously termed as subroutines or procedures.

Whenever the instruction in a subroutine are required to be executed, we branch to the

subroutine using the CALL instruction ‗call a subroutine‘..

It is a 3-byte instruction, with 1 byte for the opcode and 2 bytes for the address of

the subroutine.

After executing the instructions in the subroutine we return to the next

instruction after the CALL instruction in the main program. This is achieved by the

execution of the RET instruction (RETurn from subroutine).

RET is a 1-byte instruction.



96


Difference between CALL and JUMP instructions

If a JMP instruction is executed, we jump to the destination location, and the

execution caries on from there, without bothering to come back later to the instruction

after the JMP.

If a CALL instruction is executed, we jump to the subroutine, and the execution

carries on from there till the RET instruction is executed in the subroutine, and then we

come back to the instruction after the CALL in the main program.

The address of the next instruction after the CALL instruction is called the return

address.

In order to facilitate such a return, the CALL instruction will first of all store above

the top of the stack, the return address.

Only then the branch to the subroutine takes place.



97




98


• The way stack contents get affected due to execution of ‗CALL F950H‘ is shown

below,

•The way in which the stack contents get affected due to execution of RET is shown

below,



99


Conditional CALL Instructions – Branch to a subroutine based on the value of a

single flag.

The branch takes place based on the value of carry flag, zero flag, parity flag or sign

flag.

There is no CALL instruction based on the value of auxiliary carry flag.

CNC a16– Call if Not Carry and a16 stands for any 16-bit address.

This instruction is used to branch to the subroutine address a16 provided, only if

carry flag value is 0.

If carry flag value is 1, program flow continues in the main program sequentially.


Example: CNC F950H



100




101


CC a16– Call if Carry and a16 stands for any 16-bit address.


carry flag value is 1.

If carry flag value is 0, program flow continues in the main program sequentially.


Example: CC F950H



102


CNZ a16– Call if Not Zero result and a16 stands for any 16-bit address.


zero flag value is 0 (result is not zero).

If zero flag value is 1, program flow continues in the main program sequentially.


Example: CNZ F950H



103


CZ a16– Call if Zero result and a16 stands for any 16-bit address.


zero flag value is 1 (result is zero).

If zero flag value is 0, program flow continues in the main program sequentially.


Example: CZ F950H



104


CPO a16– Call if Parity Odd and a16 stands for any 16-bit address.


parity flag value is 0 (odd parity).

If parity flag value is 1, program flow continues in the main program sequentially.


Example: CPO F950H

CPE a16– Call if Parity Even and a16 stands for any 16-bit address.


parity flag value is 1 (even parity).

If parity flag value is 0, program flow continues in the main program sequentially.


Example: CPE F950H



105


CP a16– Call if Positive and a16 stands for any 16-bit address.


sign flag value is 0 (positive result).

If sign flag value is 1, program flow continues in the main program sequentially.


Example: CP F950H

CM a16– Call if Minus and a16 stands for any 16-bit address.


sign flag value is 1 (negative result).

If sign flag value is 0, program flow continues in the main program sequentially.


Example: CM F950H



106


Conditional RET Instructions – Effect a return to the main program based on the

value of a single flag.

The return takes place based on the value of carry flag, zero flag, parity flag or sign

flag.

There is no RET instruction based on the value of auxiliary carry flag.

RNC– Return if Not Carry.

This instruction is used to return to the main program, only if carry flag value is 0.

If carry flag value is 1, program flow continues in the subroutine sequentially.


Example: RNC



107




108


RC– Return if Carry.

This instruction is used to return to the main program, only if carry flag value is 1.

If carry flag value is 0, program flow continues in the subroutine sequentially.


Example: RC



109


RNZ– Return if Not Zero result.

This instruction is used to return to the main program, only if zero flag value is 0

(result is not zero).

If zero flag value is 1, program flow continues in the subroutine sequentially.


Example: RNZ



110


RZ– Return if Zero result.

This instruction is used to return to the main program, only if zero flag value is 1

(result is zero).

If zero flag value is 0, program flow continues in the subroutine sequentially.


Example: RZ



111


RPO– Return if Parity Odd.

This instruction is used to return to the main program, only if parity flag value is 0

(odd parity).

If parity flag value is 1, program flow continues in the subroutine sequentially.


Example: RPO

RPE– Return if Parity Even.

This instruction is used to return to the main program, only if parity flag value is 1

(even parity).

If parity flag value is 0, program flow continues in the subroutine sequentially.


Example: RPE



112


RP– Return if Positive.

This instruction is used to return to the main program, only if sign flag value is 0

(positive result).

If sign flag value is 1, program flow continues in the subroutine sequentially.


Example: RP

RM– Return if Minus.

This instruction is used to return to the main program, only if sign flag value is 1

(negative result).

If sign flag value is 0, program flow continues in the subroutine sequentially.


Example: RM



113


RST n – RESTART instructions

n has a value from 0 to 7 only. Example: RST 0, RST 1, …, RST 7.

Functionally RST n instruction is RST n = CALL n*8

Example: RST 2 is functionally equivalent to CALL 2*8 = CALL 0010H.

The advantage of RST 2 is that it is only 1 byte, whereas CALL 0010H is 3-bytes long.

Thus RST instructions are useful for branching to frequently used subroutines.

RST n is only 1-byte long. The reason is that n value is restricted to the range 0-7. So

only 3 bits are needed to denote n value, and the other 5 bits in the byte provide the

code for RST.



114




115

Memory Interfacing : Concept of Chip Selection

• In a microcomputer system, the microprocessor is the master, which controls all

the operations of the computer.

•This is because, it is the microprocessor in which the control circuit is embedded.

•In addition to the processor, there may be a number of RAM chips, EPROM chips,

I/O ports, and other special peripheral chips like 8253 timer etc.

•But at any instant of time, the processor can communicate with only one chip.

•The processor selects the chip with which it would like to communicate by

activating chip select pin/pins of the chip.

•A chip select pin can be active low or active high.

•It is the choice of the chip designer.

•Only when the chip select pins of the chip are activated, the chip is selected for

communication with the processor.

•A chip select line is also variously called a ‗device select line‘, ‗chip enable line‘, or

‗device enable line‘.



116

Memory Interfacing : RAM Chip, Pin Details and Address Range

• Let us say, we have a 2K X 8 RAM chip. Here 2K X 8 means that there are 2K (= 2 X

1024 = 2048) memory locations, with each location having 8-bits of information.

•It is available as a 24-pin DIP IC.

•Its functional pin diagram is shown below,

• Note that there are 11 address input pins to select one of the 2K = 211 memory

locations in the chip.

•There are eight bi-directional pins for data transfer with the processor.



117


• The action desired by the processor is indicated by the RD* and WR* input pins to the

RAM chip.

•There are two pins meant for power supply connection of +5V DC and Ground.

•Then there is an active low chip select pin.

•What is the starting address for this chip?

•Does it have to always start from 0000H, or can it start at say C000H?

•It need not always start at 0000H.

•Suppose we had a 2K X 8 RAM chip in our system, with the starting address at 0000H.

•Sometimes later, we decide to increase the RAM capacity in the system by another 2K

X 8.

•If this added memory also starts with the address 0000H, effectively we have not made

any additions to the RAM memory capacity at all.

•To be useful, the added memory address range should not overlap with the existing

address range.



118


• Of course, in 8085 based system it should be within the address range 0000H –

FFFFH.

•Let us say it is desired to place the 2K X 8 RAM such that its starting address is

C000H. One possible circuit connection is given below,

• Note that there are 11 address input pins to select one of the 2K = 211 memory

locations in the 2K X8 RAM chip.

•But 8085 sends out a 16-bit address.



119


• Remaining 5 address lines are used for selecting the chip such that the starting

address for the RAM becomes C000H as shown below,

• All of the NAND gate inputs become 1, when A15, A14, A13, A12, A11 IO/M* = 110000.

•So the NAND gate output becomes 0, thus activating the chip select pin of the RAM.

•Thus location 0 in the RAM is addressed by the 8085 as location C000H.

•Location 1 in this RAM will be addressed as C001H.

•The last address in this RAM is C7FFH.

•Hence, for the chip select circuit, the address range will be from C000H – C7FFH.

•If the 8085 sends out an address that is outside the range of C000H – C7FFH, the

chip does not get selected at all.



120


• Note that there is nothing like a unique chip select circuit.

•The chip select circuit shown below also serves the same purpose as specified earlier.

•The address range, C000H – C7FFH.

• Another thing to note is that the starting address should be exactly divisible by the

size of the memory chip.

•For example, a 2K X 8 RAM chip can have any starting address that is divisible by

800H = 2K.



121


•Thus, possible starting addresses for a 2K X 8 RAM are 0000H, 0800H, 1000H,…,

F800H.

•Suppose we have the chip select circuit as shown below, then what is the address

range for the RAM?

• In this case, A15 and A14 are used in selecting the RAM, and A10-0 selects a location

in RAM.

•But A13, A12 and A11 can have any value. They have no role to play in chip selection, or

selecting a location in the RAM.



122


•There are eight possible values for A13-11, and as such we will have eight different

address ranges possible for the RAM.



123


•Thus location 0 in this 2K X 8 RAM can be addressed by the 8085 as any of the eight

memory locations C000H, C800H, D000H, D800H, E000H, E800H, F000H, F800H.

•In other words, every location has multiple addresses.

•This kind of chip selection where we have some don’t care values for address

lines is called partially decoded addressing.

•Its disadvantage is that just 2K locations of physical memory have occupied 16K

locations of address space.

•But the advantage of partially decoded addressing is that the chip select circuit is quite

simple.

•If all the address lines are used for selecting a memory chip, and for selecting a

location in that memory chip, it is called ―fully decoded addressing‖.

•Advantage: 2K locations of physical memory occupy only 2K locations of address

space.

•Disadvantage: Chip select circuit is quite complex.



124

Memory Interfacing : 74138 Decoder IC to generate Chip Select Signal

•Let us consider a 3 to 8 decoder IC 74138.

•It is a 16-pin IC.



125


•Depending on the inputs I2, I1, I0, only one of the output lines is activated.

•The 74138 chip is selected when E1*=0, E2*=0 and E3=1.

•If this condition is not satisfied then all the output lines will be in the 1 state.

•In other words, if the chip is selected, then depending on the inputs I2, I1 and I0, one

of the output line will become 0.

•This IC can be used to generate chip select signals for up to eight chips in a

microcomputer system.

•Example: Suppose we have eight number of 1K X 8 EPROM chips.

•The starting address for these chips are 2000H, 2400H, 2800H,…, 3C00H, respectively



126


• The starting address for EPROM-0 is,

• EPROM-7 is selected using,



127


•If we do not use 74138, then we must have separate chip select circuits for each of

the eight chips, which will be more expensive as well as more complex.

•Suppose we want the EPROMS to have the starting addresses as 4000H, 4400H,…,

5C00H.

•In such a case, the 74138 has to be selected for the conditionA15, A14, A13 = 010.



128

I/O Interfacing :

•CPU and main memory are very fast compared with electromechanical input or

output devices like printers, etc.

•In such case, it is essential that the data lines of the computer are not kept

engaged for a long time during communication with I/O devices.

•Otherwise, the overall speed of the computer system comes down drastically.

•So I/O devices are connected to a computer through I/O ports.

•For example, to communicate with a printer, the CPU loads the output port connected

to the printer at electronic speeds. The printer slowly prints it.

•When the printer has finished printing, the output port requests the CPU for further data.

•This way, the CPU is allowed to work at its full speed, with no degradation in the overall

speed of the computer system.

•To further improve the speed, a printer will have printer buffer.

•Thus I/O devices are never directly connected to a computer. Computer and an

I/O device always communicate with an I/O port as the middleman.



129

I/O Interfacing : Comparison of I/O Port chip and Memory chip

1. An I/O port chip also stores information like a memory chip.

•But an I/O port chip generally stores only 1 byte of information, and some I/O chips

store a few bytes of information.

•However, memory chips contain a large number of memory locations like 1 K, 4 K,

8 K, etc. A location within a memory chip is selected by the address pins An-0.

2. An I/O port chip will have eight lines for communication with the

microprocessor, and another eight lines for communication with the I/O device.

• An I/O port only acts as a buffer between the microprocessor and the I/O device.

•But, a memory chip will have only eight lines for communication with the

microprocessor.

3. Many I/O port chips are programmable. That is, the user can decide the way the

I/O port should work in the system (Input port or Output port).

•I/O ports can be operated in several modes like basic I/O, handshake I/O etc.

•But memory chips are only storage chips, and as such are not programmable.



130




131




132

I/O Instruction Set – IN and OUT Instructions

•Two instructions (IN and OUT instructions) in 8085 for communication with I/O ports

•IN a8 - INput to Accumulator from the contents of input port whose 8-bit address is

indicated in the instruction as a8.

•It occupies 2 bytes in memory. First byte – Opcode, Second byte – 8-bit port address

•Example: IN EFH



133


•A possible chip select circuit to connect an input port with an address as EFH is

shown below.



134


•OUT a8 - OUTput Accumulator contents to an output port whose 8-bit address is

indicated in the instruction as a8.

•It occupies 2 bytes in memory. First byte – Opcode, Second byte – 8-bit port address

•Example: OUT EFH



135


•A possible chip select circuit to connect an output port with an address as EFH is

shown below.

•Notice that it is possible to have an input port with the address EFH, and an output

port with the same address EFH.

•When the 8085 send out the address as EFH and IO/M* as 1, only one of them is

selected based on the RD* and WR* signals.

•Thus it is possible to have a total of 256 input ports and total of 256 output ports.



136

I/O Interfacing : Memory-mapped I/O

•It is possible to address an I/O port as if it were a memory location.

•For example, let us say, the chip select pin of an I/O port chip is activated when

address = FFF0H, IO/M* = 0, and RD* = 0.



137


•The I/O port chip is selected when the 8085 is thinking that it is addressing

memory location FFF0H for a read operation.

•Note: 8085 thinks that it is addressing a memory location because it has sent out IO/M*

as a logic 0.

•But in reality, an input port has been selected, and the input port supplies information to

the 8085.

•Such I/O ports that are addressed by the processor as if they were memory

locations are called memory-mapped I/O ports.



138


•6800 Processor supports memory-mapped I/O.



139

I/O Interfacing : I/O-mapped I/O

•Generally, a processor like 8085 addresses an I/O port by sending out 8-bit port

address and IO/M* = 1.

•For example, the chip select of an I/O port chip is activated when 8-bit address =

F0H, IO/M* = 1, and RD* = 0.

•Such I/O ports, which are addressed by the processor by sending out IO/M* as

logic 1 are called as I/O-mapped I/O ports.



140

I/O Interfacing : Comparison of Memory-mapped I/O and I/O-mapped I/O

1. IN and OUT instructions are used for addressing I/O-mapped I/O ports. The

mnemonics of these instructions clearly indicate that the processor communicates with

an I/O port.

• To load accumulator from memory-mapped input port with address FFF0H, we

have to execute LDA FFF0H instruction.

2. Some microprocessors have a control pin to select a memory location or an I/O

port.

• Example: 8085 microprocessor – IO/M* pin is used to select an I/O port or a memory

location.

• In other words, there are two separate address spaces – one for I/O ports and

another for memory.



141




142


3. The I/O address space has only 256 locations, as I/O port addresses are only 8

bits in size in 8085.

•The memory address space has 64K locations, as memory addresses are 16-bits.

•Thus it is possible to have full 64K space exclusively for memory, if we prefer to

use I/O-mapped I/O scheme for addressing I/O ports.

•It is possible to have an I/O-mapped I/O port with the address 67H, and also have a

memory location with the address 0067H.

4. If we connect I/O ports as memory-mapped ports with addresses in the range of

FF00H – FFF0H, then we should not allot this address range to any memory chip.

•If memory and a memory-mapped I/O port have the same address, both get

selected simultaneously, and this can damage the processor, the memory chip,

and the I/O port chip. Thus with memory-mapped I/O, the entire 64K address space (in

case of 8085) is not available for memory. This is because some address space is lost to

memory-mapped I/O ports.



143

I/O Interfacing : Demerits of I/O-mapped I/O and Merits of Memory-mapped I/O

1. Only IN and OUT instructions are used for addressing I/O-mapped I/O ports. But

a large number of instructions can be used for communication with a memory-

mapped I/O port.

2. The designer of a microprocessor is required to produce a chip design with minimum

possible pins. If I/O-mapped I/O facility is needed, then there must be a pin of the

kind IO/M*, to distinguish between I/O addressing and memory addressing.

3. Using I/O-mapped I/O, only accumulator can communicate with an I/O port. But

using memory-mapped I/O any register can communicate with the memory-

mapped I/O port.

4. Using I/O-mapped I/O, only data transfer operation is possible between

accumulator and an I/O port. They are done using the IN and OUT instructions. But

using memory-mapped I/O, even arithmetic and logical operations can be

performed.



144

I/O Interfacing : Demerits of I/O-mapped I/O and Merits of Memory-mapped I/O

5. Using I/O-mapped I/O, only 256 input ports and 256 output ports could be

addressed in a 8085, as an I/O port address is only 8-bits wide. But, using

memory-mapped I/O, even up to 64K I/O ports can be addressed in a 8085

system, as memory addresses are 16-bits wide. However, this will be at a cost of

corresponding reduction in memory addressing capability.



145

Interrupts in 8085:

• When the 8085 is executing a program, it can get interrupted half way through the

program by an I/O device.

•An I/O device interrupts the working of the processor, because it may want to

urgently communicate with the processor.

•It may want to send some information to the processor, or receive some information

from the processor.

•A microprocessor does not directly communicate with an I/O device.

•It communicates with an I/O device via an I/O port.

•Data transfer can be in parallel or serial form.

•Parallel data transfer is possible using programmed I/O or Direct Memory Access

(DMA).



146

Interrupts in 8085:

•There are three different ways a microprocessor can communicate with an I/O port for

parallel data transfer with programmed I/O. They are,

1. Basic or simple data transfer

2. Status check data transfer

3. Interrupt-driven data transfer.



147

Interrupts in 8085: Basic or Simple Data Transfer

•This method is useful when we have accurate knowledge of the I/O device timing

characteristics.

•When we know that the device is ready for data transfer, we execute IN or OUT

instruction, depending on the required direction of data transfer. When the I/O port is

connected in the system as an I/O-mapped I/O port.

•If the port is connected as a memory-mapped I/O port, ‗MOV M, A’, ‘MOV A, M’, or

any other memory reference instruction is used depending on the direction of data

transfer.

•The advantage of simple I/O is its simplicity, but its disadvantage is that it is not very

efficient.



148

Interrupts in 8085: Basic or Simple Data Transfer



149

Interrupts in 8085: Status Check Data Transfer

•This method is useful when we do not have accurate knowledge of the I/O device

timing characteristics.

•The processor should get status information about the readiness of the I/O device

for data transfer.

•Generally, the processor will be in a loop checking for the readiness of the device.

•The moment the device is ready, it comes out of the loop, and executes IN or OUT

instruction depending on the requirement.

•In this case, the processor has simply wasted its time in a loop till the device got ready.

•Status check I/O is more efficient than simple I/O, but is more complex.

•This method of data transfer is also known as handshake data transfer.



150

Interrupts in 8085: Status Check Data Transfer



151

Interrupts in 8085: Interrupt-Driven Data Transfer

•This method is useful when we do not have accurate knowledge of the I/O device

timing characteristics, except that it takes quite a long time for the device to get

ready.

• If we resort to status check data transfer, the processor will have to waste a long time

in the loop for the device to get ready.

•To avoid this problem, interrupt-driven data transfer can be used.

•In this case, the processor will go ahead with its required work, and whenever the

device gets ready for data transfer, the corresponding I/O port will send a interrupt

request signal to the processor.

•The interrupt request may arrive even half way through an instruction execution.

•Then the processor will complete the instruction. After this, processor will perform data

transfer with the I/O device using IN or OUT instruction. Then it resumes the execution

of the interrupted program. The advantage of this method is that the processor is not

wasting its time in a loop checking for the readiness of the I/O device.



152

Interrupts in 8085: Interrupt-Driven Data Transfer



153

Interrupts in 8085:

•Interrupt pins of 8085 are used by I/O devices to initiate transfer of data to or from 8085,

without wasting much of the CPU time.

•There are five interrupt pins on 8085.

•They are input pins of 8085.

•They are TRAP, RST7.5, RST6.5, RST5.5 and INTR.



154

Interrupts in 8085:

•Note that RST7, RST6 and RST5 are instructions of 8085, whereas RST7.5, RST6.5

and RST5.5 are interrupt pins of 8085.

•An interrupt pin can be activated by an I/O port even half way through an

instruction, without having any relation to a clock signal.

•Thus the interrupts are asynchronous in nature.

•The 8085 checks all these interrupt pins at about the end of every instruction.

•Specifically, they are checked in the penultimate clock cycle of the last machine

cycle of an instruction.

•However, the interrupt pins are not checked at the end of an instruction, if the

instruction belongs to the branch group, JMP, CALL, RET etc.

•In such cases,, the interrupt requests are sensed after a lapse of about 15 clock

cycles.

•At this point, if several interrupts are active simultaneously, the 8085 services

them as per the priority shown in the table as follows.



155

Interrupts in 8085:

• When an I/O port activates one of these pins, the 8085 gets interrupted if each of

the following conditions are satisfied.

1. The interrupt system is enable by setting the interrupt enable (IE) flip-flop of 8085.

This condition is not applicable to TRAP.

2. The interrupt pin has not been masked. This condition is not applicable to TRAP and

INTR.

3. Higher priority interrupts are not active at the same time.



156

Interrupts in 8085:

• Action taken by the 8085 when it gets interrupted.

1. It completes the execution of the current instruction.

2. Stores on the stack top the address of the next instruction, called Return address,

which is present in the program counter.

3. Program branches to a subroutine, whose execution satisfies the I/O device that

interrupted the 8085. This subroutine is named as an interrupt service subroutine

or ISS.

4. Normally an ISS consists of three portions. The first portion is used for saving on

the stack all the register values of 8085 that are going to be affected by the execution

of the ISS. Thus it uses a number of PUSH instructions. The next portion will have

instructions to achieve the actual purpose of the ISS. The last part is used for

restoring the original values to various registers that were affected by the second part

of ISS. As such it contains a number of POP instructions. The ISS then ends with EI

(Enable Interrupt) and RET (Return)instructions.



157

Interrupts in 8085:

5. After completely executing the ISS, the control returns to the program that was

interrupted. This is done by popping the top of stack information to the PC, using RET

instruction at the end of ISS.



158

Interrupts in 8085:

• 8085 has five internal interrupt signals that correspond to the five external

interrupt pins.

•Only when the internal interrupt signal is activated, the 8085 gets interrupted,

provided higher priority internal interrupt signals are not active at the same time.

•The 8085 checks all these internal interrupt signals in the penultimate clock cycle

of the last machine cycle of an instruction.

•There is a flip-flop in 8085 called IE (Interrupt Enable) flip-flop.

•When this flip-flop is reset to the 0 state, 8085 interrupt system is disabled.

•That is, even if an external interrupt pin is activated, the corresponding internal

interrupt signal is not activated.

•This flip-flop state has nothing to do with the internal interrupt signal

corresponding to TRAP.

•TRAP is a non-maskable interrupt. It means whenever the external TRAP pin is

activated, the corresponding internal interrupt signal is always activated.



159

Interrupts in 8085:



160

Interrupts in 8085:

• Further, TRAP being the highest priority interrupt, it always interrupts the 8085.

•The IE flip-flop is reset to the 0 state by the following three conditions.

1. Execution of DI instruction

2. Recognition of an interrupt request

3. Resetting of 8085.

• DI instruction stands for ‗disable interrupts‘.

•It is an 1-byte instruction.

•When this instruction is executed, the IE flip-flop is reset. This disables the 8085

interrupt system except for the TRAP pin.

•When the 8085 recognizes an interrupt, it branches to an ISS.

•In the ISS, the 8085 would not like to be interrupted again. That is the reason, as to why

the 8085 will place itself in DI state, when it recognizes an interrupt.

•However, TRAP can still interrupt an ISS.



161

Interrupts in 8085:

•Thus when the control is transferred to an ISS, interrupt system is disabled

automatically.

•Accordingly, there is no need for the programmer to write a DI instruction at the

beginning of an ISS.

•Whether the programmer writes a DI instruction at the beginning of an ISS or not,

interrupt system remains disabled, except for TRAP.

•Setting of IE flip-flop to 1 is by executing the EI instruction.

•The EI instruction stands for ‗enable interrupts‘.

•It is an 1-byte instruction.

•When this instruction is executed, the IE flip-flop is set to 1. This enables the 8085

interrupt system.

•But the interrupts will be enabled only after the next instruction after EI is

executed.



162

Interrupts in 8085:

•The reason is as follows,

1. When the 8085 branches to an ISS, the interrupt system is disabled

automatically. Thus before we come out of the ISS, it is necessary to again

enable the interrupt system using EI instruction. Otherwise, when the control is

back with the interrupted program, it cannot be interrupted again, except by TRAP.

But immediately after EI, the interrupt system should not get enabled. If it gets

enabled, there is the danger of branching to another ISS before the RET instruction

in the current ISS is executed. To overcome this problem, the interrupt system gets

enabled only after one instruction is executed subsequent to the execution of

the EI instruction.

2. Thus, if we end an ISS with EI followed by RET, the interrupt system is enabled

only when the control is back with the interrupted program.



163

Interrupts in 8085: Masking of Interrupts

•In 8085 microprocessor masking of interrupt can be done for four hardware

interrupts INTR, RST 5.5, RST 6.5, and RST 7.5.



164


1.The maskable interrupts are by default masked by the Reset signal. So no interrupt is

recognized by the hardware reset.

2.The interrupts can be enabled by the EI instruction.

3.The three RST interrupts can be selectively masked by loading the appropriate word in

the accumulator and executing SIM instruction. This is called software masking.

4. All maskable interrupts are disabled whenever an interrupt is recognized.

5. All maskable interrupts can be disabled by executing the DI instruction.



165


•SIM Instruction: The SIM instruction is used to mask or unmask RST hardware

interrupts. When executed, the SIM instruction reads the content of accumulator

and accordingly mask or unmask the interrupts. The format of control word to be

stored in the accumulator before executing SIM instruction is as shown below,

• In addition to masking interrupts, SIM instruction can be used to send serial data on

the SOD line of the processor. The data to be send is placed in the MSB bit of the

accumulator and the serial data output is enabled by making D6 bit to 1.



166


•RIM Instruction: RIM instruction is used to read the status of the interrupt mask

bits. When RIM instruction is executed, the accumulator is loaded with the current

status of the interrupt masks and the pending interrupts. The format and the

meaning of the data stored in the accumulator after execution of RIM instruction is

shown below,

• In addition, RIM instruction is also used to read the serial data on the SID pin of the

processor. The data on the SID pin is stored in the MSB of the accumulator after

the execution of the RIM instruction.



167

Interrupts in 8085: INTR and INTA* pins

• INTR is an active high input pin.

•Lowest priority.

•It is level sensitive input.

•The line should remain high till the 8085 checks the internal interrupt signal

corresponding to INTR at about the end of an instruction.

•The INTR internal interrupt signal is activated only when INTR pin is in logic 1 state

and IE flip-flop is in logic 1 state.

•The 8085 gets interrupted because of INTR pin, only if the following conditions are,

1. INTR internal interrupt signal is active

2. Higher priority internal interrupt signals are not active at the same time.

• Without EI instruction in the main program, the main program will never be interrupted

by any of the 8085 interrupts, except TRAP.

•INTR is a non-vectored interrupt in 8085. This means that the 8085 does not know

by itself the starting address of the ISS.



168


• It has to be provided to the 8085 by an external I/O port, or by an interrupt

controller like Intel 8259.

•The action taken by the 8085 when INTR pin is activated is detailed in the following.

1. In the penultimate clock cycle of the last machine cycle of every instruction,

the 8085 senses all the internal interrupt signals.

2. If INTR internal signal is at logic 1, the 8085 enters a interrupt acknowledge

(INA) machine cycle.

3. The interrupt from the I/O port is acknowledged by the 8085 by activating INTA*

pin in the T2 state of the INA machine cycle. INTA* is an active low pin. In

response to INTA*, the interrupting port should send code for CALL instruction

to IR register of 8085 on AD7-0 pins. Intel 8259 interrupt controller is capable of

sending such a CALL instruction to 8085. INTA* signal becomes 1 after the 8085

receives the code for CALL and decodes it, uses six T states.



169


4. In M2 machine cycle, is an INA machine cycle, LS byte of ISS address is

transferred to the Z register of 8085 by the 8259. This will be in response to activation

of INTA* during T2. This machine cycle uses only three T states, as the 8085 does not

have to decode this information.

5. In M3 machine cycle, is an INA machine cycle, MS byte of ISS address is

transferred to the W register of 8085 by the 8259. In response to activation of INTA*

during T2. Now the 8085 has received the complete ISS address. After this, save on

the stack top the return address available in PC, before branching to the ISS.

6. In M4, which is a MW (Wait Machine Cycle) machine cycle, MS byte of the PC is

pushed onto the stack. This takes three T states.

7. In M5, which is also a MW machine cycle, LS byte of PC is pushed onto the stack.

At this point, the address specified in the CALL instruction, which is present in the

WZ register pair, is moved to the PC. All this takes three T states. Starts the ISS

execution.



170




171


• It can be noticed that, after completion of the instruction during which the 8085 got

interrupted, it takes 6 + 3 + 3 + 3 + 3 = 18 T states before the 8085 transfers control to

the ISS.



172

Interrupts in 8085: RST5.5 and RST6.5 pins

•RST5.5 and RST6.5 are level-sensitive inputs.

•RST6.5 has higher priority than RST5.5.

•RST5.5 has higher priority than INTR.

•These pins should remain high till the 8085 checks all the internal interrupt signals at

about the end of an instruction.

•Both internal interrupt signals are activated only when,

1. These external interrupt pins are in logic 1 state

2. IE flip-flop is in logic 1 state.

3. These interrupts are not masked by the SIM instruction.

• The 8085 gets interrupted because of RST5.5 or RST6.5, only if the following

conditions are met,

1. RST5.5 or RST6.5 internal interrupt signal is active

2. Higher priority internal interrupt signals are not active.



173

Interrupts in 8085: RST5.5 and RST6.5 pins

•RST5.5 and RST6.5 are vectored interrupts in 8085. This mean that the 8085 knows

by itself the starting address of the ISS. It is 5.5*8=002CH incase of RST5.5, and

6.5*8=0034H in case of RST6.5.

•Generally at locations 002Ch and 0034H, we will not have the ISS. This location

will have a JMP a16 instruction, where a16 points to the ISS address.



174

Interrupts in 8085: RST7.5 pin

•RST7.5 is an edge-sensitive inputs.

•This is used by peripherals that send a pulse, rather than a sustained high level, for

interrupting the processor.

•Internal to 8085 there is a flip-flop connected to RST7.5 interrupt pin.

•This flip-flop is set to 1, when a positive going edge occurs on RST7.5 input.

•RST7.5 has higher priority than RST6.5, RST5.5 and INTR.

•RST7.5 internal interrupt signals are activated only when,

1. Q output of the RST7.5 flip-flop is at logic 1

2. IE flip-flop is in logic 1 state.

3. These interrupts are not masked by the SIM instruction.

• The 8085 gets interrupted because of RST7.5, only if the following conditions are

met,

1. RST7.5 internal interrupt signal is active

2. TRAP internal interrupt signals is not active.



175

Interrupts in 8085: RST7.5 pin

•RST7.5 is a vectored interrupts in 8085. This mean that the 8085 knows by itself the

starting address of the ISS. It is 7.5*8=003CH.

•Generally at locations 003CH, we will not have the ISS. This location will have a

JMP a16 instruction, where a16 points to the ISS address.

•There is no pin of 8085 that can be used to reset the RST7.5 flip-flop.

•So, RST7.5 flip-flop has to be reset by software.

•SIM instruction is used to reset the RST7.5 flip-flop.

•Also, the moment when the 8085 recognizes RST7.5 interrupt request and

branches to ISS, the RST7.5 flip-flop is automatically reset to 0.



176

Interrupts in 8085: TRAP pin

•TRAP is a non-maskable interrupt.

•Whenever this pin is activated, the 8085 will always get interrupted, even if the

8085 is in DI state.

•TRAP input is both edge- and level-sensitive.

•Thus the TRAP line must make a transition from 0 to 1, and must remain in 1 state

till the end of the execution of an instruction in order to interrupt the 8085.

•Internal to 8085 there is a flip-flop connected to the TRAP interrupt pin.

•Higher priority compared to all the other interrupts in 8085.

•The moment when the 8085 recognizes TRAP interrupt request and branches to

ISS, the TRAP flip-flop is automatically reset to 0.

•It is also reset by activation of reset input of 8085.

•TRAP is a vectored-interrupt in 8085. The 8085 knows by itself the starting

address of the ISS as 4.5*8 = 0024H.



177

Interrupts in 8085: TRAP pin

•Generally at locations 0024H, we will not have the ISS. This location will have a

JMP a16 instruction, where a16 points to the ISS address.



178

Timing Diagrams

•To know the working of 8085 microprocessor, we should know the timing diagram

of 8085 microprocessor.

•Before we go for timing diagram of 8085 microprocessor we should know some basic

parameters to draw timing diagram of 8085 microprocessor. Those parameters are

1. Instruction Cycle: Instruction cycle is the total time taken for completing one

instruction execution.

2. Machine Cycle: Machine cycle is the time required to complete one operation

such as accessing either the memory or an I/O device.

3. T-state: T-state is the time corresponding to one clock period. It is a basic unit

used to calculate the time taken for execution of instructions and programs in a

processor.



179

Timing Diagrams

•We also have to know five control signal to understand timing diagram of 8085

microprocessor.



180

Timing Diagrams : Opcode Fetch Machine Cycle

•The lower byte of address (AD0 – AD7) is available on the multiplexed

address/data bus during T1 state of each machine cycle, except during the bus idle

machine cycle.

•The higher byte of address (A8 – A15) is available during T1 to T3 states of each

machine cycle, except during the bus idle machine cycle.

•The first machine cycle of every instruction is the Opcode Fetch. This indicates the

kind of instruction to be executed by the system.

•The length of this machine cycle varies between 4T to 6T states—it depends on the

type of instruction.

•In this, the processor places the contents of the PC on the address lines,

identifies the nature of machine cycle by IO/M*, S0, S1 and activates the ALE

signal. All these occur in T1 State.

•In T2 state, RD* signal is activated so that the identified memory location is read

from and places the content on the data bus (D0 – D7).



181


•In T3, data on the data bus is put into the instruction register (IR) and also raises

the RD* signal thereby disabling the memory.

•In T4, the processor takes the decision, on the basis of decoding the IR, whether

to enter into T5 and T6 or to enter T1 of the next machine cycle.

•One byte instructions that operate on eight bit data are executed in T4.

•Examples: ADD B; MOV C, B; RRC; DCR C etc.



182




183

Timing Diagrams : Memory Read and Memory Write Machine Cycles

•Both the Memory Read and Memory Write machine cycles are 3T states in length.

•In Memory Read, the contents of RAM memory (including stack also) or ROM are

read while in Memory Write, it stores data into data memory.

•During T2 and T3 states data from either memory or CPU are made available in

Memory Read or Memory Write machine cycles, respectively.

•The status signal (IO/ M*, S0, S1) states are complementary in nature in Memory

Read and Memory Write cycles.

•Reading or writing operations are performed in T2.

•In T3 of Memory Read, data from data bus are placed into the specified register

(A,B, C, etc.) and raises RD* so that memory is disabled while in T3 of Memory

Write WR* signal is raised which disables the memory.



184

Timing Diagrams : Memory Read and Memory Write Machine Cycles



185

Timing Diagrams : I/O Read Machine Cycle

•8085 executes this cycle to read the data from I/O device.

•The length of this machine cycle is 3T states (T1- T3).

•The IN instruction uses this machine cycle during the execution.

•In State T1, the microprocessor places the address on the address lines from

stack pointer, general purpose register pair or program counter and then activates

the ALE signal for latching the low-byte of address.

•Also, the microprocessor sends status signals: IO/M* = 1, S1 = 1, and S0 = 0 (for

I/O read machine cycle).

•In State T2, the microprocessor sends RD* signal low to enable addressed

memory location. Then I/O device places data on the data bus (AD0-AD7).

•In State T3, the 8085 loads the data from the data bus into the specified register

(A, B, C, D, E, H, and L) and raises RD* to high which disables the I/O device.



186

Timing Diagrams : I/O Write Machine Cycle

•8085 executes this cycle to store the data into data I/O device.

•The length of this machine cycle is 3T states (T1-T3).

•The OUT instruction uses this machine cycle during the execution.

•In State T1, microprocessor places the address on the address lines from stack

pointer, general purpose register pair and then activates the ALE signal for latching

the low-byte of address.

•Also, the microprocessor sends status signals: IO/M*=1, S1 = 0, and S0 = 1 (for I/O

write machine cycle).

•In State T2, the microprocessor places the data on the data bus and sends WR*

signal low for writing into the addressed I/O device.

•In State T3, the 8085 writes (stores) the data from the data bus into addressed I/O

device and raises WR* to high which disables the I/O device and terminates the

write operation.



187

Timing Diagrams : I/O Read and I/O Write Machine Cycles



188

Timing Diagrams : MVI M, d8

• In 8085 Instruction set, this instruction MVI M, d8 is used to load a memory location

pointed by HL pair with an 8-bit value.

•This instruction uses immediate addressing for specifying the data.

•It occupies 2-bytes in memory.

•Let us consider, MVI M, ABH as an example instruction of this type.

•It is a 2-byte instruction, with opcode for MVI M using up one Byte, and ABH using

up another more byte.

•We are considering that HL register pair is containing 16-bit address 4050H and

content of that address initially CDH.

•So after execution of the instruction the updated values will be ABH.



Address Hex Codes Mnemonic Comment

2006 36 MOV M, ABH Content of the memory location pointer by HL register pair will get updated by ABH

2007 AB Operand ABH

189

Timing Diagrams : MVI M, d8

• So this instruction MVI M, ABH requires 2-bytes, 3-Machine Cycles (Opcode Fetch,

Memory Read, Memory Write) and 10 T-States for execution as shown in the timing

diagram.



190

Timing Diagrams : DCX SP

• In 8085 Instruction set, DCX SP instruction is used to decrement the SP contents by

1.

•DCX SP instruction is a special case of DCX rp instruction which decreases the

content of the register pair.

•This instruction occupies only 1-byte in memory.

•Let us consider that the initial content of SP is 4050H.

•So after decrement of the content of SP by using DCX SP instruction, SP would have

the value 404FH. Here is the required tracing table as below –



Address Hex Codes Mnemonic Comment

2003 3B DCX SP SP <-SP – 1

191

Timing Diagrams : DCX SP

• So this instruction DCX SP requires 1-Byte, 1-Machine Cycle (Opcode Fetch) and 6

T-States for execution as shown in the timing diagram.



192

Timing Diagrams : CALL a16

•M1 (Machine cycle 1) is used for fetching the opcode of CALL instruction

•M2 and M3 machine cycles are required to call the 2 bytes of the address following

the CALL.

•Memory write are done in machine cycles M4 and M5 in which contents of PC are

stored in stack and then a new instruction cycle begins.

•So this instruction CALL a16 requires 3-bytes, 5-Machine Cycles (Opcode Fetch,

Memory Read, Memory Read, Memory Write, Memory Write) and 18 T-States for

execution as shown in the timing diagram.



193

Timing Diagrams : CALL a16



RD*

194

Timing Diagrams : RET

• RET is used when program control is sent from a subroutine back to its parent

routine.

•First we look into its Machine Code,

1. Opcode Fetch (4T) without doing anything to stack pointer.

2. Memory Read(3T): Reads part of the address of the place to return to. This is

where it was stored by CALL when calling the subroutine… SP++

3. Memory Read (3T): Reads the remaining part of the address of the place to

return to. The address is 16-bit and hence needs 2 places to store it, hence 2 places

to read from… SP++.

•So this instruction RET requires 1-byte, 3-Machine Cycles (Opcode Fetch, Memory

Read, Memory Read) and 10 T-States for execution as shown in the timing diagram.



195

Timing Diagrams : RET



196

Summary

1. Architecture of 8085

2. Pin details of 8085

3. Instruction Set and Addressing Modes

4. Memory Interfacing

5. I/O Interfacing

6. Interrupts in 8085

7. Timing Diagram



Documents

EC7451: MICROPROCESSOR AND … I - 8085...2. Receiving a data byte from an input port or from memory 3. Sending out a byte to an output port or to memory. EC7451: MICROPROCESSOR AND