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EEC 581

Computer Architecture

Lecture 1 Review – MIPS

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Supercomputing: Suddenly Fancy

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Instructions:

Language of the Machine

More primitive than higher level languagese.g., no sophisticated control flow

Very restrictivee.g., MIPS Arithmetic Instructions

We’ll be working with the MIPS instruction set architecture (some of you have done this in 2030)

a representative of Reduced Instruction Set Computer (RISC)

similar to other architectures developed since the 1980's

used by NEC, Nintendo, Silicon Graphics, Sony

Design goals: Maximize performance and Minimize cost, Reduce design time

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MIPS arithmetic

All instructions have 3 operands

Operand order is fixed (destination first)

Example:

C code: A = B + C

MIPS code: add $s0, $s1, $s2

(associated with variables by compiler)

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MIPS arithmetic

Design Principle: simplicity favors regularity.

Of course this complicates some things...

C code: A = B + C + D;

E = F - A;

MIPS code: add $t0, $s1, $s2

add $s0, $t0, $s3

sub $s4, $s5, $s0

Operands must be registers, only 32 registers provided

All memory accesses are accomplished via loads and stores

A common feature of RISC processors

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Registers vs. Memory

Processor I/O

Control

Datapath

Memory

Input

Output

Arithmetic instructions operands must be registers,

— only 32 registers provided

Compiler associates variables with registers

What about programs with lots of variables

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Memory Organization

Viewed as a large, single-dimension array, with an

address.

A memory address is an index into the array

"Byte addressing" means that the index points to a

byte of memory.

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

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Memory Organization

Bytes are nice, but most data items use larger "words“

MIPS provides lw/lh/lb and sw/sh/sb instructions

For MIPS, a word is 32 bits or 4 bytes.

(Intel’s word=16 bits and double word or dword=32bits)

232 bytes with byte addresses from 0 to 232-1

230 words with byte addresses 0, 4, 8, ... 232-4

Words are aligned

i.e., what are the least 2 significant bits of a word address?

0

4

8

12

...

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Registers hold 32 bits of data

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Endianness [defined by Danny Cohen 1981]

Byte ordering How a multiple byte data word stored in memory

Endianness (from Gulliver’s Travels) Big Endian

Most significant byte of a multi-byte word is stored at the lowestmemory address

e.g. Sun Sparc, PowerPC

Little Endian

Least significant byte of a multi-byte word is stored at the lowestmemory address

e.g. Intel x86

Some embedded & DSP processors would support both for interoperability

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Example of Endian

Store 0x87654321 at address 0x0000, byte-addressable

0x87

0x65

0x43

0x21

LowerMemoryAddress

HigherMemoryAddress

0x0000

0x0001

0x0002

0x0003

BIG ENDIAN

0x21

0x43

0x65

0x87

LowerMemoryAddress

HigherMemoryAddress

0x0000

0x0001

0x0002

0x0003

LITTLE ENDIAN

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Instructions

Load and store instructions

Example:

C code: long A[100];

A[9] = h + A[8];

MIPS code: lw $t0, 32($s3)

add $t0, $s2, $t0

sw $t0, 36($s3)

Store word has destination last

Remember arithmetic operands are registers, not memory!

32 bits of data

32 bits of data

32 bits of data

32 bits of data

A[0]

A[1]

A[2]

4 bytes

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Our First Example

MIPS Software Convention

$4, $5, $6, $7 are used for passing arguments

swap(int v[], int k);

{

int temp;

temp = v[k]

v[k] = v[k+1];

v[k+1] = temp;

}

swap:

muli $2, $5, 4

add $2, $4, $2

lw $15, 0($2)

lw $16, 4($2)

sw $16, 0($2)

sw $15, 4($2)

jr $31

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# Main guts of the program:muli $2, $5, 4 # reg $2 = k * 4 ... see later for muli add $2, $4, $2 # reg $2 = v(array base address) + k*4

# reg $2 now has the address of v[k] lw $15, 0($2) # reg $15 (temp) = v[k] lw $16, 4($2) # reg $16 = v[k+1] ... next element of v sw $16, 0($2) # v[k] = reg $16 = v[k+1] sw $15, 4($2) # v[k+1] = reg $15 = temp = v[k]

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So far we’ve learned:

MIPS

— loading words but addressing bytes

— arithmetic on registers only

Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3

lw $s1, 100($s2) $s1 = Memory[$s2+100]

sw $s1, 100($s2) Memory[$s2+100] = $s1

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Software Conventions for MIPS Registers

Register Names Usage by Software Convention

$0 $zero Hardwired to zero

$1 $at Reserved by assembler

$2 - $3 $v0 - $v1 Function return result registers

$4 - $7 $a0 - $a3 Function passing argument value registers

$8 - $15 $t0 - $t7 Temporary registers, caller saved

$16 - $23 $s0 - $s7 Saved registers, callee saved

$24 - $25 $t8 - $t9 Temporary registers, caller saved

$26 - $27 $k0 - $k1 Reserved for OS kernel

$28 $gp Global pointer

$29 $sp Stack pointer

$30 $fp Frame pointer

$31 $ra Return address (pushed by call instruction)

$hi $hi High result register (remainder/div, high word/mult)

$lo $lo Low result register (quotient/div, low word/mult)

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Instruction Format

Instruction Meaning

add $s1,$s2,$s3 $s1 = $s2 + $s3

sub $s1,$s2,$s3 $s1 = $s2 – $s3

lw $s1,100($s2) $s1 = Memory[$s2+100]

sw $s1,100($s2) Memory[$s2+100] = $s1

bne $s4,$s5,Label Next instr. is at Label if $s4 $s5

beq $s4,$s5,Label Next instr. is at Label if $s4 = $s5

j Label Next instr. is at Label

Formats:

op rs rt rd shamt funct

op rs rt 16 bit address

op 26 bit address

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Machine Language

Instructions, like registers and words of data, are also 32 bits long

Example: add $t0, $s1, $s2

registers have numbers, $t0=9, $s1=17, $s2=18

Instruction Format:

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct

Can you guess what the field names stand for?

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MIPS Encoding: R-Type

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opcode rs rt rd

26 25 21 20 16 15 11 10 6 5 0

shamt funct

0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 00 031

opcode rs rt rd

26 25 21 20 16 15 11 10 6 5 0

shamt funct

add $4, $3, $2rt

rs

rd

0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 00 0

Encoding = 0x00622020

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MIPS Encoding: R-Type

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opcode rs rt rd

26 25 21 20 16 15 11 10 6 5 0

shamt funct

sll $3, $5, 7shamt

rt

rd

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 00 031

opcode rs rt rd

26 25 21 20 16 15 11 10 6 5 0

shamt funct

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 00 0

Encoding = 0x000519C0

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Consider the load-word and store-word instructions,

What would the regularity principle have us do?

New principle: Good design demands a compromise

Introduce a new type of instruction format

I-type for data transfer instructions

other format was R-type for register

Example: lw $t0, 32($s2)

35 18 9 32

op rs rt 16 bit number

Where's the compromise?

Machine Language

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MIPS Encoding: I-Type

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opcode rs rt Immediate Value

26 25 21 20 16 15 0

lw $5, 3000($2)

Immediate

rs

rt

0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 01 0

Encoding = 0x8C450BB8

0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 01 031

opcode rs rt

26 25 21 20 16 15 0

Immediate Value

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MIPS Encoding: I-Type

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opcode rs rt Immediate Value

26 25 21 20 16 15 0

sw $5, 3000($2)

Immediate

rs

rt

1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 01 0

Encoding = 0xAC450BB8

1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 01 031

opcode rs rt

26 25 21 20 16 15 0

Immediate Value

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Instructions are bits

Programs are stored in memory

— to be read or written just like data

Fetch & Execute Cycle

Instructions are fetched and put into a special register

Bits in the register "control" the subsequent actions

Fetch the “next” instruction and continue

Processor Memory

memory for data, programs,

compilers, editors, etc.

Stored Program Concept

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Decision making instructions

alter the control flow,

i.e., change the "next" instruction to be executed

MIPS conditional branch instructions:

bne $t0, $t1, Label

beq $t0, $t1, Label

Example: if (i==j) h = i + j;

bne $s0, $s1, Label

add $s3, $s0, $s1

Label: ....

Control

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MIPS unconditional branch instructions:j label

Example:

if (i!=j) beq $s4, $s5, Lab1

h=i+j; add $s3, $s4, $s5

else j Lab2

h=i-j; Lab1: sub $s3, $s4, $s5

Lab2: ...

Can you build a simple for loop?

Example

while (A[i] == k)

i += 1;

Assume that i an k corresponds to registers $s3 and $s5, and the base of

A is in $s6.

Control

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Loop: sll $t1, $s3, 2 % Temp reg $t1 = 4*i

add $t1, $t1, $s6 % $t1 = address of A[i]

lw $to, 0($t1) % Temp reg $t0 = A[i]

bne $t0, $s5, Exit % go to Exit if A[i] ~= k

addi $s3, $s3,1 % i = i + 1

j Loop % go to Loop

Exit:

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BEQ/BNE uses I-Type

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opcode rs rt Signed Offset Value(encoded in words, e.g. 4-bytes)

26 25 21 20 16 15 0

beq $0, $9, 40

OffsetEncoded by 40/4 = 10

rt

rs

0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 00 0

Encoding = 0x1009000A

0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 00 031

opcode rs rt

26 25 21 20 16 15 0

Immediate Value

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MIPS Encoding: J-Type

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opcode Target Address

26 0

jal 0x00400030

Target

0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 00 0

Encoding = 0x0C10000C

0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 00 031

opcode

26 25 0

Target Address

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0000 0000 0100 0000 0000 0000 0011 0000XInstruction=4 bytesTarget Address

•jal will jump and push

return address in $ra ($31)•Use “jr $31” to return

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JALR and JR uses R-Type

JALR (Jump And Link Register) and JR (Jump Register)

Considered as R-type

Unconditional jump

JALR used for procedural call

0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 10 031

opcode rs 0 rd (default=31)

26 25 21 20 16 15 11 10 6 5 0

0 funct

jalr r2Or jalr r31, r2

jr r2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00 031

opcode rs 0

26 25 21 20 16 15 11 10 6 5 0

0 funct0

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We have: beq, bne, what about Branch-if-less-than?

New instruction:if $s1 < $s2 then

$t0 = 1

slt $t0, $s1, $s2 else

$t0 = 0

Can use this instruction to build "blt $s1, $s2, Label"

— can now build general control structures

For ease of assembly programmers, the assembler allows “blt” as a “pseudo-instruction”

— assembler substitutes them with valid MIPS instructions

— there are policy of use conventions for registers

blt $4 $5 loop slt $1 $4 $5

bne $1 $0 loop

Control Flow

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Small constants are used quite frequently (50% of operands)

e.g., A = A + 5;

B = B + 1;

C = C - 18;

Solutions? Why not?

put 'typical constants' in memory and load them.

create hard-wired registers (like $zero) for constants like one.

Use immediate values

MIPS Instructions:

addi $29, $29, 4

slti $8, $18, 10

andi $29, $29, 6

ori $29, $29, 4

Constants

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We'd like to be able to load a 32 bit constant into a register

Must use two instructions, new "load upper immediate" instruction

lui $t0, 1010101010101010

Then must get the lower order bits right, i.e.,

ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000

0000000000000000 1010101010101010

1010101010101010 1010101010101010

ori

1010101010101010 0000000000000000

filled with zeros

How about larger constants?

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Input/Output

Place proper arguments (e.g. system call code) to corresponding

registers and place a ‘syscall’

Print string li $v0, 4

la $a0, var

syscall

Print integer li $v0, 1

add $a0, $t0, $0

syscall

Read integer li $v0, 5 # result in $v0

Syscall

See Appendix A for more.

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Assembly provides convenient symbolic

representation

much easier than writing down numbers

e.g., destination first

Machine language is the underlying reality

e.g., destination is no longer first

Assembly can provide 'pseudoinstructions'

e.g., “move $t0, $t1” exists only in Assembly

would be implemented using “add $t0,$t1,$zero”

When considering performance you should count real

instructions

Assembly Language vs. Machine

Language

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Things we are not going to cover

support for procedures

linkers, loaders, memory layout

stacks, frames, recursion

manipulating strings and pointers

interrupts and exceptions

system calls and conventions

Some of these we'll talk about later

We've focused on architectural issues

basics of MIPS assembly language and machine code

we’ll build a processor to execute these instructions.

Other Issues

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simple instructions all 32 bits wide

very structured

only three instruction formats

rely on compiler to achieve performance

— what are the compiler's goals?Generate machine code and optimization

help compiler where we can

op rs rt rd shamt funct

op rs rt 16 bit address

op 26 bit address

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Summary of MIPS

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Instructions:

bne $t4,$t5,Label Next instruction is at Label if $t4 $t5

beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5

j Label Next instruction is at Label

Formats:

Addresses are not 32 bits

— How do we handle this with load and store instructions?

op rs rt 16 bit address

op 26 bit address

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Addresses in Branches and Jumps

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Instructions:

bne $t4,$t5,Label Next instruction is at Label if $t4$t5

beq $t4,$t5,Label Next instruction is at Label if $t4=$t5

Formats:

Could specify a register (like lw and sw) and add it to address

use Instruction Address Register (PC = program counter)

Program counter = Register + Branch Address

most branches are local (principle of locality)

Jump instructions just use high order bits of PC

Must be careful to avoid placing a program across an address

boundaries of 256 MB (64 million instructions)

26-bit field can represent 28-bit byte addressing in word addressing

mode. 28-bit -> 256 MB; 64 million instruction.

op rs rt 16 bit addressI

Addresses in Branches

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To Summarize

MIPS operands

Name Example Comments

$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform

32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is

$fp, $sp, $ra, $at reserved for the assembler to handle large constants.

Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so

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memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays,

words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

MIPS assembly language

Category Instruction Example Meaning Comments

add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants

load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register

store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register

store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory

load upper immediate lui $s1, 100$s1 = 100 * 2

16 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to

PC + 4 + 100

Equal test; PC-relative branch

Conditional

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to

PC + 4 + 100

Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1;

else $s1 = 0

Compare less than; for beq, bne

set less than

immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1;

else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return

tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

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And and $1,$2,$3 $1 = $2 & $3 Bitwise and

Or or $1,$2,$3 $1 = $2 | $3 Bitwise or

Exclusive or xor $1,$2,$3 $1 = $2 ^ $3

Nor nor $1,$2,$3 $1 = ~($2 | $3) Bitwise nor

Shift left logical sll $1,$2,CONST $1 = $2 << CONST shifts CONST number of bits to the left (multiplies by 2CONST)

Shift right logical srl $1,$2,CONST $1 = $2 >> CONST shifts CONST number of bits to the right

Logical

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Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addressing

2. Register addressing

3. Base addressing

4. PC-relative addressing

5. Pseudodirect addressing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Address

rd . . . funct

Immediate

PC

PC

+

+

Addressing Mode

Operand is constant

Operand is in register

lb $t0, 48($s0)

bne $4, $5, Label(label will be assembled into

a distance)

j Label

Concatenation w/ PC[31..28]

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Supplementary Materials

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Design alternative:

provide more powerful operations

goal is to reduce number of instructions executed

danger is a slower cycle time and/or a higher CPI

Sometimes referred to as “RISC vs. CISC”

virtually all new instruction sets since 1982 have been RISC

VAX: minimize code size, make assembly language easy

instructions from 1 to 54 bytes long!

We’ll look at PowerPC and 80x86

Alternative Architectures

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PowerPC

Indexed addressing

example: lw $t1,$a0+$s3

#$t1=Memory[$a0+$s3]

What do we have to do in MIPS?

Update addressing

update a register as part of load (for marching through

arrays)

example: lwu $t0,4($s3)

#$t0=Memory[$s3+4];$s3=$s3+4

What do we have to do in MIPS?

Others:

load multiple/store multiple

a special counter register “bc Loop”

decrement counter, if not 0 goto loop

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80x86

1978: The Intel 8086 is announced (16 bit architecture)

1980: The 8087 floating point coprocessor is added

1982: The 80286 increases address space to 24 bits, +instructions

1985: The 80386 extends to 32 bits, new addressing modes

1989-1995: The 80486, Pentium, Pentium Pro add a few instructions

(mostly designed for higher performance)

1997: MMX (SIMD-INT) is added (PPMT and P-II)

1999: SSE (single prec. SIMD-FP and cacheability instructions) is added in P-III

2001: SSE2 (double prec. SIMD-FP) is added in P4

2004: Nocona introduced (compatible with AMD64 or once called x86-64)

“This history illustrates the impact of the “golden handcuffs” of compatibility

“adding new features as someone might add clothing to a packed bag”

“an architecture that is difficult to explain and impossible to love”

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A Dominant Architecture: 80x86

See your textbook for a more detailed description

Complexity:

Instructions from 1 to 17 bytes long

one operand must act as both a source and destination

one operand can come from memory

complex addressing modes

e.g., “base or scaled index with 8 or 32 bit displacement”

Saving grace:

the most frequently used instructions are not too difficult to build

compilers avoid the portions of the architecture that are slow

“what the 80x86 lacks in style is made up in quantity,

making it beautiful from the right perspective”

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Instruction complexity is only one variable

lower instruction count vs. higher CPI / lower clock rate

Design Principles:

simplicity favors regularity

smaller is faster

good design demands compromise

make the common case fast

Instruction set architecture

a very important abstraction indeed!

Summary