EKT 221 : Digital 2EKT 221 : Digital 2Memory BasicsMemory Basics

Today’s OutlineToday’s Outline

Memory BasicsMemory BasicsMemory DefinitionsMemory DefinitionsMemory OrganizationsMemory OrganizationsRAM – Static RAM (SRAM)RAM – Static RAM (SRAM)

Memory DefinitionsMemory Definitions

Collection of cells capable of storing binary Collection of cells capable of storing binary informationinformation

Contains electronic circuits for storing & Contains electronic circuits for storing & retrieve informationretrieve information

Used to provide temporary or permanent Used to provide temporary or permanent storage capabilitystorage capability

Memory Basic ProcessMemory Basic Process

Info/content from memory is send to h/w Info/content from memory is send to h/w (usually consist of registers & combinational (usually consist of registers & combinational logic) to be processedlogic) to be processed

The processed info is then returned to the The processed info is then returned to the same or different memory addresssame or different memory address

Input and Output devices may also interact with Input and Output devices may also interact with memorymemory

MemoryHardware

forprocessing

I/O

PrintersMouse

KeyboardMonitor

Digital CameraScanners

PlottersThumb Drive

External Memory

Types of MemoriesTypes of Memories

Random Access Memory (RAM)Random Access Memory (RAM)Write operation – stores new infoWrite operation – stores new infoRead operation – transfer the stored info out Read operation – transfer the stored info out

of memoryof memoryRead Only Memory (ROM)Read Only Memory (ROM)

Perform read operation onlyPerform read operation only

Memory data elementsMemory data elements Typical data elements are:

bit : a single binary digit byte : a collection of eight (8) bits accessed together word : a collection of binary bits whose size is a typical unit of

access for the memory. (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)

Memory Data ─ a bit or a collection of bits to be stored into or accessed from memory cells.

Memory Operations ─ operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).

Memory OrganizationMemory Organization Organized as an indexed array of words. Value of the

index for each word is the memory address. Often organized to fit the needs of a particular computer

architecture. Some historically significant computer architectures and their associated memory organization: Digital Equipment Corporation PDP-8 (DEC Alpha)

used a 12-bit address to address 4096 12-bit words. IBM 360

used a 24-bit address to address 16,777,216 8-bit (bytes), or 4,194,304 - 32-bit words.

Intel 8080 (8-bit predecessor to the 8086 and the current Intel processors)

used a 16-bit address to address 65,536 8-bit (bytes).

Memory Block DiagramMemory Block Diagram

A basic memory system is shown here:

k address lines are decoded to address 2m words of memory.

Each word is n bits.

Read and Write are single control lines defining the simplest of memory operations. (Refer to next slide for example)

K Address Linem

2m Wordsn bits per Word

Memory OrganizationMemory Organization

Example of memory contents above:• address bits = 3; m = 3• data bits = 8; n = 8• Therefore number of address lines = k = (2m); 23 = 8• Address range = 0 to 2m -1; therefore 0 to 23 – 1, Address range = 0 to 7• 1 word is the size of the memory content; so the memory above has 8

words of 8-bit data

K Address Linem

2m Wordsn bits per Word

Memory OrganizationMemory OrganizationExample:

• address bits = m = 10• data bits =16; n = 16• Address line = (2m)

210 = 1024 or 1K, labeled 0 to 1023• memory content = 16-bit • so the memory has 1K words of 16-

bit data or 1K x 16-bit memory

Note :K (Kilo) = 210

M (Mega) = 220

G (Giga) = 230

Other Example : 64K = 216 = (26 * 210)2M = 221 = (21 * 220)4G = 232 = (22 * 230)What is the address bits (m)?

Memory OperationsMemory Operations Memory operations require the following:

Data Address An operation ─ Typical operations are READ and WRITE. (RAM)

Read Memory ─ an operation that reads a data value stored in memory: (takes from memory)

Place a valid address on the address lines Activate the Read input. Note : the content of the selected word are not changed by reading them

Write Memory ─ an operation that writes a data value to memory: Place a valid address on the address lines Apply data on the data lines Activate the Write input

Other than Read/Write (R/W) Chip Select is used to enable a particular Other than Read/Write (R/W) Chip Select is used to enable a particular RAM. It is sometimes called Memory Enable.RAM. It is sometimes called Memory Enable.

Memory EnableMemory Enable

RAM Integrated CircuitRAM Integrated Circuit Types of random access memory (RAM)

Static – information stored in latches Dynamic – information stored as electrical charges on

capacitors Charge “leaks” off Periodic refresh of charge required Dependence on Power Supply

Volatile – loses stored information when power turned off (example : FPGA – Flex10K)

Non-volatile – retains information when power turned off (example : CPLD – MAX)

RAM : Cell Arrays and RAM : Cell Arrays and Coincident SelectionCoincident Selection

Memory arrays can be very large =>Large decodersLarge fanouts for the bit linesHowever, the decoder size and fanouts can

be reduced by using a coincident selection in a 2-dimensional array:

Uses two decoders, one for words and one for bits Word select becomes Row select Bit select becomes Column select

A3 and A2 used for Row select

A1 and A0 for Column select

Figure : 9.7Morris Mano, pg 410

Example: Coincident Selection

• 16 X 1 RAM Chip• 16 = 24 = 4 bit add.[A3..A0]• The column decoder is enabled with the CS input

• When CS =0, column decoder is disabled and all o/p are 0 and NONE of the cells are selected

Example: Coincident Selection

If Address is 1001:• A3, A2 = 10, row decoder line 2 active

• Activating RAM 8,9,10 & 11

• A1, A0 = 01, column decoder line 1 active

• Activating RAM 1,5,9,13

• The intersect RAM is RAM 9 is activated. Other RAM cells not selected are disabled.

• Then it depends on the operation functions (Read or Write)

• Read : Data out thru OR gate and tri-state buffer

• Write : Data available on the Data input line is transferred into the selected RAM cell.

Figure : 9.7Morris Mano, pg 410

Constructing RAMConstructing RAM

Previously : Block Diagram of a 16 X 1 Previously : Block Diagram of a 16 X 1 RAM using 4 X 4 RAM Cell ArrayRAM using 4 X 4 RAM Cell Array

How to create 8 X 2 RAM using 4 X 4 How to create 8 X 2 RAM using 4 X 4 RAM Cell Array?RAM Cell Array?Number of Address bits = 8 = 2Number of Address bits = 8 = 233 = 3-bits = 3-bitsNumber of Data bits = 2-bitsNumber of Data bits = 2-bits

Figure 9.8 : Morris Mano, pg 411

3-bits addressing• 2-bits at Row Decoder• 1-bit at Column Decoder

Since 2 bits at a time are to be written or read:2 input lines• Data input 0• Data input 12 output lines• Data output 0• Data output 1

Example:If Address is = 011Row Decoder = line 1RAM = 4,5,6 & 7Column Decoder = line 1RAM = 2,6,10,14 and 3,7,11,15

Therefore : Cell 6 & 7 are activated

Constructing RAMConstructing RAM How about 32K X 8 bit?How about 32K X 8 bit? Address bit = 32 x 2Address bit = 32 x 21010

= 2= 255 x 2 x 21010= 15-bits= 15-bits Data bit = 8-bitData bit = 8-bit Without Coincident selection a single decoder would have 15 Without Coincident selection a single decoder would have 15

inputs and 32,768 outputs. (32 x 1K = 32 x 1024)inputs and 32,768 outputs. (32 x 1K = 32 x 1024) And 32,800 no of gates.And 32,800 no of gates.

With Coincident selection:With Coincident selection: Make row and column equalMake row and column equal Total RAM = 32K x 8 = 256K = 262144Total RAM = 32K x 8 = 256K = 262144 Take Sq Root of 262144 = 512Take Sq Root of 262144 = 512 512 = 2512 = 299 , meaning 9-bits is fed to the , meaning 9-bits is fed to the ROWROW Decoder. Decoder. Remaining 6-bits is fed to the Remaining 6-bits is fed to the COLUMNCOLUMN Decoder. Decoder. Row Decoder = 9 to 512 line decoderRow Decoder = 9 to 512 line decoder Column Decoder = 6 to 64 line decoderColumn Decoder = 6 to 64 line decoder No of gates = 608No of gates = 608

ARRAY of SRAM ICsARRAY of SRAM ICs

If an application is larger than the capacity of one chip, If an application is larger than the capacity of one chip, thenthen

There is a need to combine a number of chips in an There is a need to combine a number of chips in an array to form a required size of memory.array to form a required size of memory.

Depends on 2 parametersDepends on 2 parameters No of wordsNo of words No of bits per wordNo of bits per word

Number of words = address lineNumber of words = address line 1-bit added to address bit would double the no of words1-bit added to address bit would double the no of words

Number of bit = data input & outputNumber of bit = data input & output 1-bit added to the word size, 1 data input & output must be 1-bit added to the word size, 1 data input & output must be

addedadded

Let say u have this memory Let say u have this memory Chip.Chip.

• How to construct a 256K X 8 RAM using this 64K X 8 RAM Chip?• No of words is the same• No of address is not the same (64K 256K)

• 64K = 26 x 210 = 16-bit address bit• 256 = 28 x 210 = 18-bit address bit

• An additional 2 bit is needed for the address bit

Constructing 256K X 8 RAM using Constructing 256K X 8 RAM using four 64K x 8 RAM Chipfour 64K x 8 RAM Chip

2 additional address bit is applied to a 2 x 2 additional address bit is applied to a 2 x 4 decoder and represent the MSB of the 4 decoder and represent the MSB of the address bit.address bit.

How many 64K x 8 RAM chip to add?How many 64K x 8 RAM chip to add?Additional 2 bit = 2Additional 2 bit = 222 = = 44 of 64 x 8 RAM of 64 x 8 RAMUse Memory Enable to activate the Use Memory Enable to activate the

decoder.decoder.

Figure 9.10: Morris Mano, pg 413

When bit 17 and 16 = 00The first 64 x 8 RAM is activatedAddress : 0 – 65,535

Constructing 256K X Constructing 256K X 8 RAM using 64K x 8 8 RAM using 64K x 8 RAM ChipRAM Chip

When bit 17 and 16 = 01The 2nd 64 x 8 RAM is activatedAddress : 65,536 – 131,071

When bit 17 and 16 = 10The 3rd 64 x 8 RAM is activatedAddress : 131,071 – 196,607

When bit 17 and 16 = 11The 4th 64 x 8 RAM is activatedAddress : 196,608 – 262,143

What is we are to expand the What is we are to expand the word size?word size?

Example : 64K X 16 using 64K X 8 chipExample : 64K X 16 using 64K X 8 chip No of chip to be use refers to the word size.No of chip to be use refers to the word size. In this case, 16-bit is to be constructed from In this case, 16-bit is to be constructed from

8-bit words8-bit words Therefore Therefore 22 of 64K X 8 Chip is to be use of 64K X 8 Chip is to be use Connections:Connections:

Address line is input to both chipsAddress line is input to both chips CS is common to both chipsCS is common to both chips R/W control input is also common to both chipsR/W control input is also common to both chips INPUT & OUTPUT DATA LINE is SPLITINPUT & OUTPUT DATA LINE is SPLIT

Constructing a 64K X 16 using 64K Constructing a 64K X 16 using 64K X 8 chipX 8 chip

Din [7..0]Din [15..8]

Dout [15..8] Dout [7..0]

ExerciseExercise

How many 128K x 16 RAM chips are needed to How many 128K x 16 RAM chips are needed to provide a memory capacity of 1 M bytes?provide a memory capacity of 1 M bytes?

How many bits of address lines are required to How many bits of address lines are required to access 1M bytes? How many of these lines are access 1M bytes? How many of these lines are connected to the address inputs of all chips?connected to the address inputs of all chips?

How many lines must be decoded to produce How many lines must be decoded to produce the chip select inputs? Specify the size of the the chip select inputs? Specify the size of the decoder.decoder.

THANK YOUTHANK YOU