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ELE22MIC Lecture 17 • Microprocessor Storage Heirarchy – Speed – Volatility – Range: DRAM, SRAM, EPROM, FLASH, DISK • Protection and Privilege Levels • Memory Management Unit • 68HC11 Gray Code – Encoder Software Demonstration • Refer: http://thor.ee.latrobe.edu.au/~paulm

ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

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Page 1: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

ELE22MIC Lecture 17• Microprocessor Storage Heirarchy

– Speed– Volatility– Range: DRAM, SRAM, EPROM, FLASH, DISK

• Protection and Privilege Levels

• Memory Management Unit

• 68HC11 Gray Code – Encoder Software Demonstration

• Refer: http://thor.ee.latrobe.edu.au/~paulm

Page 2: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Storage HierarchyTypical Memory Heirarchy:

Speed, Capacity, Memory type

<1ns, <1KB, Register

2ns, 1MB, Cache

<10ns, 64M-1GB, Main memory

1s, <2MB Floppy Disk

10ms, 5-300GB, Hard/FLASH Disk

1s/10min, 650MB-4.7GB CDROM/RW/DVD

100s, 100MB-4TB Tape

Page 3: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Storage Hierarchy

• Consider the following issues– Speed – Cost– Volatility– Protection

Storage systems are organized in hierarchy as follows:

Register, Cache, Main memory, Disk, CDRW/Tape

Page 4: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Cache• Main Memory Caching

– copys data into faster storage systems to improving the system performance.

• Modern systems currently don’t use external cache memory as the overhead is greater than the benefit.

• Cache use in hardware - its use ebbs & flows with the technology capacity - it is used when performance improvement can be gained. Used in Intel 386 through Pentium.

Page 5: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Main Memory• Main Memory - Currently with PC333 and faster

memory systems - R/W access times are <3ns.• SDRAM - Synchronous Dynamic RAM• When using SDRAM, and later technology,

refresh is managed on the memory controller without system intervention.

• SRAM - Static Ram - as used in HCCOM – 85ns cycle time.

Page 6: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Dynamic RAM

• Modern IBM PCs use dynamic RAM• Popular since 1970• Always maintained a packing density edge over

other technologies. (simplicity of cell)• Early devices were 1k & 4k memories using 3-

transistors per memory cell (BIT)• The data is held on capacitance formed between

the gate and the source of each transistor.

Page 7: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Dynamic RAM

• Due to leakage the charge on the capacitor will leak away within a few milliseconds.

• The charge must be replenished at fixed intervals to maintain data integrity

• So memory is “Dynamic” in that it must be refreshed frequently to keep logic value.

• Low power– only need to overcome leakage current– charge state change from 1->0, 0->1

Page 8: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Dynamic RAM (1970-1980)

Page 9: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Dynamic RAM

• Refresh was initially performed under software control. Later versions used a dedicated channel in the DMA controller. Modern DRAM is refreshed by control logic on the memory stick.

• Memory is arranged in a matrix of Rows & Columns

• Density up to 1Gb (one Giga-Bit per chip)

Page 10: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Modern Dynamic RAM

Page 11: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Static RAM

• The data is held by on a pair of cross-coupled transistors.

• Only requires power to maintain data.

• To minimise Current flow, low power devices require large value poly-resistors (see diagram next page)

• No refresh time outage

• Add battery & logic to create non-volatile memory - no limit on number of writes

Page 12: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Static RAM

Page 13: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

EPROM MEMORY

• EPROM technology was once used to store the Basic Input Output System (BIOS) for each PC and any plug-in card - eg Video cards had their Video BIOS stored in the EPROM.

• This technology has access cycle times of 80-200ns per byte, and so the BIOSes were copied into faster RAM at boot time. This is known as Shadow RAM (Options in BIOS setup)

Page 14: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

EPROM USAGE• EPROMs are erased by placing them under strong Ultra

Violet light for around 5 minutes (see datasheets for exact specs) - i.e. Until every memory location responded with the value $FF. All charge was removed from the floating gate.

• So a typical program development cycle involved Program EPROM-> Install in device -> Test Code -> Locate a bug -> Erase Device in UV Eraser and do it all over again. Obviously better to have several EPROMS with some always being erased to avoid the erasure turnaround time of a few minutes

Page 15: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

EPROM USAGE

• Slow development cycles lead to the invention of EPROM Editors and EPROM Emulators. These were RAM based devices that could be loaded with data whilst the CPU was held in the reset state.

• Field Service:• Updating devices in the field required opening up the

BOX and replacing the EPROM, potentially exposing the device to damage from static discharge, bent component legs, and device failure/replacement.

Page 16: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage• It is necessary to be able to store large quantities of information

(programs and data) for long periods of time and during periods of no power.

• Old forms of storage:– paper tape, punched cards, magnetic tape - small capacity,

very slow, hard to use.• Modern forms of storage:

– hard disks/flash disks– floppy disks– optical disks– magnetic tape - huge capacities, very fast, very versatile,

easy to use.

Page 17: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

FLASH

• In an effort to improve responsiveness to program upgrades flash memory was invented

• Similar technology to EPROM, but erasure - removal of charge - performed by charge tunnelling through oxide insulator.

• Requires voltages > 5V. • Modern Flash has Internal Charge Pump to

generate the write voltages.

Page 18: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

FLASH

• So a typical program development cycle involves Erase & Program (few seconds) -> Install in device -> Test Code -> Locate a bug -> and do it all over again - faster than EPROM

• In-System Programmable (ISP) Flash – Some flash chips can be programmed in-circuit - Flash can be

permanently soldered onto the PCB - improves electrical & mechanical reliability.

• Development Cycle - ISP Flash: – Erase & Program -> Test Code -> Locate a bug– 10000 write cycle limit...

Page 19: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

FLASH DISKs

• Based on flash memory• Accessed as a disk -

– 512 byte / 1k block read write

• Formatted as a disk – mount / unmount / USB hot pluggable

• High packing density• Fast read cycle• Slow write cycle• Limited number of writes before cell value becomes less

reliable - 10 000 to 100 000 writes.

Page 20: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Secondary Storage- Floppy Disks • A floppy (flexible) disk is a flexible Mylar disk

which has been uniformly coated with a ferro-magnetic compound.

• Each side is organised in concentric circles called Tracks.

• Each track is organised in divided into segments called sectors.

• Historically Disks have been available in 8 inch, 5 1/4”, 3 1/2” dimensions.

Page 21: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Magnetic Surface Recording

Page 22: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Floppy Disks

Page 23: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Floppy Disks• A 5 1/4” floppy disk can contain:

– two sides,– 80 tracks,– 9 sectors per track,– 512 bytes per sector.

• The 5 1/4” floppy disk can contain:– 2 x 80 x 9 x 512 bytes = 720k bytes = 720 KB

Page 24: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Floppy Disks• Using similar formatting arrangements the 3

1/2” floppy disk can contain 2MB, but after formatting for IBM format only 1.44 MB. The File Allocation Table (FAT) occupies this space (560KB). – FAT points to start of each file, and links block to block

within a file.

• Using different formatting method can save a large amount of space lost in the FAT. – For example Linux’s 2nd Extended File System

(EXT2FS). Uses minimum number of I-Nodes to point to file blocks, and block size can be varied.

Page 25: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Hard Disks• Original hard disk interface ST506 was a very

popular standard between disk vendors.

• Originally developed by Seagate Technology

• Data is read & written serially onto the disk surface in a similar manner to floppy disks.

• 5mbit/sec data transfer rate

• Separate controller & disk.

Page 26: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Hard Disks• In 1983 ESDI was developed. 15mbit/sec.

• Higher density - 20 to 50 Sectors per track.

• The defect map is stored in the drive.

• The number of Cylinders, Heads & Sectors stored in ROM on the hard-disk.

Page 27: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Hard Disks

Page 28: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Mass Storage - Hard Disks• Circa 1985 IDE was developed. • Transfer rate of 16M byte/sec.• Integrated hard-disk controller.• Enhanced IDE (EIDE) transfer rates:

– UDMA - 33 MB/s; ATA 66, - 66MB/s– ATA 100 - 100MB/s

• SCSI-Ultra320 SCSI 320MB/s, 2-4ms seek time• Serial ATA - SATA 1.5Gbit/s, 250GB capacity

Page 29: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Format• Disks can have a logical structure imposed upon them

called a format.

• The format type is identified by numeric values in a special sector called the root super-block and the partition table.

• The format tells the operating system what to expect where – Where to find the root directory– Where is each file extent can be found– How to locate the operating system at boot time.

Page 30: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Format• There is a huge list of different format types

including:– FAT 12 - still used on IBM format floppy disks– FAT 16 - Used on hard disks < 2 GB– FAT 32 - Used on hard disks > 2GB– ISO9660 - Used on CDROMs (MS Jolliet)– NTFS - Newer NTFS allows for encrypted data. – Ext3fs - Used on newer unixes (allows journalling)– Minix, QNX, SCO,….etc– See fdisk under Linux for more info.

Page 31: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Root Directory• The root directory contains a list or table

describing file attributes such as: names, sizes, dates & times, and where each file commences on the physical disk.

• Where each file extent is found is specified using a File Allocation Table (in MSDOS) or an I-Node (under most Unixes).

Page 32: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

File Allocation Table• MSDOS File Allocation Table

– FAT 16 -> 2^16 table entries -> 65536 clusters

– FAT 32 -> 2^32 table entries -> 4177918 clusters

– A cluster is a group of sectors allocated by one FAT entry - determined at format time - vary from 1 sector (512 bytes) to 128 sectors (64k) per cluster

– Each FAT entry forms a link in a linked list pointing to the next cluster entry. A terminal value indicates end of cluster.

– The Directory Entry includes a pointer to the first cluster and the file size.

Page 33: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Files• Each file is an abstraction

– It is a block of bytes managed by the operating system.

– Identified by complete path-name or file-name• Path refers to [device:] [directory/folder..] filename . ext

– Operating systems services such as open, close, read, write and seek hide the underlying mechanisms and formats - Sectors, Tracks, controllers, CRCs / checksums, speed of rotation, head position, etc

Page 34: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Hardware Protection

To ensure proper system operation protection is required for any shared resource.

• Dual-Mode Privileged operation

• I/O protection

• Memory protection

• CPU protection

Page 35: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Management Unit

• The MMU hardware acts basically a sophisticated look-up table, configurable by the processor.

• The MMU provides the translation from logical to physical addresses.

• A word is defined as the basic addressable unit of a processor.

• In a 16 bit processor, a word is 16 bits, in a 32 bit processor a word is 32 bits.

Page 36: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Management Unit

LogicalAddressBus

Physical AddressBus

Page 37: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Management Unit

• In systems using memory management, words of memory are grouped together to form pages.

• An address can be considered to consist of a page number and a word number within that page.

• The MMU translates the page number to a new page number, but leaves the word number unmodified.

Page 38: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Management Unit

LogicalAddressBus

Physical AddressBus

Page 39: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Management UnitLogical Address :

Physical Page Number:Word -> Physical Address

Page 40: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Memory Protection

• Some registers within the MMU are used to distinguish the address of one program from another, e.g.

– Base register – holds the smallest legal physical memory address

– Limit register – contains the size of the range

• Memory outside the defined range is protected - Accessing memory outside the selected range causes a GP Fault.

Page 41: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

MMU : Logical Mem < Physical (1)

• The simplest form of memory management is when the logical space is smaller than the physical memory present.

Page 42: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Physical Page Number:Word Number -> Physical Address

MMU : Logical Mem < Physical (2)

Page 43: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

• In this instance, the processor's logical address becomes the word number within a page and the MMU supplies the page number. The processor selects which page in physical memory its logical address corresponds to.

• The physical page number and the word number together form the physical address for memory.

MMU - Logical < Physical (3)

Page 44: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

MMU - Logical < Physical (4)

Page 45: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

• For processor's with address spaces equal to or larger than the physical space, the memory management scheme becomes:

• The MMU contains a translation table.

• The translation table is accessible and configurable by the processor.

MMU - Logical >= Physical (1)

Page 46: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

• F

MMU - Logical >= Physical (2)

Page 47: ELE22MIC Lecture 17 Microprocessor Storage Heirarchy –Speed –Volatility –Range: DRAM, SRAM, EPROM, FLASH, DISK Protection and Privilege Levels Memory Management

Acknowledgments

• Motorola M68HC11 Reference Manual

• HC11 images derived from Motorola 11rm.pdf - HC11 Reference Manual

• DRAM images & Floppy Disk images from IEEE Electronics Engineers Handbook, 4th Edition, Donald Christiansen, ISBN 0-07-021862-5.

• Seng Goh’s original lecture notes on Memory Management