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This is information on a product in full production.
October 2016 DocID025248 Rev 4 1/10
10
EMIF06-HSD03F3
EMI filter with integrated ESD protection for micro-SD Card™
Datasheet production data
Figure 1. Pin configuration (bump side)
Figure 2. Functional schematic
Features
Very low line capacitance to compensate long PCB tracks (2.5 pF typ.)
High efficiency in ESD suppression up to 18 kV (IEC 61000-4-2)
Very low PCB space consumption:
– 1.1 x 2.4 mm
Ultralow leakage current: 20 nA max.
Very thin package: 0.605 mm
Smart pinout for easier PCB layout
High reduction of parasitic elements through integration and wafer level packaging
Lead-free package
Complies with the following standards:
– IEC 61000-4-2 level 4:±15 kV (air discharge), ±8 kV (contact discharge)
Application
SD3.0, UHS-1 SDR104 (208 MHz)
Description
The EMIF06-HSD03F3 chip is a highly integrated device designed to suppress EMI/RFI noise for interface line filtering.
The EMIF06-HSD03F3 Flip-Chip packaging means the package size is equal to the die size. That’s why EMIF06-HSD03F3 is a very small device. Additionally, this filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 18 kV.
Flip- hip packageC( bumps)17
Ix OxR = 1 ΩL 1 nH=
CLINE = 2.5 pF
DET VCC
www.st.com
Application diagram EMIF06-HSD03F3
2/10 DocID025248 Rev 4
1 Application diagram
Figure 3. Schema
Vcc
DET
CPUGND
µSD cardcontacts face down
DAT2
DAT3
CMD
VCC
CLK
DAT0
DAT1
µSD cardcontacts spring
Top layerSecond layer
I1 O1
Vcc
I3 O3
I5 O5
DET
I2 O2
GND
GND
GND
I4 O4
I6 O6
Maximum distance = 50 mm
DocID025248 Rev 4 3/10
EMIF06-HSD03F3 Characteristics
2 Characteristics
Figure 4. Electrical characteristics (definitions)
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Symbol Parameter Value Unit
VPP
ESD discharge IEC 61000-4-2, level 4 for Ix pins:
Air dischargeContact discharge
ESD discharge IEC 61000-4-2, level 1 for Ox pins:
Air dischargeContact discharge
18
18
10
10
kV
Tj Maximum junction temperature 125 °C
TOP Operating temperature range - 30 to + 85 °C
Tstg Storage temperature range - 55 to +150 °C
Symbol ParameterV = Breakdown voltageI = Leakage current at V
V = Stand-off voltage
V = Clamping voltageI = Peak pulse current
BR
RM RM
RM
CL
PP
V
I
VCLVBR VRM
IF
VF
IRM
IPP
Slope: 1/Rd
R = Dynamic resistanced
Cline
R =I/O
= Line capacitance
Series resistance betweeninput and ouptput
Characteristics EMIF06-HSD03F3
4/10 DocID025248 Rev 4
Table 2. Electrical characteristics (Tamb = 25 °C)
Symbol Test conditions Min. Typ. Max. Unit
VBR Data lines, IR = 1 mA 5 9 V
IRM VRM = 3 V per line 20 nA
RI/O 1 Ω
Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz 2.5 3 pF
L 1 nH
Rd Dynamics resistance, tP = 100 nsIO-GND (positive polarity) 650
m ΩGND-IO (negative polarity) 320
VCC
VBR IR = 1 mA 5 9 V
IRM VRM = 3 V 20 nA
Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz 40 pF
DET
VBR IR = 1 mA 5 9 V
IRM VRM = 3 V 20 nA
Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz 40 pF
DocID025248 Rev 4 5/10
EMIF06-HSD03F3 Characteristics
Figure 5. Attenuation versus frequencyIX, OX
Figure 6. Attenuation versus frequencyVCC, DET
S21(dB)
100.0 k 1.0 M 10.0 M 100.0 M 1.0 G-10.00
- 9.00
- 8.00
- 7.00
- 6.00
- 5.00
- 4.00
- 3.00
- 2.00
- 1.00
0.00
I6 I2I3
I4I5I1
F(Hz)
S21(dB)
100.0k 1.0M 10.0M 100.0M 1.0G
-30.00
-22.50
-15.00
-7.50
0.00
VCC DET
F(Hz)
Figure 7. ESD response to IEC 61000-4-2(+8 kV contact discharge)
Figure 8. ESD response to IEC 61000-4-2(-8 kV contact discharge)
20.0 V / Div
20 ns / Div
V : Peak clamping voltageCL
V :clamping voltage @ 30 nsCL
V :clamping voltage @ 60 nsCL
V :clamping voltage @ 100 nsCL
12
34
19.2 V
109.6 V
13.9 V6.6 V2
1
34
10.0 V / Div
20 ns / Div
V : Peak clamping voltageCL
V :clamping voltage @ 30 nsCL
V :clamping voltage @ 60 nsCL
V :clamping voltage @ 100 nsCL
12
34
-5.1 V
-61.1 V
-4.1 V-2.4 V
2
1
34
Figure 9. Digital crosstalk I1-O2 Figure 10. Analog crosstalk versus frequency
10 ns / Div
1.0 V / Div
P2:rise(C1)1.99 ns P3: fall(C1)
1.93 ns
P1: top(C1)3.01 ns
P4: pkpk(C2)1.28 ns
XTalk(dB)
100.0 k 1.0 M 10.0 M 100.0 M 1.0 G-110.00
-100.00
-90.00
-80.00
-70.00
-60.00
-50.00
-40.00
-30.00
-20.00
-10.00
0.00
VCC- ClkI1-O2 I2-O3
F(Hz)
Characteristics EMIF06-HSD03F3
6/10 DocID025248 Rev 4
Figure 11. TLP measurement
y = -0.0078x 2 + 2.1203x - 13.887R2 = 0.9956
y = 0.0961x 2 + 2.1437x - 4.7641R2 = 0.9935
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20 25 30 35 40
tP=100ns
TJ initial=25°C
Positive polarity
Negative polarity
Poly. (Positive polarity)
Poly. (Negative polarity)
VCL(V)
IPP(A)
DocID025248 Rev 4 7/10
EMIF06-HSD03F3 Package information
3 Package information
Epoxy meets UL94, V0
Lead-free package
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
3.1 Flip-Chip package information
Figure 12. Flip-Chip package dimensions
40
0 ±
40
µm
400 ± 40 µm
1.10 mm ± 40 µm60 ± 60 µm5
2.4
0 m
m± 4
0 µ
m
Package information EMIF06-HSD03F3
8/10 DocID025248 Rev 4
Figure 15. Tape and reel specification
Note: More information is available in the application notes:
AN2348, “IPAD™ 400 µm Flip Chip: package description and recommendations for use”
AN1751, “EMI filters: recommendations and measurements”
AN4541: “EMI Filters for SD3.0 card: High speed SD card protection and filtering devices”
Figure 13. Footprint recommendations Figure 14. Marking
220 µm recommended
220 µm recommended260 µm maximum
Solder stencil opening:
Copper pad Diameter:
Solder mask opening:300 µm minimum x
y
x
w
z
w
Dot, ST logo
xx = markingz = manufacturing locationyww = datecode
(y = yearww = week)
ECOPACK® grade
DocID025248 Rev 4 9/10
EMIF06-HSD03F3 Ordering information
4 Ordering information
Figure 16. Ordering information scheme
5 Revision history
Table 3. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF06-HSD03F3 KK Flip Chip 3.4 mg 5000 Tape and reel (7”)
EMIF 06 - HSD 03 F3
EMI Filter
Number of lines
Application
HSD = High speed SD card
Version
Version = 3
Package
F = Flip Chipx = 3: Lead-free, pitch = 400 µm, bump = 255 µm
Table 4. Document revision history
Date Revision Changes
19-Nov-2013 1 Initial release
09-Jan-2014 2 Corrected typographical error.
06-Jan-2015 3 Added mention for new AN4541.
06-Oct-2016 Updated Figure 1.
EMIF06-HSD03F3
10/10 DocID025248 Rev 4
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