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ISSN 01464116, Automatic Control and Computer Sciences, 2010, Vol. 44, No. 5, pp. 302–307. © Allerton Press, Inc., 2010. Original Russian Text © P.N. Bibilo, P.V. Leonchik, 2010, published in Avtomatika i Vychislitel’naya Tekhnika, 2010, No. 5, pp. 72–75. 302 1. INTRODUCTION Along with complexity, speed, and testability, energy consumption has become one of the most impor tant digital device parameters today. The problem of reducing energy consumption of integral CMOS microcircuits, based on which digital devices are implemented, is solved practically at all design stages, from algorithmic to topological ones. To reduce the consumed power, the corresponding synchronization is selected, asynchronous circuits applied, specific logical gate libraries are developed, new constructive and circuit engineering solutions applied, etc. [1]. The problem of reducing energy consumption at the logical synthesis stage of combinational circuits, which are functional units of a VLSIC (very large scale integrated circuit), is considered in the present paper. Synthesis of combinational logical circuits in industrial logical circuit synthesizers is traditionally divided into two large stages: global, technologically independent optimization and technology mapping [2]. Mutual or individual minimization of Boolean functions system in the category of disjunctive normal forms (DNFs), which makes it possible to obtain optimized twolayered (AND–OR) function represen tations, is most often used as technologically independent optimization. Optimized multilayered repre sentations as parenthesis algebraic forms of functions are obtained on the basis of multiple application of Shannon’s decomposition. These representations were called binary decision diagrams or BDD represen tations [3–5]. The corresponding heuristic evaluations of the energetic quality of these representations are suggested in the present paper for selection of preferable optimized (with respect to energy consumption criterion) multilayered representations of systems of completely defined Boolean functions. The probabilities of unit signal value appearance at logical circuit inputs, obtained as a result of synthesis based on optimized rep resentations, are used in evaluations. The effect of the energetic BDD optimization procedure on energy consumption of combinational logical circuits, synthesized using the design library for custom digital CMOS VLSIC by the wellknown industrial synthesizer LeonardoSpectrum [2], is investigated experi mentally. The modified optimization program for BDD representations of Boolean functions systems acts as such a procedure. 2. CONSIDERATION OF ENERGY CONSUMPTION DURING OPTIMIZATION OF BDD REPRESENTATIONS OF BOOLEAN FUNCTIONS SYSTEMS A binary decision diagram (BDD) turned out to be an efficient function representation form and obtained wide circulation [5]. Selection of the variable sequence, according to which Shannon’s decom position is carried out, is the main BDD construction problem. The minimum BDD complexity (quantity of nodes) criterion was accepted as the main optimization criterion for BDD optimization, and the crite Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption P. N. Bibilo and P. V. Leonchik United Institute of Informatics Problems, National Academy of Sciences of Belarus, ul. Surganova 6, Minsk, 220012 Belarus email: [email protected] Received May 26, 2010 Abstract—The effect of a minimization procedure of multilayered BDD representations of systems of completely defined Boolean functions on combinational CMOS circuit energy consumption is inves tigated. The corresponding experiment is described, and the obtained results are analyzed. Keywords: energy consumption, combinational CMOS circuits, Boolean functions, binary decision diagrams DOI: 10.3103/S0146411610050081

Experimental investigation of the BDD optimization procedure effect on combinational CMOS circuit energy consumption

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ISSN 0146�4116, Automatic Control and Computer Sciences, 2010, Vol. 44, No. 5, pp. 302–307. © Allerton Press, Inc., 2010.Original Russian Text © P.N. Bibilo, P.V. Leonchik, 2010, published in Avtomatika i Vychislitel’naya Tekhnika, 2010, No. 5, pp. 72–75.

302

1. INTRODUCTION

Along with complexity, speed, and testability, energy consumption has become one of the most impor�tant digital device parameters today. The problem of reducing energy consumption of integral CMOSmicrocircuits, based on which digital devices are implemented, is solved practically at all design stages,from algorithmic to topological ones. To reduce the consumed power, the corresponding synchronizationis selected, asynchronous circuits applied, specific logical gate libraries are developed, new constructiveand circuit engineering solutions applied, etc. [1]. The problem of reducing energy consumption at thelogical synthesis stage of combinational circuits, which are functional units of a VLSIC (very large scaleintegrated circuit), is considered in the present paper.

Synthesis of combinational logical circuits in industrial logical circuit synthesizers is traditionallydivided into two large stages: global, technologically independent optimization and technology mapping[2]. Mutual or individual minimization of Boolean functions system in the category of disjunctive normalforms (DNFs), which makes it possible to obtain optimized two�layered (AND–OR) function represen�tations, is most often used as technologically independent optimization. Optimized multilayered repre�sentations as parenthesis algebraic forms of functions are obtained on the basis of multiple application ofShannon’s decomposition. These representations were called binary decision diagrams or BDD represen�tations [3–5].

The corresponding heuristic evaluations of the energetic quality of these representations are suggestedin the present paper for selection of preferable optimized (with respect to energy consumption criterion)multilayered representations of systems of completely defined Boolean functions. The probabilities of unitsignal value appearance at logical circuit inputs, obtained as a result of synthesis based on optimized rep�resentations, are used in evaluations. The effect of the energetic BDD optimization procedure on energyconsumption of combinational logical circuits, synthesized using the design library for custom digitalCMOS VLSIC by the well�known industrial synthesizer LeonardoSpectrum [2], is investigated experi�mentally. The modified optimization program for BDD representations of Boolean functions systems actsas such a procedure.

2. CONSIDERATION OF ENERGY CONSUMPTION DURING OPTIMIZATION OF BDD REPRESENTATIONS OF BOOLEAN FUNCTIONS SYSTEMS

A binary decision diagram (BDD) turned out to be an efficient function representation form andobtained wide circulation [5]. Selection of the variable sequence, according to which Shannon’s decom�position is carried out, is the main BDD construction problem. The minimum BDD complexity (quantityof nodes) criterion was accepted as the main optimization criterion for BDD optimization, and the crite�

Experimental Investigation of the BDD Optimization Procedure Effect on Combinational CMOS Circuit Energy Consumption

P. N. Bibilo and P. V. LeonchikUnited Institute of Informatics Problems, National Academy of Sciences of Belarus,

ul. Surganova 6, Minsk, 220012 Belaruse�mail: [email protected]�net.by

Received May 26, 2010

Abstract—The effect of a minimization procedure of multilayered BDD representations of systems ofcompletely defined Boolean functions on combinational CMOS circuit energy consumption is inves�tigated. The corresponding experiment is described, and the obtained results are analyzed.

Keywords: energy consumption, combinational CMOS circuits, Boolean functions, binary decisiondiagrams

DOI: 10.3103/S0146411610050081

AUTOMATIC CONTROL AND COMPUTER SCIENCES Vol. 44 No. 5 2010

EXPERIMENTAL INVESTIGATION 303

rion associated with probabilities of signal varia�tions at the systems inputs was a subordinate crite�rion. The first criterion is oriented at minimizationof complexity (quantity of transistors) of the logicalcircuit, which is composed at the technology map�ping stage, because reduction in the quantity oftransistors makes it possible to decrease energy con�sumption. The second criterion makes it possible toselect BDDs among equally complex ones, basedon which the combinational logical circuits charac�terized by low energy consumption may be con�structed.

The suggested energetic approach to BDD opti�mization is illustrated by the example of system Fincluding three functions f 1, f 2, and f 3 (Table 1).Assume the variable sequence, based on whichShannon’s decomposition is constructed, is as fol�lows: ⟨x1,x2,x3,x4,x5,x6⟩. Shannon’s decomposition ofcompletely defined Boolean function f(x1, …, xn)with respect to variable (argument) xi is the repre�sentation of f(x1, …, xn) as follows:

(1)

Functions f(x1, …, xi – 1, 1, xi + 1, …, xn) and f(x1, …, xi – 1, 0, xi + 1, …, xn) in (1) are called decompositioncoefficients. They are obtained from function f(x1, …, xn) by substitution of constants 1 and 0, respectively,instead of variable x1. It can be seen that if coefficients are equal, then f(x1, …, xn) = f(x1, …, xi – 1, xi + 1, …,xn). The variable xi is called a nonexisting or slack variable of the completely defined function f(x1, …, xn)in this case. Each of coefficients f(x1, …, xi – 1, 1, xi + 1, …, xn) and f(x1, …, xi – 1, 0, xi + 1, …, xn) may bedecomposed with respect to one of the variables from the set {x1, …, xi – 1, xi + 1, …, xn}. The coefficientdecomposition process is finished when all n variables will be used for decomposition. At the final decom�position stage, coefficients degenerate into constants 0 and 1. The binary decision diagram or BDD impliesan oriented graph determining all different Shannon’s decompositions coefficients for Boolean functionf(x1, …, xn) with respect to all of its variables x1, …, xn for the assigned order (rearrangement) of variables,based on which decompositions are carried out.

We assume that the dashed edge will lead to the coefficient f(x1, …, xi – 1, 0, xi + 1, …, xn) on the BDD,and the solid edge, to the coefficient f(x1, …, xi – 1, 1, xi + 1, …, xn). To reduce the BDD graph, constantnodes 0 and 1 are usually duplicated, and directed edges are substituted by undirected edges. Note that theBDD graph in the literature is usually presented in reduced form, the obtained decomposition coefficientsare not marked, and it is only assumed that all edges entering the same edge�variable correspond to onedecomposition coefficient.

We construct the BDD (figure) according to matrix representation of the function system (Table 1)using the algorithm presented in [6]. The following multilayered function system representation corre�sponds to the current BDD:

(2)

We indicate the probability of unit signal value appearance in xi at the input of the logical circuit imple�menting the BDD as αi, the quantity of literals of the variable xi in multilayered functions system repre�sentation corresponding to BDD is represented as Si. We consider the functional

Ki = αi × Si, if αi < 0.5;

Ki = (1 – αi) × Si, if αi ≥ 0.5.

f x1 … xn, ,( ) xi f x1 … xi 1– 1 xi 1+ … xn, , , , , ,( ) xi f x1 … xi 1– 0 xi 1+ … xn, , , , , ,( ).∨=

f 1 x1ψ1 x1ψ

2; f 2

∨ x1ϕ3 x1ψ

4; f 3

∨ x1ψ5 x1ψ

6; ψ

1∨ x2ϕ

1 x2ϕ2; ψ

2∨ x2ϕ

3;= = = = =

ψ4 x2s1 x2ϕ

4; ψ

5∨ x2ϕ

3; ψ

6 x2ϕ5 x2ϕ

6; ϕ

2∨ x3s2 x3s1

; ϕ3

∨ x3s3 x3s4;∨= = = = =

ϕ4 x3s5

; ϕ5 x3s6 x3s2

; ϕ6

∨ x3s2; s1 x4λ

1; s2 x4λ

3 x4λ2; s4

∨ x4λ4;= = = = = =

λ1 x5ω

1; λ

2 x5ω1 x5; λ

3∨ x5; λ

4 x5ω2; ω

1 x6; ω2 x6.= = = = = =

Table 1. DNF system of Boolean functions

Tx B f

x1 x2 x3 x4 x5 x6 f 1 f 2 f 3

1 1 – 0 1 0 1 0 0

0 – – 1 0 1 1 0 0

0 – – 0 1 0 0 1 0

0 – 0 – 1 – 0 1 0

1 1 1 – 1 0 0 1 0

1 0 – 1 0 1 0 1 0

1 0 0 – – 1 0 0 1

1 0 ⎯ 1 – 1 0 0 1

1 – 0 1 – 1 0 0 1

0 1 – 0 1 0 0 0 1

1 0 – – 1 – 0 0 1

– 1 0 – 1 – 1 0 1

304

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BIBILO, LEONCHIK

We call Ki the evaluated energetic quality of the variable xi in BDD representation. If the probability αi

is close to 0.5, then such variables will cause more switching at the circuit element inputs, and, therefore,it is desired to minimize the quantity of appearances of such variables literals in the functional BDD rep�resentation. If the probability αi is close to 0 or 1, then such variables will cause less signal switching in thecircuit. The experiments on validation of the energetic quality concept of the variable x1 in the BDD rep�resentation were carried out. The idea of experiments will be clarified by the example. Assume there aretwo variants (Table 2) of probabilities of unit input signal values that appear at inputs of the logical circuit,which implements the functional BDD description represented by (1). Having synthesized the corre�sponding logical circuit and carried out circuit engineering simulation for two testing sample flows char�acterized by signal probabilities presented in Table 3, it was proven by circuit engineering simulation thatthe circuit’s energy consumption for testing samples of variant 2 was more than the one for testing samplesof the variant 1, by 45%.

f 1 f 2 f 3

x1

x2

x3

ψ1 ψ2 ψ4 ψ5 ψ6

ϕ2 ϕ3 ϕ4 ϕ5 ϕ6

x1 x1

x3 x3 x3 x3

x2 x2 x2 x2

0

s1 s4 s2

x4

x5

0

0 0

0 0

x6

λ1 λ2 λ3 λ4

ω1 ω2

x4 x4

x6

x5 x5 x5

0 1

System representation of Boolean functions in the form of a binary decision diagram (BDD).

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EXPERIMENTAL INVESTIGATION 305

The BDD energetic quality will be consid�ered the best, if the sum of the estimated ener�getic qualities Ki with respect to all input vari�ables will be less. Variant 1 is preferable in theconsidered example, because it is characterizedby the smaller sum of the estimated Ki—7.5.

BDD optimization algorithm presented in[6] was modified in the aspect of evaluation ofBDD representations, obtained during thesearch of the best variables rearrangement, basedon which BDD construction is carried out. Thecomplexity of BDD representation was evalu�ated in the suggested algorithm’s modification asthe sum of Ki evaluated with respect to all vari�ables xi, but not as the quantity of BDD nodes aswas done in [6].

3. ORGANIZATION OF EXPERIMENTS

The investigations were carried out for flows of sample DNF systems (programmable logic array (PLA)circuits) from the library Berkeley PLA Test [7], the design library of custom digital integrated CMOS cir�cuits acting as a synthesis library. Two BDD optimization programs were taken as programs under study:the program OPT_BDD [6] implementing the BDD optimization algorithm without considering energyconsumption and oriented only at BDD complexity minimization, and the program Bdd_Energy imple�menting the selection of decomposition variables sequence considering the variables’ energetic quality.

Experimental stages:(1) The results of operation of the optimization programs obtained using OPT_BDD and Bdd_Energy

were represented using VHDL language [2].(2) Logical circuits were synthesized according to VHDL descriptions of the representations of the

optimized function system using the synthesizer LeonardoSpectrum [2]. The circuits' complexities (quan�tities of logical gates) were recorded.

(3) VHDL descriptions of logical circuits were transformed into circuit engineering Spice descrip�tions [8].

(4) The sequence of N = 512 input testing vectors with nonuniform probabilities of the appearance ofthe unit signal value in xi according to Table 3 was generated.

(5) Circuit engineering simulation was carried out using the method [8] in the system AccuSim(designed by the company Mentor Graphics) for the indicated testing sample sequence, and the circuit’saverage current consumption was calculated (parameter Average provided by the system AccuSim as aresult of analog simulation).

4. EXPERIMENTAL RESULTS

The experimental results for the BDD optimization programs are presented in Table 4, the minimumconsumed current values and the minimum values of the circuit element quantities are typed in bold. Notethat analog (circuit engineering) simulation is labor�intensive, for example, the simulation for 128 inputsamples in the case of the circuit tial (Table 4) including 816 logical gates using the system AccuSim took

Table 2. Evaluated BDD energetic quality (figure)

xi Si

Variant 1 Variant 2

αi Ki αi Ki

x1 6 0.3 1.8 0.3 1.8

x2 8 0.1 0.8 0.5 4.0

x3 8 0.1 0.8 0.5 4.0

x4 4 0.4 1.6 0.4 1.6

x5 5 0.3 1.5 0.3 1.5

x6 2 0.5 1.0 0.5 1.0

7.5 13.9Ki

i 1=

6

Table 3. Probabilities of unit values of input variables

xi x1 x2 x3 x4 x5 x6 x7 x8

αi 0.10 0.13 0.16 0.19 0.22 0.25 0.28 0.31

xi x9 x10 x11 x12 x13 x14 x15 x16

αi 0.34 0.37 0.40 0.43 0.46 0.49 0.52 0.55

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11 minutes of personal computer operation with the CPU Intel E6750 functioning at a clock frequency of2.66 GHz.

If we analyze the obtained experimental results, the following conclusions may be made. Circuits char�acterized by lower energy consumption are obtained based on the multilayered BDD representations,obtained using the program of BDD energetic optimization of the function system. However, if the circuitis more complex, i.e., includes many more logical gates (nearly by 10%) compared to the circuit obtainedafter traditional BDD optimization, then this circuit’s energy consumption will generally be higher. Theexamples of such circuits are in0, root, add6, br1, gary, and tial (Table 4). The percent reduction (if theminus sign is present) of the A2 consumed current value against the value A1, taken as 100%, is shown inthe column ρBDD (Table 4). However, if the complexity of the circuit obtained using the energetic BDDoptimization exceeds the complexity of the circuit after traditional BDD optimization insignificantly,then its energy consumption will generally be less.

5. CONCLUSIONS

The technologically independent BDD optimization considering the possibilities of appearance of unitsignal values at the circuit’s inputs makes it possible to reduce the synthesized logical circuit’s energy con�sumption to some extent; however, the circuits’ complexity (area) is the main factor affecting the energyconsumption of irregular combinational CMOS circuits. Therefore, the development of efficient areaminimization methods for irregular logical circuits synthesized within the library basis of custom digitalCMOS VLSIC design remains a topical scientific problem.

REFERENCES

1. Rabaey, J.M., Chandrakasan, A., and Nikolic, B., Digital Integrated Circuits, Prentice–Hall, 2nd ed.

Table 4. The experimental investigation results of BDD optimization programs

Circuit name

Traditional BDD optimization (OPT_BDD program)

Energetic BDD optimization (Bdd_Energy program)

ρBDD, %

Average (current), A1Quantity of circuit’s

elements Average (current), A2Quantity of circuit’s

elements

z9sym 0.308 55 0.267 55 –15.4%

mlp4 0.693 200 0.638 216 –8.6%

in0 1.111 272 1.244 310 10.7%

life 0.313 46 0.294 46 –6.5%

b12 0.251 51* 0.251 51* 0.0%

tms 0.667 137 0.665 132 –0.3%

root 0.355 75 0.393 85 9.7%

add6 0.329 50 0.469 62 29.9%

br1 0.077 85 0.115 91 33.0%

br2 0.065 66 0.052 68 –25.0%

gary 1.111 272 1.648 402 32.6%

m3 0.952 174 0.967 181 1.6%

max1024 1.323 404 1.326 393 0.2%

tial 3.257 673 3.440 816 5.3%

* The same logical circuit.

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EXPERIMENTAL INVESTIGATION 307

2. Bibilo, P.N., Integrated Circuit Design Systems Based on VHDL Language. StateCAD, ModelSim, LeonardoSpec�trum, Moscow: SOLON, 2005.

3. Akers, S.B., Binary Decision Diagrams, IEEE Trans. on Computers, 1978, vol. C�27, no. 6, pp. 509–516.4. Bryant, R.E., Graph�Based Algorithms for Boolean Functions Manipulation, IEEE Trans. on Computers, 1986,

vol. C�35, no. 8, pp. 677–691.5. Bryant, R.E. and Meinel, C., Ordered Binary Decision Diagrams, in Logic Synthesis and Verification, Hassoun, S.,

Sasao, T., and Brayton, R.K., Eds., Kluwer Academic, 2002, pp. 285–307.6. Bibilo, P.N. and Leonchik, P.V., Binary Decision Diagram Construction Algorithm for the Completely Defined

Boolean Functions System, Upr. Sist. Mash., 2009, no. 5, pp. 42–49.7. http://www1.cs.columbia.edu/~cs4861/sis/espresso�examples/ex/.8. Avdeev, N.A. and Bibilo, P.N., Energy Consumption Evaluation of the Digital VLSIC Unit, Sovr. Elektronika,

2009, no. 9, pp. 46–49.