FAMILY PROGRAMMING MANUALa 4-bit word GPR address relative to the base address (CP), while ’Rb’ specifies a 4 bit byte GPR address relative to the base address (CP). reg Specifies

This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Ref: ST10FPM

ST10FAMILY PROGRAMMING MANUAL

Release 1

ST10 FAMILY PROGRAMMING MANUAL

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1 INTRODUCTION ......................................................................................................... 3

2 STANDARD INSTRUCTION SET............................................................................... 4

2.1 ADDRESSING MODES............................................................................................... 4

2.1.1 Short adressing modes................................................................................................ 42.1.2 Long addressing mode ................................................................................................ 52.1.3 DPP override mechanism............................................................................................ 62.1.4 Indirect addressing modes .......................................................................................... 62.1.5 Constants .................................................................................................................... 72.1.6 Branch target addressing modes................................................................................. 7

2.2 INSTRUCTION EXECUTION TIMES .......................................................................... 8

2.2.1 Definition of measurement units .................................................................................. 92.2.2 Minimum state times.................................................................................................... 102.2.3 Additional state times .................................................................................................. 10

2.3 INSTRUCTION SET SUMMARY................................................................................. 13

2.4 INSTRUCTION SET ORDERED BY FUNCTIONAL GROUP ..................................... 15

2.5 INSTRUCTION SET ORDERED BY OPCODES ........................................................ 26

2.6 INSTRUCTION CONVENTIONS................................................................................. 34

2.6.1 Instruction name .......................................................................................................... 342.6.2 Syntax.......................................................................................................................... 342.6.3 Operation..................................................................................................................... 342.6.4 Data types ................................................................................................................... 352.6.5 Description................................................................................................................... 352.6.6 Condition code............................................................................................................. 352.6.7 Flags............................................................................................................................ 362.6.8 Addressing modes....................................................................................................... 37

2.7 ATOMIC AND EXTENDED INSTRUCTIONS ............................................................. 38

2.8 INSTRUCTION DESCRIPTIONS ................................................................................ 39

3 MAC INSTRUCTION SET........................................................................................... 123

3.1 ADDRESSING MODES............................................................................................... 123

3.2 MAC INSTRUCTION EXECUTION TIME ................................................................... 124

3.3 MAC INSTRUCTION SET SUMMARY........................................................................ 124

3.4 MAC INSTRUCTION CONVENTIONS........................................................................ 126

3.4.1 Operands..................................................................................................................... 1263.4.2 Operations ................................................................................................................... 1263.4.3 Abbreviations............................................................................................................... 1263.4.4 Data addressing Modes............................................................................................... 1263.4.5 Instruction format......................................................................................................... 1273.4.6 Flag states ................................................................................................................... 1273.4.7 Repeated instruction syntax ........................................................................................ 1273.4.8 Shift value.................................................................................................................... 127

3.5 MAC INSTRUCTION DESCRIPTIONS ....................................................................... 127

4 REVISION HISTORY .................................................................................................. 170

TABLE OF CONTENTS Page


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3/172January 2000

1 - INTRODUCTION

This programming manual details the instructionset for the ST10 family of products. The manual isarranged in two sections. Section 1 details thestandard instruction set and includes all of thebasic instructions. Section 2 details the extension to the instructionset provided by the MAC. The MAC instructionsare only available to devices containing the MAC,refer to the datasheet for device-specificinformation.In the standard instruction set, addressing modes,instruction execution times, minimum state timesand the causes of additional state times aredefined. Cross reference tables of instructionmnemonics, hexadecimal opcode, addressmodes and number of bytes, are provided for theoptimization of instruction sequences. Instruction set tables ordered by functional group,can be used to identify the best instruction for agiven application. Instruction set tables orderedby hexadecimal opcode can be used to identify

specific instructions when reading executablecode i.e. during the de-bugging phase. Finally,each instruction is described individually on apage of standard format, using the conventionsdefined in this manual. For ease of use, theinstructions are listed alphabetically. The MAC instruction set is divided into its 5functional groups: Multiply and Multiply-Accumulate, 32-Bit Arithmetic, Shift, Compareand Transfer Instructions. Two new addressingmodes supply the MAC with up to 2 new operandsper instruction. Cross reference tables of MAC instructionmnemonics by address mode, and MACinstruction mnemonic by functional code can beused for quick reference. As for the standard instruction set, eachinstruction has been described individually in astandard format according to defined conventions.For convenience, the instructions are described inalphabetical order.

ST10


This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.


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2 - STANDARD INSTRUCTION SET

2.1 - Addressing Modes

2.1.1 - Short adressing modes

The ST10 family of devices use several powerfuladdressing modes for access to word, byte and bitdata. This section describes short, long and indi-rect address modes, constants and branch targetaddressing modes. Short addressing modes usean implicit base offset address to specify the24-bit physical address. Short addressing modesgive access to the GPR, SFR or bit-addressablememory spacePhysicalAddress = BaseAddress +∆ x ShortAddress.Note: ∆ = 1 for byte GPRs, ∆ = 2 for word GPRs

(see Table 1).

Rw, Rb

Specifies direct access to any GPR in the cur-rently active context (register bank). Both ’Rw’ and’Rb’ require four bits in the instruction format. Thebase address of the current register bank is deter-mined by the content of register CP. ’Rw’ specifiesa 4-bit word GPR address relative to the baseaddress (CP), while ’Rb’ specifies a 4 bit byteGPR address relative to the base address (CP).

reg

Specifies direct access to any (E)SFR or GPR inthe currently active context (register bank). ’reg’requires eight bits in the instruction format. Short’reg’ addresses from 00h to EFh always specify(E)SFRs. In this case, the factor ’∆’ equals 2 andthe base address is 00’F000h for the standardSFR area, or 00’FE00h for the extended ESFRarea. ‘reg’ accesses to the ESFR area require apreceding EXT*R instruction to switch the baseaddress. Depending on the opcode of an instruc-tion, either the total word (for word operations), or

the low byte (for byte operations) of an SFR canbe addressed via 'reg'. Note that the high byte ofan SFR cannot be accessed by the 'reg' address-ing mode. Short 'reg' addresses from F0h to FFhalways specify GPRs. In this case, only the lowerfour bits of 'reg' are significant for physicaladdress generation, therefore it can be regardedas identical to the address generation describedfor the 'Rb' and 'Rw' addressing modes.

bitoff

Specifies direct access to any word in thebit-addressable memory space. 'bitoff' requireseight bits in the instruction format. Depending onthe specified 'bitoff' range, different baseaddresses are used to generate physicaladdresses: Short 'bitoff' addresses from 00h to7Fh use 00’FD00h as a base address, thereforethey specify the 128 highest internal RAM wordlocations (00’FD00h to 00’FDFEh).Short 'bitoff'addresses from 80h to EFh use 00’FF00h as abase address to specify the highest internal SFRword locations (00’FF00h to 00’FFDEh) or use00’F100h as a base address to specify the highestinternal ESFR word locations (00’F100h to00’F1DEh). ‘bitoff’ accesses to the ESFR arearequire a preceding EXT*R instruction to switchthe base address. For short 'bitoff' addresses fromF0h to FFh, only the lowest four bits and thecontents of the CP register are used to generatethe physical address of the selected word GPR.

bitaddr

Any bit address is specified by a word addresswithin the bit-addressable memory space (see'bitoff'), and by a bit position ('bitpos') within thatword. Thus, 'bitaddr' requires twelve bits in theinstruction format.

Table 1 : Short addressing mode summary

Mnemo Physical Address Short Address Range Scope of Access

Rw (CP) + 2*Rw Rw = 0...15 GPRs (Word) 16 values

Rb (CP) + 1*Rb Rb = 0...15 GPRs (Byte) 16 values

reg 00’FE00h00’F000h(CP)(CP)

+ 2*reg+ 2*reg+ 2*(reg^0Fh)+ 1*(reg^0Fh)

regregregreg

= 00h...EFh= 00h...EFh= F0h...FFh= F0h...FFh

SFRsESFRsGPRsGPRs

(Word, Low byte)(Word, Low byte)(Word) 16 values(Bytes) 16 values

bitoff 00’FD00h00’FF00h(CP)

+ 2*bitoff+ 2*(bitoff^FFh)+ 2*(bitoff^0Fh)

bitoffbitoffbitoff

= 00h...7Fh= 80h...EFh= F0h...FFh

RAMSFRGPR

Bit word offset 128 valuesBit word offset 128 valuesBit word offset 16 values

bitaddr Word offset as with bitoffImmediate bit position

bitoffbitpos

= 00h...FFh= 0...15

Any single bit


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2.1.2 - Long addressing modeLong addressing mode uses one of the four DPPregisters to specify a physical 18-bit or 24-bitaddress. Any word or byte data within the entireaddress space can be accessed in this mode. Alldevices support an override mechanism for theDPP addressing scheme (see section 2.1.3 - DPPoverride mechanism).Long addresses (16-bit) are treated in two parts.Bits 13...0 specify a 14-bit data page offset, andbits 15...14 specify the Data Page Pointer (1 of 4).The DPP is used to generate the physical 24-bitaddress (see Figure 1).

All ST10 devices support an address space of upto 16MByte, so only the lower ten bits of theselected DPP register content are concatenatedwith the 14-bit data page offset to build the physi-cal address.

Note: Word accesses on odd byte addressesare not executed, but rather trigger ahardware trap. After reset, the DPP regis-ters are initialized so that all longaddresses are directly mapped onto theidentical physical addresses, within seg-ment 0.

The long addressing mode is referred to by the mnemonic “mem”.

Figure 1 : Interpretation of a 16-bit long address

Table 2 : Summary of long address modes

Mnemo Physical Address Long Address Range Scope of Access

mem (DPP0) || mem^3FFFh 0000h...3FFFh Any Word or Byte

(DPP1) || mem^3FFFh 4000h...7FFFh

(DPP2) || mem^3FFFh 8000h...BFFFh

(DPP3) || mem^3FFFh C000h...FFFFh

mem pag || mem^3FFFh 0000h...FFFFh (14-bit) Any Word or Byte

mem seg || mem 0000h...FFFFh (16-bit) Any Word or Byte

015 14 13

16-bit Long Address

DPP0DPP1DPP2DPP3

14-bit page offset

24-bit Physical Address

selects Data Page Pointer09

023 1314


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2.1.3 - DPP override mechanism

The DPP override mechanism temporarilybypasses the DPP addressing scheme. TheEXTP(R) and EXTS(R) instructions override thisaddressing mechanism. Instruction EXTP(R)replaces the content of the respective DPPregister, while instruction EXTS(R) concatenatesthe complete 16-bit long address with thespecified segment base address. The overridingpage or segment may be specified directly as aconstant (#pag, #seg) or by a word GPR (Rw)(see Figure 2).

2.1.4 - Indirect addressing modes

Indirect addressing modes can be considered as acombination of short and long addressing modes.In this mode, long 16-bit addresses are specifiedindirectly by the contents of a word GPR, which isspecified directly by a short 4-bit address (’Rw’=0to 15). Some indirect addressing modes add aconstant value to the GPR contents before thelong 16-bit address is calculated. Other indirectaddressing modes allow decrementing or incre-menting of the indirect address pointers (GPR con-tent) by 2 or 1 (referring to words or bytes).

In each case, one of the four DPP registers isused to specify the physical 18-bit or 24-bitaddresses. Any word or byte data within the entirememory space can be addressed indirectly. Notethat EXTP(R) and EXTS(R) instructions overridethe DPP mechanism.

Instructions using the lowest four word GPRs(R3...R0) as indirect address pointers are speci-fied by short 2-bit addresses.

Word accesses on odd byte addresses are notexecuted, but rather trigger a hardware trap.After reset, the DPP registers are initialized in away that all indirect long addresses are directlymapped onto the identical physical addresses.Physical addresses are generated from indirectaddress pointers by the following algorithm:1. Calculate the physical address of the wordGPR which is used as indirect address pointer, byusing the specified short address (’Rw’) and thecurrent register bank base address (CP).

GPRAddress = (CP) + 2 x ShortAddress2. Pre-decremented indirect address pointers(‘-Rw’) are decremented by a data-type-depen-dent value (∆ = 1 for byte operations, ∆ = 2 forword operations), before the long 16-bit addressis generated:(GPRAddress) = (GPRAddress) - ∆ [optional step!]3. Calculate the long 16-bit (Rw + #data16 ifselected) address by adding a constant value (ifselected) to the content of the indirect addresspointer:

Long Address = (GPR Address) + Constant4. Calculate the physical 18-bit or 24-bit addressusing the resulting long address and the corre-sponding DPP register content (see long 'mem'addressing modes).Physical Address = (DPPi) + Long Address^3FFFh5. Post-Incremented indirect address pointers(‘Rw+’) are incremented by a data-type-depen-dent value (∆ = 1 for byte operations, ∆ = 2 forword operations):(GPR Address) = (GPR Address) + ∆ [optional step!]

Figure 2 : Overriding the DPP mechanism

015 14 13

16-bit Long Address

#pag 14-bit page offset


015

16-bit Long Address

#seg 16-bit segment offset


EXTP(R):

EXTS(R):


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The following indirect addressing modes are pro-vided:

2.1.5 - ConstantsThe ST10 Family instruction set supports the useof wordwide or bytewide immediate constants. For optimum utilization of the available code stor-age, these constants are represented in theinstruction formats by either 3, 4, 8 or 16 bits. Therefore, short constants are alwayszero-extended, while long constants can be trun-

cated to match the data format required for theoperation:

Note: Immediate constants are always signifiedby a leading number sign “#”.

2.1.6 - Branch target addressing modes

Jump and Call instructions use different address-ing modes to specify the target address and seg-ment.

Relative, absolute and indirect modes can beused to update the Instruction Pointer register(IP), while the Code Segment Pointer register(CSP) can only be updated with an absolutevalue.

A special mode is provided to address theinterrupt and trap jump vector table situated in thelowest portion of code segment 0.

Table 3 : Table of indirect address modes

Mnemonic Notes

[Rw] Most instructions accept any GPR(R15...R0) as indirect address pointer.Some instructions, however, onlyaccept the lower four GPRs (R3...R0).

[Rw+] The specified indirect address pointeris automatically incremented by 2 or 1(for word or byte data operations) afterthe access.

[-Rw] The specified indirect address pointeris automatically decremented by 2 or 1(for word or byte data operations)before the access.

[Rw+#data16] A 16-bit constant and the contents ofthe indirect address pointer are addedbefore the long 16-bit address is calcu-lated.

Table 4 : Table of constants

Mnemonic Word operation Byte operation

#data3 0000h + data3 00h + data3

#data4 0000h + data4 00h + data4

#data8 0000h + data8 data8

#data16 data16 data16 ^ FFh

#mask 0000h + mask mask

Table 5 : Branch target address summary

Mnemonic Target Address Target Segment Valid Address Range

caddr (IP) = caddr - caddr = 0000h...FFFEh

rel (IP) = (IP) + 2*rel - rel = 00h...7Fh

(IP) = (IP) + 2*(~rel+1) - rel = 80h...FFh

[Rw] (IP) = ((CP) + 2*Rw) - Rw = 0...15

seg - (CSP) = seg seg = 0...255

#trap7 (IP) = 0000h + 4*trap7 (CSP) = 0000h trap7 = 00h...7Fh


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caddr

Specifies an absolute 16-bit code address withinthe current segment. Branches MAY NOT betaken to odd code addresses.

Therefore, the least significant bit of ’caddr’ mustalways contain a ’0’, otherwise a hardware trapwould occur.

rel

Represents an 8-bit signed word offset addressrelative to the current Instruction Pointer contentswhich points to the instruction after the branchinstruction.

Depending on the offset address range, either for-ward (’rel’= 00h to 7Fh) or backward (’rel’= 80h toFFh) branches are possible.

The branch instruction itself is repeatedly exe-cuted, when ’rel’ = ’-1’ (FFh) for a word-sizedbranch instruction, or ’rel’ = ’-2’ (FEh) for a dou-ble-word-sized branch instruction.

[Rw]

The 16-bit branch target instruction address isdetermined indirectly by the content of a wordGPR. In contrast to indirect data addresses, indi-rectly specified code addresses are NOT calcu-lated by additional pointer registers (e.g. DPPregisters).

Branches MAY NOT be taken to odd codeaddresses. Therefore, to prevent a hardware trap,the least significant bit of the address pointer GPRmust always contain a ’0.

seg

Specifies an absolute code segment number. Alldevices support 256 different code segments, soonly the eight lower bits of the ’seg’ operand valueare used for updating the CSP register.

#trap7Specifies a particular interrupt or trap number forbranching to the corresponding interrupt or trapservice routine by a jump vector table.

Trap numbers from 00h to 7Fh can be specified,which allows access to any double word codelocation within the address range00’0000h...00’01FCh in code segment 0 (i.e. theinterrupt jump vector table).

For further information on the relation betweentrap numbers and interrupt or trap sources, referto the device user manual section on “Interruptand Trap Functions”.

2.2 - Instruction execution times

The instruction execution time depends on wherethe instruction is fetched from, and where theoperands are read from or written to.

The fastest processing mode is to execute a pro-gram fetched from the internal ROM. In this casemost of the instructions can be processed in justone machine cycle.

All external memory accesses are performed bythe on-chip External Bus Controller (EBC) whichworks in parallel with the CPU.

Instructions from external memory cannot be pro-cessed as fast as instructions from the internalROM, because it is necessary to perform datatransfers sequentially via the external interface.

In contrast to internal ROM program execution,the time required to process an external programadditionally depends on the length of the instruc-tions and operands, on the selected bus mode,and on the duration of an external memory cycle.

Processing a program from the internal RAMspace is not as fast as execution from the internalROM area, but it is flexible (i.e. for loading tempo-rary programs into the internal RAM via the chip'sserial interface, or end-of-line programming viathe bootstrap loader).

The following description evaluates the minimumand maximum program execution times. which issufficient for most requirements. For an exactdetermination of the instructions' state times, thefacilities provided by simulators or emulatorsshould be used.

This section defines measurement units, summa-rizes the minimum (standard) state times of the16-bit microcontroller instructions, and describesthe exceptions from the standard timing.


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2.2.1 - Definition of measurement unitsThe following measurement units are used to define instruction processing times:

[fCPU]: CPU operating frequency (may vary from 1MHz to 80MHz).

[State]: One state time is specified by one CPU clock period. Therefore, one State is used as the basictime unit, because it represents the shortest period of time which has to be considered forinstruction timing evaluations.

1 [State] = 1/fCPU[s] ; for fCPU = variable

= 50[ns] ; for fCPU = 20MHz

[ACT]: ALE (Address Latch Enable) Cycle Time specifies the time required to perform one externalmemory access. One ALE Cycle Time consists of either two (for demultiplexed external busmodes) or three (for multiplexed external bus modes) state times plus a number of state times,which is determined by the number of waitstates programmed in the MCTC (Memory CycleTime Control) and MTTC (Memory Tristate Time Control) bit fields of the SYSCON/BUSCONxregisters.

For demultiplexed external bus modes:

1*ACT = (2 + (15 – MCTC) + (1 – MTTC)) * States

= 100 n... 900 ns ; for fCPU = 20MHz

For multiplexed external bus modes:

1*ACT = (3 + (15 – MCTC) + (1 – MTTC)) * States

= 150ns ... 950ns ; for fCPU = 20MHz

Ttot The total time (Ttot) taken to process a particular part of a program can be calculated by thesum of the single instruction processing times (TIn) of the considered instructions plus an offsetvalue of 6 state times which takes into account the solitary filling of the pipeline:

Ttot =TI1 + TI2 + ... + TIn + 6 * States

TIn The time (TIn) taken to process a single instruction, consists of a minimum number (TImin)plus an additional number (TIadd) of instruction state times and/or ALE Cycle Times:

TIn =TImin + TIadd


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2.2.2 - Minimum state times

The table below shows the minimum number ofstate times required to process an instructionfetched from the internal ROM (TImin (ROM)).This table can also be used to calculate the mini-mum number of state times for instructionsfetched from the internal RAM (TImin (RAM)), orALE Cycle Times for instructions fetched from theexternal memory (TImin (ext)).

Most of the 16-bit microcontroller instructions(except some branch, multiplication, division anda special move instructions) require a minimum oftwo state times. For internal ROM program execu-tion, execution time has no dependence oninstruction length, except for some special branchsituations.

To evaluate the execution time for the injected tar-get instruction of a cache jump instruction, it canbe considered as if it was executed from the inter-nal ROM, regardless of which memory area therest of the current program is really fetched from.

For some of the branch instructions the tablebelow represents both the standard number ofstate times (i.e. the corresponding branch istaken) and an additional TImin value in parenthe-ses, which refers to the case where, either thebranch condition is not met, or a cache jump istaken.

Instructions executed from the internal RAMrequire the same minimum time as they would if

they were fetched from the internal ROM, plus aninstruction-length dependent number of statetimes, as follows:

– For 2-byte instructions: TImin(RAM) = TImin(ROM) + 4 * States

– For 4-byte instructions: TImin(RAM) = TImin(ROM) + 6 * States

Unlike internal ROM program execution, the mini-mum time TImin(ext) to process an externalinstruction also depends on instruction length.TImin(ext) is either 1 ALE Cycle Time for most ofthe 2-byte instructions, or 2 ALE Cycle Times formost of the 4-byte instructions.

The following formula represents the minimumexecution time of instructions fetched from anexternal memory via a 16-bit wide data bus:

– For 2-byte instructions: TImin(ext) = 1*ACT + (TImin(ROM) - 2) * States

– For 4-byte instructions: TImin(ext) = 2*ACTs + (TImin(ROM) - 2) * States

Note: For instructions fetched from an externalmemory via an 8-bit wide data bus, theminimum number of required ALE CycleTimes is twice the number for those of a16-bit wide bus.

2.2.3 - Additional state times

Some operand accesses can extend the execu-tion time of an instruction TIn. Since the additionaltime TIadd is generally caused by internal instruc-tion pipelining, it may be possible to minimize theeffect by rearranging the instruction sequences.Simulators and emulators offer a high level of pro-grammer support for program optimization.

The following operands require additional statetimes:

Internal ROM operand reads:TIadd = 2 * States Both byte and word operand reads always require2 additional state times.

Table 6 : Minimum instruction state times [Unit = ns]

InstructionTImin (ROM)

[States]

TImin (ROM) (20MHz

CPU clk)

CALLI, CALLA

CALLS, CALLR, PCALL

JB, JBC, JNB, JNBS

JMPS

JMPA, JMPI, JMPR

MUL, MULU

DIV, DIVL, DIVU, DIVLU

MOV[B] Rn, [Rm + #data16]

RET, RETI, RETP, RETS

TRAP

All other instructions

4

4

4

4

4

10

20

4

4

4

2

(2)

(2)

(2)

200

200

200

200

200

500

1000

200

200

200

100

(100)

(100)

(100)


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Internal RAM operand reads via indirect addressing modes: TIadd = 0 or 1 * StateReading a GPR or any other directly addressed operand within the internal RAM space does NOT causeadditional state time. However, reading an indirectly addressed internal RAM operand will extend the pro-cessing time by 1 state time, if the preceding instruction auto-increments or auto-decrements a GPR, asshown in the following example:

In this case, the additional time can be avoided by putting another suitable instruction before the instruc-tion In+1 indirectly reading the internal RAM.

Internal SFR operand reads: TIadd = 0, 1 * State or 2 * StatesSFR read accesses do NOT usually require additional processing time. In some rare cases, however,either one or two additional state times will be caused by particular SFR operations:

– Reading an SFR immediately after an instruction, which writes to the internal SFR space, as shown inthe following example:

– Reading the PSW register immediately after an instruction which implicitly updates the flags as shownin the following example:

– Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitlywrites to the SP register, as shown in the following example:

In each of these above cases, the extra state times can be avoided by putting other suitable instructionsbefore the instruction In+1 reading the SFR.

External operand reads: TIadd = 1 * ACTAny external operand reading via a 16-bit wide data bus requires one additional ALE Cycle Time. Read-ing word operands via an 8-bit wide data bus takes twice as much time (2 ALE Cycle Times) as the read-ing of byte operands.

External operand writes: TIadd = 0 * State ... 1 * ACTWriting an external operand via a 16-bit wide data bus takes one additional ALE Cycle Time. For timingcalculation of the external program parts, this extra time must always be considered. The value of TIaddwhich must be considered for timing evaluations of internal program parts, may fluctuate between 0 statetimes and 1 ALE Cycle Time. This is because external writes are normally performed in parallel to otherCPU operations. Thus, TIadd could already have been considered in the standard processing time ofanother instruction. Writing a word operand via an 8-bit wide data bus requires twice as much time (2 ALECycle Times) as the writing of a byte operand.

In : MOV R1, [R0+] ; auto-increment R0

In+1 : MOV [R3], [R2] ; if R2 points into the internal RAM space:

; TIadd = 1 * State

In : MOV T0, #1000h ; write to Timer 0

In+1 : ADD R3, T1 ; read from Timer 1: TIadd = 1 * State

In : ADD R0, #1000h ; implicit modification of PSW flags

In+1 : BAND C, Z ; read from PSW: TIadd = 2 * States

In : MOV SP, #0FB00h ; explicit update of the stack pointer

In+1 : SCXT R1, #1000h ; implicit decrement of the stack pointer:

; TIadd = 2 * States


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Jumps into the internal ROM space: TIadd = 0 or 2 * StatesThe minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2additional state times, if the branch target instruction is a double word instruction at a non-aligned doubleword location (xxx2h, xxx6h, xxxAh, xxxEh), as shown in the following example:

A cache jump, which normally requires just 2 state times, will be extended by 2 additional state times, ifboth the cached jump target instruction and the following instruction are non-aligned double word instruc-tions, as shown in the following example:

If necessary, these extra state times can be avoided by allocating double word jump target instructions toaligned double word addresses (xxx0h, xxx4h, xxx8h, xxxCh).Testing Branch Conditions: TIadd = 0 or 1 * StatesNO extra time is usually required for a conditional branch instructions to decide whether a branch condi-tion is met or not. However, an additional state time is required if the preceding instruction writes to thePSW register, as shown in the following example:

In this case, the extra state time can be intercepted by putting another suitable instruction before the con-ditional branch instruction.

label : .... ; any non-aligned double word instruction

; (e.g. at location 0FFEh)

.... : ....

In+1 : JMPA cc_UC, label ; if a standard branch is taken:

; TIadd = 2 * States (TIn = 6 * States)

label : .... ; any non-aligned double word instruction

; (e.g. at location 12FAh)

In+1 : .... ; any non-aligned double word instruction

; (e.g. at location 12FEh)

In+2 : JMPR cc_UC, label ; provided that a cache jump is taken:

; TIadd = 2 * States (TIn = 4 * States)

In : BSET USR0 ; implicit modification of PSW flags

In+1 : JMPR cc_Z, label ; test condition flag in PSW: TIadd= 1 * State


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Hig

hi

Lo

wxF

xExD

xCxB

xAx9

x8x7

x6x5

x4x3

x2x1

x0

0x

BSET BITaddrQ.q

BCLR BITaddrQ.q

JMPR cc, rel

RO

LM

UL

BF

LDL

AD

DB

AD

DA

DD

BA

DD

AD

DB

AD

DA

DD

BA

DD

AD

DB

AD

D

Rw

n, R

wm

Rw

n, R

wm

BIT

OFF

, MA

SK

, #d

ata 3

Rw

n, [

Rw

i]R

wn,

[Rw

i+]

Rw

n, #

data

3

RE

G, #

data

16M

EM

, RE

GR

EG

, ME

MR

wn, R

wm

1xR

OL

Rw

n, #

d 4M

ULU

BF

LDH

AD

DC

BA

DD

CA

DD

CB

AD

DC

AD

DC

BA

DD

CA

DD

CB

AD

DC

AD

DC

BA

DD

C

2xR

OR

PR

IOR

BC

MP

SU

BB

SU

BS

UB

BS

UB

SU

BB

SU

BS

UB

BS

UB

SU

BB

SU

B

Rw

n, R

wm

Rw

n, R

wm

BIT

add,

BIT

add

Rw

n, [

Rw

i]R

wn,

[Rw

i+]

Rw

n, #

data

3

RE

G, #

data

16M

EM

, RE

GR

EG

, ME

MR

wn, R

wm

3xR

OR

_B

MO

VN

Rw

n, #

d 4B

ITad

d, B

ITad

dS

UB

CB

SU

BC

SU

BC

BS

UB

CS

UB

CB

SU

BC

SU

BC

BS

UB

CS

UB

CB

SU

BC

4xS

HL

DIV

BM

OV

CM

PB

CM

PC

MP

BC

MP

__

CM

PB

CM

PC

MP

BC

MP

Rw

n, R

wm

Rw

nB

ITad

d, B

ITad

dR

wn, [

Rw

i]R

wn,

[Rw

i+]

Rw

n, #

data

3

RE

G, #

data

16M

EM

, RE

GR

EG

, ME

MR

wn, R

wm

5xS

HL

DIV

UB

OR

Rw

n, #

d 4R

wn

BIT

add,

BIT

add

XO

RB

XO

RX

OR

BX

OR

XO

RB

XO

RX

OR

BX

OR

XO

RB

XO

R

6xS

HR

DIV

LB

AN

DA

ND

BA

ND

AN

DB

AN

DA

ND

BA

ND

AN

DB

AN

DA

ND

BA

ND

Rw

n, R

wm

Rw

nB

ITad

d, B

ITad

dR

wn, [

Rw

i]R

wn,

[Rw

i+]

Rw

n, #

data

3

RE

G, #

data

16M

EM

, RE

GR

EG

, ME

MR

wn, R

wm

7xS

HR

DIV

LUB

XO

R

Rw

n, #

d 4R

wn

BIT

add,

BIT

add

OR

BO

RO

RB

OR

OR

BO

RO

RB

OR

OR

BO

R

8x_

_JB

MO

VB

MO

VID

LEC

MP

I1_

MO

VC

oXX

XC

MP

IN

EG

CM

PI1

BIT

add,

RE

L[-

Rw

m],

Rw

nR

wn, #

d 16

[Rw

n],

ME

MR

wn, [

Rw

m⊗

]R

wn, M

EM

Rw

nR

wn,

#d 4

9xJM

PI

TRA

PM

OV

BM

OV

PW

RD

N_

MO

VC

oXX

X

cc, [

Rw

n]

#tra

pJN

BR

wn, [

Rw

m+]

CM

PI2

ME

M, [

Rw

n][ID

XI⊗

], [R

wm

⊗]

CM

PD

2C

PLB

CM

PD

2

Ax

AS

HR

CA

LLI

JBC

MO

VB

MO

VS

RV

WD

TC

MP

D1

DIS

WD

TM

OV

BC

oXX

XC

MP

D1

NE

GB

CM

PD

1

Rw

n, R

wm

cc, [

Rw

n]

BIT

add,

BIT

add

[Rw

n],

Rw

mR

wn, #

d 16

[Rw

n],

ME

MR

wn, R

wm

Rw

n, M

EM

Rw

nR

wn,

#d 4

Bx

AS

HR

CA

LLR

MO

VB

MO

VS

RS

TE

INIT

MO

VB

CoS

TO

RE

Rw

n, #

d 4R

EL

JNB

S[R

wm

], R

wn

CM

PD

2[R

wm

+ #

d 16],

Rw

n

Rw

n, C

oRE

GC

MP

D2

CP

LBC

MP

D2

Cx

NO

PR

ET

CA

LLA

MO

VB

MO

V_

SC

XT

MO

VB

ZM

OV

CoS

TO

RE

MO

VB

Z_

MO

VB

Z

CC

, CA

DD

R[R

wn],

[Rw

m]

RE

G, #

d 16

ME

M, R

EG

Rw

n, [

Rw

m +

#d 1

6][R

wn

⊗],

CoR

EG

RE

G, M

EM

Rw

n, R

wm

Dx

EX

TP

(R)/

RE

TS

CA

LLS

MO

VB

MO

VE

XT

P(R

)/S

CX

TM

OV

CoM

OV

ATO

MIC

/EX

TR

EX

TS

(R)

EX

TS

(R)

RE

G, M

EM

[Rw

m +

#d 1

6],

Rw

n[ID

XI⊗

], [R

wm

⊗]

#dat

a 2

Rw

m, #

d 2S

EG

, CA

DD

DR

[Rw

n+],

[Rw

m]

#pa

g, #

data

2M

OV

BS

MO

VB

SM

OV

BS

Ex

PU

SH

RE

TP

JMPA

MO

VB

MO

VM

OV

BM

OV

_M

OV

B_

PC

ALL

MO

VB

MO

V

RE

GR

EG

CC

, CA

DD

R[R

wn],

[Rw

m+]

RE

G, D

ata#

16R

wn, [

Rw

m +

#d 1

6]R

EG

, CA

DD

RR

wn, #

data

4

Fx

JMP

S_

_M

OV

BM

OV

_M

OV

BM

OV

BM

OV

MO

VB

MO

V

PO

PR

ET

IS

EG

, CA

DD

RM

EM

, RE

G[R

wm

+ #

d 16],

Rw

nR

EG

, ME

MR

wn, #

data

4

2.3 - Instruction set summary

The following table lists the instruction mnemonic by hex-code with operand.

Table 7 : Instruction mnemonic by hex-code with operand


14/172

Table 8 lists the instructions by their mnemonic and identifies the addressing modes that may be used witha specific instruction and the instruction length, depending on the selected addressing mode (in bytes).

Table 8 : Mnemonic vs address mode & number of bytes

Mnemonic Addressing Modes Bytes Mnemonic Addressing Modes Bytes

ADD[B] Rwn1, Rwm

1 2 CPL[B] Rwn1 2

ADDC[B] Rwn1, [Rwi]

2 NEG[B]

AND[B] Rwn1, [Rwi+]

2 DIV Rwn 2

OR[B] Rwn1, #data3

2 DIVL

SUB[B] reg, #data16 4 DIVLU

SUBC[B] reg, mem 4 DIVUXOR[B] mem, reg 4 MUL Rwn, Rwm 2

MULUASHR Rwn, Rwm 2 CMPD1/2 Rwn, #data4 2

ROL / ROR Rwn, #data4 2 CMPI1/2 Rwn, #data16 4

SHL / SHR Rwn, mem 4

BAND bitaddrZ.z, bitaddrQ.q 4 CMP[B] Rwn, Rwm 1

BCMP Rwn, [Rwi] 1 2

BMOV Rwn, [Rwi+]1 2

BMOVN Rwn, #data31 2

BOR / BXOR reg, #data16 4

reg, mem 4BCLR bitaddrQ.q, 2 CALLA cc, caddr 4

BSET JMPABFLDH bitoffQ, #mask8, #data8 4 CALLI cc, [Rwn] 2

BFLDL JMPI

MOV[B] Rwn1, Rwm

1 2 CALLS seg, caddr 4

Rwn1, #data4

2 JMPS

Rwn1, [Rwm]

2 CALLR rel 2

Rwn1, [Rwm+]

2 JMPR cc, rel 2

[Rwm], Rwn1 2 JB bitaddrQ.q, rel 4

[-Rwm], Rwn 1 2 JBC

[Rwn], [Rwm] 2 JNB

[Rwn+], [Rwm] 2 JNBS

[Rwn], [Rwm+] 2 PCALL reg, caddr 4

reg, #data16 4 POP reg 2

Rwn, [Rwm+#data16]1 4 PUSH

[Rwm+#data16], Rwn 1 4 RETP

[Rwn], mem 4 SCXT reg, #data16 4

mem, [Rwn] 4 reg, mem 4

reg, mem 4 PRIOR Rwn, Rwm 2

mem, reg 4


15/172

Note 1. Byte oriented instructions (suffix ‘B’) use Rb instead of Rw (not with [Rwi]!).

2.4 - Instruction set ordered by functional groupThe minimum number of state times required forinstruction execution are given for the followingconfigurations: internal ROM, internal RAM, exter-nal memory with a 16-bit demultiplexed and multi-plexed bus or an 8-bit demultiplexed andmultiplexed bus. These state time figures do nottake into account possible wait states on externalbusses or possible additional state times inducedby operand fetches. The following notes apply tothis summary:

Data addressing modesRw: Word GPR (R0, R1, … , R15).Rb: Byte GPR (RL0, RH0, …, RL7, RH7).

reg: SFR or GPR (in case of a byte operationon an SFR, only the low byte can beaccessed via ‘reg’).

mem: Direct word or byte memory location.[…]: Indirect word or byte memory location.

(Any word GPR can be used as indirectaddress pointer, except for the arithmetic,logical and compare instructions, whereonly R0 to R3 are allowed).

bitaddr: Direct bit in the bit-addressable memoryarea.

bitoff: Direct word in the bit-addressable mem-ory area.

#datax: Immediate constant (the number of signif-icant bits that can be user-specified isgiven by the appendix “x”).

#mask8:Immediate 8-bit mask used for bit-fieldmodifications.

Multiply and divide operationsThe MDL and MDH registers are implicit sourceand/or destination operands of the multiply anddivide instructions.

Branch target addressing modescaddr: Direct 16-bit jump target address

(Updates the Instruction Pointer).seg: Direct 8-bit segment address (Updates

the Code Segment Pointer).rel: Signed 8-bit jump target word offset

address relative to the InstructionPointer of the following instruction.

#trap7: Immediate 7-bit trap or interrupt number.

Extension operationsThe EXT* instructions override the standard DPPaddressing scheme:#pag: Immediate 10-bit page address.#seg: Immediate 8-bit segment address.

MOVBS Rwn, Rbm 2 TRAP #trap7 2

MOVBZ reg, mem 4 ATOMIC #data2 2

mem, reg 4 EXTR

EXTS Rwm, #data2 2 EXTP Rwm, #data2 2

EXTSR #seg, #data2 4 EXTPR #pag, #data2 4

NOP - 2 SRST/IDLE - 4RET PWRDNRETI SRVWDTRETS = DISWDT

EINIT

Table 8 : Mnemonic vs address mode & number of bytes (continued)

Mnemonic Addressing Modes Bytes Mnemonic Addressing Modes Bytes


16/172

Branch condition codescc: Symbolically specifiable condition codes

cc_UC Unconditionalcc_Z Zerocc_NZ Not Zerocc_V Overflowcc_NV No Overflowcc_N Negativecc_NN Not Negativecc_C Carrycc_NC No Carrycc_EQ Equal

cc_NE Not Equalcc_ULT Unsigned Less Thancc_ULE Unsigned Less Than or Equalcc_UGE Unsigned Greater Than or Equalcc_UGT Unsigned Greater Thancc_SLE Signed Less Than or Equalcc_SLT Signed Less Thancc_SGE Signed Greater Than or Equalcc_SGT Signed Greater Thancc_NET Not Equal and Not End-of-Table

Table 9 : Arithmetic instructions

Mnemonic Description

Int.

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

ux

Byt

es

ADD Rw, Rw Add direct word GPR to direct GPR 2 6 2 3 4 6 2

ADD Rw, [Rw] Add indirect word memory to direct GPR 2 6 2 3 4 6 2

ADD Rw, [Rw+] Add indirect word memory to direct GPR and post- increment source pointer by 2

2 6 2 3 4 6 2

ADD Rw, #data3 Add immediate word data to direct GPR 2 6 2 3 4 6 2

ADD reg, #data16 Add immediate word data to direct register 2 8 4 6 8 12 4

ADD reg, mem Add direct word memory to direct register 2 8 4 6 8 12 4

ADD mem, reg Add direct word register to direct memory 2 8 4 6 8 12 4

ADDB Rb, Rb Add direct byte GPR to direct GPR 2 6 2 3 4 6 2

ADDB Rb, [Rw] Add indirect byte memory to direct GPR 2 6 2 3 4 6 2

ADDB Rb, [Rw+] Add indirect byte memory to direct GPR and post-increment source pointer by 1

2 6 2 3 4 6 2

ADDB Rb, #data3 Add immediate byte data to direct GPR 2 6 2 3 4 6 2

ADDB reg, #data16 Add immediate byte data to direct register 2 8 4 6 8 12 4

ADDB reg, mem Add direct byte memory to direct register 2 8 4 6 8 12 4

ADDB mem, reg Add direct byte register to direct memory 2 8 4 6 8 12 4

ADDC Rw, Rw Add direct word GPR to direct GPR with Carry 2 6 2 3 4 6 2

ADDC Rw, [Rw] Add indirect word memory to direct GPR with Carry 2 6 2 3 4 6 2

ADDC Rw, [Rw+] Add indirect word memory to direct GPR with Carry and post-increment source pointer by 2

2 6 2 3 4 6 2

ADDC Rw, #data3 Add immediate word data to direct GPR with Carry 2 6 2 3 4 6 2

ADDC reg, #data16 Add immediate word data to direct register with Carry 2 8 4 6 8 12 4

ADDC reg, mem Add direct word memory to direct register with Carry 2 8 4 6 8 12 4

ADDC mem, reg Add direct word register to direct memory with Carry 2 8 4 6 8 12 4


17/172

ADDCB Rb, Rb Add direct byte GPR to direct GPR with Carry 2 6 2 3 4 6 2

ADDCB Rb, [Rw] Add indirect byte memory to direct GPR with Carry 2 6 2 3 4 6 2

ADDCB Rb, [Rw+] Add indirect byte memory to direct GPR with Carry and post-increment source pointer by 1

2 6 2 3 4 6 2

ADDCB Rb, #data3 Add immediate byte data to direct GPR with Carry 2 6 2 3 4 6 2

ADDCB reg, #data16 Add immediate byte data to direct register with Carry 2 8 4 6 8 12 4

ADDCB reg, mem Add direct byte memory to direct register with Carry 2 8 4 6 8 12 4

ADDCB mem, reg Add direct byte register to direct memory with Carry 2 8 4 6 8 12 4

CPL Rw Complement direct word GPR 2 6 2 3 4 6 2

CPLB Rb Complement direct byte GPR 2 6 2 3 4 6 2

DIV Rw Signed divide register MDL by direct GPR (16-/16-bit)

20 24 20 21 22 24 2

DIVL Rw Signed long divide register MD by direct GPR (32-/16-bit)

20 24 20 21 22 24 2

DIVLU Rw Unsigned long divide register MD by direct GPR (32-/16-bit)

20 24 20 21 22 24 2

DIVU Rw Unsigned divide register MDL by direct GPR (16-/16-bit)

20 24 20 21 22 24 2

MUL Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) 10 14 10 11 12 14 2

MULU Rw, Rw Unsigned multiply direct GPR by direct GPR (16-16-bit) 10 14 10 11 12 14 2

NEG Rw Negate direct word GPR 2 6 2 3 4 6 2

NEGB Rb Negate direct byte GPR 2 6 2 3 4 6 2

SUB Rw, Rw Subtract direct word GPR from direct GPR 2 6 2 3 4 6 2

SUB Rw, [Rw] Subtract indirect word memory from direct GPR 2 6 2 3 4 6 2

SUB Rw, [Rw+] Subtract indirect word memory from direct GPR & post-increment source pointer by 2

2 6 2 3 4 6 2

SUB Rw, #data3 Subtract immediate word data from direct GPR 2 6 2 3 4 6 2

SUB reg, #data16 Subtract immediate word data from direct register 2 8 4 6 8 12 4

SUB reg, mem Subtract direct word memory from direct register 2 8 4 6 8 12 4

SUB mem, reg Subtract direct word register from direct memory 2 8 4 6 8 12 4

SUBB Rb, Rb Subtract direct byte GPR from direct GPR 2 6 2 3 4 6 2

SUBB Rb, [Rw] Subtract indirect byte memory from direct GPR 2 6 2 3 4 6 2

SUBB Rb, [Rw+] Subtract indirect byte memory from direct GPR & post-increment source pointer by 1

2 6 2 3 4 6 2

SUBB Rb, #data3 Subtract immediate byte data from direct GPR 2 6 2 3 4 6 2

SUBB reg, #data16 Subtract immediate byte data from direct register 2 8 4 6 8 12 4

Table 9 : Arithmetic instructions (continued)


Int.

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

ux

Byt

es


18/172

SUBB reg, mem Subtract direct byte memory from direct register 2 8 4 6 8 12 4

SUBB mem, reg Subtract direct byte register from direct memory 2 8 4 6 8 12 4

SUBC Rw, Rw Subtract direct word GPR from direct GPR with Carry 2 6 2 3 4 6 2

SUBC Rw, [Rw] Subtract indirect word memory from direct GPR with Carry 2 6 2 3 4 6 2

SUBC Rw, [Rw+] Subtract indirect word memory from direct GPR with Carry and post-increment source pointer by 2

2 6 2 3 4 6 2

SUBC Rw, #data3 Subtract immediate word data from direct GPR with Carry 2 6 2 3 4 6 2

SUBC reg, #data16 Subtract immediate word data from direct register with Carry

2 8 4 6 8 12 4

SUBC reg, mem Subtract direct word memory from direct register with Carry 2 8 4 6 8 12 4

SUBC mem, reg Subtract direct word register from direct memory with Carry 2 8 4 6 8 12 4

SUBCB Rb, Rb Subtract direct byte GPR from direct GPR with Carry 2 6 2 3 4 6 2

SUBCB Rb, [Rw] Subtract indirect byte memory from direct GPR with Carry 2 6 2 3 4 6 2

SUBCB Rb, [Rw+] Subtract indirect byte memory from direct GPR with Carry and post-increment source pointer by 1

2 6 2 3 4 6 2

SUBCB Rb, #data3 Subtract immediate byte data from direct GPR with Carry 2 6 2 3 4 6 2

SUBCB reg, #data16 Subtract immediate byte data from direct register with Carry 2 8 4 6 8 12 4

SUBCB reg, mem Subtract direct byte memory from direct register with Carry 2 8 4 6 8 12 4

SUBCB mem, reg Subtract direct byte register from direct memory with Carry 2 8 4 6 8 12 4

Table 9 : Arithmetic instructions (continued)


Int.

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

ux

Byt

es

Table 10 : Logical instructions


Int

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

UX

Byt

es

AND Rw, Rw Bitwise AND direct word GPR with direct GPR 2 6 2 3 4 6 2

AND Rw, [Rw] Bitwise AND indirect word memory with direct GPR 2 6 2 3 4 6 2

AND Rw, [Rw+] Bitwise AND indirect word memory with direct GPR and post-increment source pointer by 2

2 6 2 3 4 6 2

AND Rw, #data3 Bitwise AND immediate word data with direct GPR 2 6 2 3 4 6 2

AND reg, #data16 Bitwise AND immediate word data with direct register 2 8 4 6 8 12 4

AND reg, mem Bitwise AND direct word memory with direct register 2 8 4 6 8 12 4

AND mem, reg Bitwise AND direct word register with direct memory 2 8 4 6 8 12 4

ANDB Rb, Rb Bitwise AND direct byte GPR with direct GPR 2 6 2 3 4 6 2

ANDB Rb, [Rw] Bitwise AND indirect byte memory with direct GPR 2 6 2 3 4 6 2


19/172

ANDB Rb, [Rw+] Bitwise AND indirect byte memory with direct GPR and post-increment source pointer by 1

2 6 2 3 4 6 2

ANDB Rb, #data3 Bitwise AND immediate byte data with direct GPR 2 6 2 3 4 6 2

ANDB reg, #data16 Bitwise AND immediate byte data with direct register 2 8 4 6 8 12 4

ANDB reg, mem Bitwise AND direct byte memory with direct register 2 8 4 6 8 12 4

ANDB mem, reg Bitwise AND direct byte register with direct memory 2 8 4 6 8 12 4

OR Rw, Rw Bitwise OR direct word GPR with direct GPR 2 6 2 3 4 6 2

OR Rw, [Rw] Bitwise OR indirect word memory with direct GPR 2 6 2 3 4 6 2

OR Rw, [Rw+] Bitwise OR indirect word memory with direct GPR and post-increment source pointer by 2

2 6 2 3 4 6 2

OR Rw, #data3 Bitwise OR immediate word data with direct GPR 2 6 2 3 4 6 2

OR reg, #data16 Bitwise OR immediate word data with direct register 2 8 4 6 8 12 4

OR reg, mem Bitwise OR direct word memory with direct register 2 8 4 6 8 12 4

OR mem, reg Bitwise OR direct word register with direct memory 2 8 4 6 8 12 4

ORB Rb, Rb Bitwise OR direct byte GPR with direct GPR 2 6 2 3 4 6 2

ORB Rb, [Rw] Bitwise OR indirect byte memory with direct GPR 2 6 2 3 4 6 2

ORB Rb, [Rw+] Bitwise OR indirect byte memory with direct GPR andpost-increment source pointer by 1

2 6 2 3 4 6 2

ORB Rb, #data3 Bitwise OR immediate byte data with direct GPR 2 6 2 3 4 6 2

ORB reg, #data16 Bitwise OR immediate byte data with direct register 2 8 4 6 8 12 4

ORB reg, mem Bitwise OR direct byte memory with direct register 2 8 4 6 8 12 4

ORB mem, reg Bitwise OR direct byte register with direct memory 2 8 4 6 8 12 4

XOR Rw, Rw Bitwise XOR direct word GPR with direct GPR 2 6 2 3 4 6 2

XOR Rw, [Rw] Bitwise XOR indirect word memory with direct GPR 2 6 2 3 4 6 2

XOR Rw, [Rw+] Bitwise XOR indirect word memory with direct GPR and post-increment source pointer by 2

2 6 2 3 4 6 2

XOR Rw, #data3 Bitwise XOR immediate word data with direct GPR 2 6 2 3 4 6 2

XOR reg, #data16 Bitwise XOR immediate word data with direct register 2 8 4 6 8 12 4

XOR reg, mem Bitwise XOR direct word memory with direct register 2 8 4 6 8 12 4

XOR mem, reg Bitwise XOR direct word register with direct memory 2 8 4 6 8 12 4

XORB Rb, Rb Bitwise XOR direct byte GPR with direct GPR 2 6 2 3 4 6 2

XORB Rb, [Rw] Bitwise XOR indirect byte memory with direct GPR 2 6 2 3 4 6 2

XORB Rb, [Rw+] Bitwise XOR indirect byte memory with direct GPR and post-increment source pointer by 1

2 6 2 3 4 6 2

XORB Rb, #data3 Bitwise XOR immediate byte data with direct GPR 2 6 2 3 4 6 2

XORB reg, #data16 Bitwise XOR immediate byte data with direct register 2 8 4 6 8 12 4

XORB reg, mem Bitwise XOR direct byte memory with direct register 2 8 4 6 8 12 4

XORB mem, reg Bitwise XOR direct byte register with direct memory 2 8 4 6 8 12 4

Table 10 : Logical instructions (continued)


Int

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

UX

Byt

es


20/172

Table 11 : Boolean bit map instructions (continued)


Int.

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

ux

Byt

es

BANDbitaddr, bitaddr

AND direct bit with direct bit 2 8 4 6 8 12 4

BCLR bitaddr Clear direct bit 2 6 2 3 4 6 2

BCMPbitaddr, bitaddr

Compare direct bit to direct bit 2 8 4 6 8 12 4

BFLDHbitoff, #mask8,#data8

Bitwise modify masked high byte of bit-addressable direct word memory with immediate data

2 8 4 6 8 12 4

BFLDL bitoff, #mask8, #data8

Bitwise modify masked low byte of bit-addressable direct word memory with immediate data

2 8 4 6 8 12 4

BMOVbitaddr, bitaddr

Move direct bit to direct bit 2 8 4 6 8 12 4

BMOVNbitaddr, bitaddr

Move negated direct bit to direct bit 2 8 4 6 8 12 4

BORbitaddr, bitaddr

OR direct bit with direct bit 2 8 4 6 8 12 4

BSET bitaddr Set direct bit 2 6 2 3 4 6 2

BXORbitaddr, bitaddr

XOR direct bit with direct bit 2 8 4 6 8 12 4

CMP Rw, Rw Compare direct word GPR to direct GPR 2 6 2 3 4 6 2

CMP Rw, [Rw] Compare indirect word memory to direct GPR 2 6 2 3 4 6 2

CMP Rw, [Rw+] Compare indirect word memory to direct GPR and post-increment source pointer by 2

2 6 2 3 4 6 2

CMP Rw, #data3 Compare immediate word data to direct GPR 2 6 2 3 4 6 2

CMP reg, #data16 Compare immediate word data to direct register 2 8 4 6 8 12 4

CMP reg, mem Compare direct word memory to direct register 2 8 4 6 8 12 4

CMPB Rb, Rb Compare direct byte GPR to direct GPR 2 6 2 3 4 6 2

CMPB Rb, [Rw] Compare indirect byte memory to direct GPR 2 6 2 3 4 6 2

CMPB Rb, [Rw+] Compare indirect byte memory to direct GPR and post-increment source pointer by 1

2 6 2 3 4 6 2

CMPB Rb, #data3 Compare immediate byte data to direct GPR 2 6 2 3 4 6 2

CMPB reg, #data16 Compare immediate byte data to direct register 2 8 4 6 8 12 4

CMPB reg, mem Compare direct byte memory to direct register 2 8 4 6 8 12 4


21/172

Table 12 : Compare and loop instructions (continued)


Int.

RO

M

Int.

RA

M

16-b

it N

-Mu

x

16-b

it M

ux

8-b

it N

-Mu

x

8-b

it M

ux

Byt

es

CMPD1 Rw, #data4 Compare immediate word data to direct GPR and decrement GPR by 1

2 6 2 3 4 6 2


2 8 4 6 8 12 4

CMPD1 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1

2 8 4 6 8 12 4


2 6 2 3 4 6 2


2 8 4 6 8 12 4

CMPD2 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 2

2 8 4 6 8 12 4

CMPI1 Rw, #data4 Compare immediate word data to direct GPR and increment GPR by 1

2 6 2 3 4 6 2


2 8 4 6 8 12 4

CMPI1 Rw, mem Compare direct word memory to direct GPR and increment GPR by 1

2 8 4 6 8 12 4


2 6 2 3 4 6 2


2 8 4 6 8 12 4

CMPI2 Rw, mem Compare direct word memory to direct GPR and increment GPR by 2

2 8 4 6 8 12 4

Table 13 : Prioritize instructions


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PRIOR Rw, Rw Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR

2 6 2 3 4 6 2


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Table 14 : Shift and rotate instructions (continued)


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ASHR Rw, Rw Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by direct GPR

2 6 2 3 4 6 2

ASHR Rw, #data4 Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by immediate data

2 6 2 3 4 6 2

ROL Rw, Rw Rotate left direct word GPR; number of shift cycles specified by direct GPR

2 6 2 3 4 6 2

ROL Rw, #data4 Rotate left direct word GPR; number of shift cycles specified by immediate data

2 6 2 3 4 6 2

ROR Rw, Rw Rotate right direct word GPR; number of shift cycles specified by direct GPR

2 6 2 3 4 6 2

ROR Rw, #data4 Rotate right direct word GPR; number of shift cycles specified by immediate data

2 6 2 3 4 6 2

SHL Rw, Rw Shift left direct word GPR; number of shift cycles specified by direct GPR

2 6 2 3 4 6 2

SHL Rw, #data4 Shift left direct word GPR; number of shift cycles specified by immediate data

2 6 2 3 4 6 2

SHR Rw, Rw Shift right direct word GPR; number of shift cycles specified by direct GPR

2 6 2 3 4 6 2

SHR Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data

2 6 2 3 4 6 2

Table 15 : Data movement instructions


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MOV Rw, Rw Move direct word GPR to direct GPR 2 6 2 3 4 6 2

MOV Rw, #data4 Move immediate word data to direct GPR 2 6 2 3 4 6 2

MOV reg, #data16 Move immediate word data to direct register 2 8 4 6 8 12 4

MOV Rw, [Rw] Move indirect word memory to direct GPR 2 6 2 3 4 6 2

MOV Rw, [Rw+] Move indirect word memory to direct GPR and post-increment source pointer by 2

2 6 2 3 4 6 2

MOV [Rw], Rw Move direct word GPR to indirect memory 2 6 2 3 4 6 2

MOV [-Rw], Rw Pre-decrement destination pointer by 2 and move direct word GPR to indirect memory

2 6 2 3 4 6 2

MOV [Rw], [Rw] Move indirect word memory to indirect memory 2 6 2 3 4 6 2

MOV [Rw+], [Rw] Move indirect word memory to indirect memory & post-increment destination pointer by 2

2 6 2 3 4 6 2

MOV [Rw], [Rw+] Move indirect word memory to indirect memory & post-increment source pointer by 2

2 6 2 3 4 6 2


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MOV Rw, [Rw+ #data16] Move indirect word memory by base plus constant to direct GPR

4 10 6 8 10 14 4

MOV [Rw+ #data16], Rw Move direct word GPR to indirect memory by base plus constant

2 8 4 6 8 12 4

MOV [Rw], mem Move direct word memory to indirect memory 2 8 4 6 8 12 4

MOV mem, [Rw] Move indirect word memory to direct memory 2 8 4 6 8 12 4

MOV reg, mem Move direct word memory to direct register 2 8 4 6 8 12 4

MOV mem, reg Move direct word register to direct memory 2 8 4 6 8 12 4

MOVB Rb, Rb Move direct byte GPR to direct GPR 2 6 2 3 4 6 2

MOVB Rb, #data4 Move immediate byte data to direct GPR 2 6 2 3 4 6 2

MOVB reg, #data16 Move immediate byte data to direct register 2 8 4 6 8 12 4

MOVB Rb, [Rw] Move indirect byte memory to direct GPR 2 6 2 3 4 6 2

MOVB Rb, [Rw+] Move indirect byte memory to direct GPR and post-increment source pointer by 1

2 6 2 3 4 6 2

MOVB [Rw], Rb Move direct byte GPR to indirect memory 2 6 2 3 4 6 2

MOVB [-Rw], Rb Pre-decrement destination pointer by 1 and move direct byte GPR to indirect memory

2 6 2 3 4 6 2

MOVB [Rw], [Rw] Move indirect byte memory to indirect memory 2 6 2 3 4 6 2

MOVB [Rw+], [Rw] Move indirect byte memory to indirect memory and post-increment destination pointer by 1

2 6 2 3 4 6 2

MOVB [Rw], [Rw+] Move indirect byte memory to indirect memory and post-increment source pointer by 1

2 6 2 3 4 6 2

MOVB Rb, [Rw+ #data16] Move indirect byte memory by base plus constant to direct GPR

4 10 6 8 10 14 4

MOVB [Rw+ #data16], Rb Move direct byte GPR to indirect memory by base plus constant

2 8 4 6 8 12 4

MOVB [Rw], mem Move direct byte memory to indirect memory 2 8 4 6 8 12 4

MOVB mem, [Rw] Move indirect byte memory to direct memory 2 8 4 6 8 12 4

MOVB reg, mem Move direct byte memory to direct register 2 8 4 6 8 12 4

MOVB mem, reg Move direct byte register to direct memory 2 8 4 6 8 12 4

MOVBS Rw, Rb Move direct byte GPR with sign extension to direct word GPR

2 6 2 3 4 6 2

MOVBS reg, mem Move direct byte memory with sign extension to direct word register

2 8 4 6 8 12 4

MOVBS mem, reg Move direct byte register with sign extension to direct word memory

2 8 4 6 8 12 4

MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct word GPR

2 6 2 3 4 6 2

MOVBZ reg, mem Move direct byte memory with zero extension to direct word register

2 8 4 6 8 12 4

MOVBZ mem, reg Move direct byte register with zero extension to direct word memory

2 8 4 6 8 12 4

Table 15 : Data movement instructions (continued)


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8-b

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Table 16 : Jump and Call Instructions (continued)


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CALLA cc, caddr Call absolute subroutine if condition is met 4/2 10/8 6/4 8/6 10/8 14/12 4

CALLI cc, [Rw] Call indirect subroutine if condition is met 4/2 8/6 4/2 5/3 6/4 8/6 2

CALLR rel Call relative subroutine 4 8 4 5 6 8 2

CALLS seg, caddr Call absolute subroutine in any code segment 4 10 6 8 10 14 4

JB bitaddr, rel Jump relative if direct bit is set 4 10 6 8 10 14 4

JBC bitaddr, rel Jump relative and clear bit if direct bit is set 4 10 6 8 10 14 4

JMPA cc, caddr Jump absolute if condition is met 4/2 10/8 6/4 8/6 10/8 14/12 4

JMPI cc, [Rw] Jump indirect if condition is met 4/2 8/6 4/2 5/3 6/4 8/6 2

JMPR cc, rel Jump relative if condition is met 4/2 8/6 4/2 5/3 6/4 8/6 2

JMPS seg, caddr Jump absolute to a code segment 4 10 6 8 10 14 4

JNB bitaddr, rel Jump relative if direct bit is not set 4 10 6 8 10 14 4

JNBS bitaddr, rel Jump relative and set bit if direct bit is not set 4 10 6 8 10 14 4

PCALL reg, caddr Push direct word register onto system stack and call absolute subroutine

4 10 6 8 10 14 4

TRAP #trap7 Call interrupt service routine via immediate trap number

4 8 4 5 6 8 2

Table 17 : System Stack Instructions


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POP reg Pop direct word register from system stack 2 6 2 3 4 6 2

PUSH reg Push direct word register onto system stack 2 6 2 3 4 6 2

SCXT reg, #data16 Push direct word register onto system stack and update register with immediate data

2 8 4 6 8 12 4

SCXT reg, mem Push direct word register onto system stack and update register with direct memory

2 8 4 6 8 12 4

Table 18 : Return Instructions


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RET Return from intra-segment subroutine 4 8 4 5 6 8 2

RETI Return from interrupt service subroutine 4 8 4 5 6 8 2

RETP reg Return from intra-segment subroutine and pop direct word register from system stack

4 8 4 5 6 8 2

RETS Return from inter-segment subroutine 4 8 4 5 6 8 2


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Table 19 : System Control Instructions (continued)

Note 1. The EXT instructions override the standard DPP addressing sheme.


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ATOMIC #data2 Begin ATOMIC sequence 1 2 6 2 3 4 6 2

DISWDT Disable Watchdog Timer 2 8 4 6 8 12 4

EINIT Signify End-of-Initialization on RSTOUT-pin 2 8 4 6 8 12 4

EXTR #data2 Begin EXTended Register sequence 1 2 6 2 3 4 6 2

EXTP Rw, #data2 Begin EXTended Page sequence1 2 6 2 3 4 6 2

EXTP #pag, #data2 Begin EXTended Page sequence1 2 8 4 6 8 12 4

EXTPR Rw, #data2 Begin EXTended Page and Register sequence 1 2 6 2 3 4 6 2

EXTPR #pag, #data2 Begin EXTended Page and Register sequence 1 2 8 4 6 8 12 4

EXTS Rw, #data2 Begin EXTended Segment sequence1 2 6 2 3 4 6 2

EXTS #seg, #data2 Begin EXTended Segment sequence1 2 8 4 6 8 12 4

EXTSR Rw, #data2 Begin EXTended Segment and Register sequence 1 2 6 2 3 4 6 2

EXTSR #seg, #data2 Begin EXTended Segment and Register sequence 1 2 8 4 6 8 12 4

IDLE Enter Idle Mode 2 8 4 6 8 12 4

PWRDN Enter Power Down Mode (supposes NMI-pin is low) 2 8 4 6 8 12 4

SRST Software Reset 2 8 4 6 8 12 4

SRVWDT Service Watchdog Timer 2 8 4 6 8 12 4

Table 20 : Miscellaneous instructions


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NOP Null operation 2 6 2 3 4 6 2


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2.5 - Instruction set ordered by opcodes

The following pages list the instruction set orderedby their hexadecimal opcodes. This is used toidentify specific instructions when reading execut-able code, i.e. during the debugging phase.

Notes for Opcode Lists

1. Some instructions are encoded by means ofadditional bits in the operand field of the instruction

For these instructions only the lowest four GPRs,R0 to R3, can be used as indirect addresspointers.

2. Some instructions are encoded by means ofadditional bits in the operand field of the instruc-tion.

Notes on the JMPR instructions

The condition code to be tested for the JMPRinstructions is specified by the opcode. Two mne-monic representation alternatives exist for someof the condition codes.

Notes on the BCLR and BSET instructions

The position of the bit to be set or to be cleared isspecified by the opcode. The operand “bitaddrQ.q”(where q=0 to 15) refers to a particular bit within abit-addressable word.

Notes on the undefined opcodes

A hardware trap occurs when one of the unde-fined opcodes signified by ‘----’ is decoded by theCPU.

x0h - x7h:Rw, #data3or Rb, #data3x8h - xBh:Rw, [Rw] or Rb, [Rw]

xCh - xFh Rw, [Rw+] or Rb, [Rw+]

00xx.xxxx: EXTS or ATOMIC

01xx.xxxx: EXTP

10xx.xxxx: EXTSR or EXTR

11xx.xxxx: EXTPR

00xx.xxxx: EXTS or ATOMIC

Table 21 : Instruction set ordered by Hex code

Hex- code Number of Bytes Mnemonic Operand

00 2 ADD Rwn, Rwm

01 2 ADDB Rbn, Rbm

02 4 ADD reg, mem

03 4 ADDB reg, mem

04 4 ADD mem, reg

05 4 ADDB mem, reg

06 4 ADD reg, #data16

07 4 ADDB reg, #data16

08 2 ADD Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

09 2 ADDB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

0A 4 BFLDL bitoffQ, #mask8, #data8

0B 2 MUL Rwn, Rwm

0C 2 ROL Rwn, Rwm

0D 2 JMPR cc_UC, rel

0E 2 BCLR bitaddrQ.0

0F 2 BSET bitaddrQ.0

10 2 ADDC Rwn, Rwm

11 2 ADDCB Rbn, Rbm


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12 4 ADDC reg, mem

13 4 ADDCB reg, mem

14 4 ADDC mem, reg

15 4 ADDCB mem, reg

16 4 ADDC reg, #data16

17 4 ADDCB reg, #data16

18 2 ADDC Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

19 2 ADDCB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

1A 4 BFLDH bitoffQ, #mask8, #data8

1B 2 MULU Rwn, Rwm

1C 2 ROL Rwn, #data4

1D 2 JMPR cc_NET, rel



20 2 SUB Rwn, Rwm

21 2 SUBB Rbn, Rbm

22 4 SUB reg, mem

23 4 SUBB reg, mem

24 4 SUB mem, reg

25 4 SUBB mem, reg

26 4 SUB reg, #data16

27 4 SUBB reg, #data16

28 2 SUB Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

29 2 SUBB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

2A 4 BCMP bitaddrZ.z, bitaddrQ.q

2B 2 PRIOR Rwn, Rwm

2C 2 ROR Rwn, Rwm

2D 2 JMPR cc_EQ, rel or cc_Z, rel



30 2 SUBC Rwn, Rwm

31 2 SUBCB Rbn, Rbm

32 4 SUBC reg, mem

33 4 SUBCB reg, mem

Table 21 : Instruction set ordered by Hex code (continued)



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34 4 SUBC mem, reg

35 4 SUBCB mem, reg

36 4 SUBC reg, #data16

37 4 SUBCB reg, #data16

38 2 SUBC Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

39 2 SUBCB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

3A 4 BMOVN bitaddrZ.z, bitaddrQ.q

3B - - -

3C 2 ROR Rwn, #data4

3D 2 JMPR cc_NE, rel or cc_NZ, rel



40 2 CMP Rwn, Rwm

41 2 CMPB Rbn, Rbm

42 4 CMP reg, mem

43 4 CMPB reg, mem

44 - - -

45 - - -

46 4 CMP reg, #data16

47 4 CMPB reg, #data16

48 2 CMP Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

49 2 CMPB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

4A 4 BMOV bitaddrZ.z, bitaddrQ.q

4B 2 DIV Rwn

4C 2 SHL Rwn, Rwm

4D 2 JMPR cc_V, rel



50 2 XOR Rwn, Rwm

51 2 XORB Rbn, Rbm

52 4 XOR reg, mem

53 4 XORB reg, mem

54 4 XOR mem, reg

55 4 XORB mem, reg




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56 4 XOR reg, #data16

57 4 XORB reg, #data16

58 2 XOR Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

59 2 XORB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

5A 4 BOR bitaddrZ.z, bitaddrQ.q

5B 2 DIVU Rwn

5C 2 SHL Rwn, #data4

5D 2 JMPR cc_NV, rel



60 2 AND Rwn, Rwm

61 2 ANDB Rbn, Rbm

62 4 AND reg, mem

63 4 ANDB reg, mem

64 4 AND mem, reg

65 4 ANDB mem, reg

66 4 AND reg, #data16

67 4 ANDB reg, #data16

68 2 AND Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

69 2 ANDB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

6A 4 BAND bitaddrZ.z, bitaddrQ.q

6B 2 DIVL Rwn

6C 2 SHR Rwn, Rwm

6D 2 JMPR cc_N, rel



70 2 OR Rwn, Rwm

71 2 ORB Rbn, Rbm

72 4 OR reg, mem

73 4 ORB reg, mem

74 4 OR mem, reg

75 4 ORB mem, reg

76 4 OR reg, #data16

77 4 ORB reg, #data16




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78 2 OR Rwn, [Rwi+] or Rwn, [Rwi] or Rwn, #data3

79 2 ORB Rbn, [Rwi+] or Rbn, [Rwi] or Rbn, #data3

7A 4 BXOR bitaddrZ.z, bitaddrQ.q

7B 2 DIVLU Rwn

7C 2 SHR Rwn, #data4

7D 2 JMPR cc_NN, rel



80 2 CMPI1 Rwn, #data4

81 2 NEG Rwn

82 4 CMPI1 Rwn, mem

83 4 CoXXX1 Rwn, [Rwm⊗]

84 4 MOV [Rwn], mem

85 - - -


87 4 IDLE

88 2 MOV [-Rwm], Rwn

89 2 MOVB [-Rwm], Rbn

8A 4 JB bitaddrQ.q, rel

8B - - -

8C - - -

8D 2 JMPR cc_C, rel or cc_ULT, rel




91 2 CPL Rwn

92 4 CMPI2 Rwn, mem

93 4 CoXXX1 [IDXi⊗], [Rwn⊗]

94 4 MOV mem, [Rwn]

95 - - -


97 4 PWRDN

98 2 MOV Rwn, [Rwm+]

99 2 MOVB Rbn, [Rwm+]




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9A 4 JNB bitaddrQ.q, rel

9B 2 TRAP #trap7

9C 2 JMPI cc, [Rwn]

9D 2 JMPR cc_NC, rel or cc_UGE, rel



A0 2 CMPD1 Rwn, #data4

A1 2 NEGB Rbn

A2 4 CMPD1 Rwn, mem

A3 4 CoXXX1 Rwn, Rwm

A4 4 MOVB [Rwn], mem

A5 4 DISWDT

A6 4 CMPD1 Rwn, #data16

A7 4 SRVWDT

A8 2 MOV Rwn, [Rwm]

A9 2 MOVB Rbn, [Rwm]

AA 4 JBC bitaddrQ.q, rel

AB 2 CALLI cc, [Rwn]

AC 2 ASHR Rwn, Rwm

AD 2 JMPR cc_SGT, rel

AE 2 BCLR bitaddrQ.10

AF 2 BSET bitaddrQ.10

B0 2 CMPD2 Rwn, #data4

B1 2 CPLB Rbn

B2 4 CMPD2 Rwn, mem

B3 4 CoSTORE1 [Rwn⊗], CoReg

B4 4 MOVB mem, [Rwn]

B5 4 EINIT

B6 4 CMPD2 Rwn, #data16

B7 4 SRST

B8 2 MOV [Rwm], Rwn

B9 2 MOVB [Rwm], Rbn

BA 4 JNBS bitaddrQ.q, rel

BB 2 CALLR rel




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BC 2 ASHR Rwn, #data4

BD 2 JMPR cc_SLE, rel

BE 2 BCLR bitaddrQ.11

BF 2 BSET bitaddrQ.11

C0 2 MOVBZ Rbn, Rbm

C1 - - -

C2 4 MOVBZ reg, mem

C3 4 CoSTORE1 Rwn, CoReg

C4 4 MOV [Rwm+#data16], Rwn

C5 4 MOVBZ mem, reg

C6 4 SCXT reg, #data16

C7 - - -

C8 2 MOV [Rwn], [Rwm]

C9 2 MOVB [Rwn], [Rwm]

CA 4 CALLA cc, caddr

CB 2 RET

CC 2 NOP

CD 2 JMPR cc_SLT, rel

CE 2 BCLR bitaddrQ.12

CF 2 BSET bitaddrQ.12

D0 2 MOVBS Rbn, Rbm

D1 2 ATOMIC/EXTR #data2

D2 4 MOVBS reg, mem

D3 4 CoMOV1 [IDXi⊗], [Rwn⊗]

D4 4 MOV Rwn, [Rwm+#data16]

D5 4 MOVBS mem, reg

D6 4 SCXT reg, mem

D7 4 EXTP(R)/EXTS(R) #pag, #data2

D8 2 MOV [Rwn+], [Rwm]

D9 2 MOVB [Rwn+], [Rwm]

DA 4 CALLS seg, caddr

DB 2 RETS

DC 2 EXTP(R)/EXTS(R) Rwm, #data2

DD 2 JMPR cc_SGE, rel




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Note 1. This instruction only applies to products including the MAC.

DE 2 BCLR bitaddrQ.13

DF 2 BSET bitaddrQ.13

E0 2 MOV Rwn, #data4

E1 2 MOVB Rbn, #data4

E2 4 PCALL reg, caddr

E3 - - -

E4 4 MOVB [Rwm+#data16], Rbn

E5 - - -

E6 4 MOV reg, #data16

E7 4 MOVB reg, #data16

E8 2 MOV [Rwn], [Rwm+]

E9 2 MOVB [Rwn], [Rwm+]

EA 4 JMPA cc, caddr

EB 2 RETP reg

EC 2 PUSH reg

ED 2 JMPR cc_UGT, rel

EE 2 BCLR bitaddrQ.14

EF 2 BSET bitaddrQ.14

F0 2 MOV Rwn, Rwm

F1 2 MOVB Rbn, Rbm

F2 4 MOV reg, mem

F3 4 MOVB reg, mem

F4 4 MOVB Rbn, [Rwm+#data16]

F5 - - -

F6 4 MOV mem, reg

F7 4 MOVB mem, reg

F8 - - -

F9 - - -

FA 4 JMPS seg, caddr

FB 2 RETI

FC 2 POP reg

FD 2 JMPR cc_ULE, rel

FE 2 BCLR bitaddrQ.15

FF 2 BSET bitaddrQ.15




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2.6 - Instruction conventionsThis section details the conventions used in theindividual instruction descriptions. Each individualinstruction description is described in a standardformat in separate sections under the followingheadings:

2.6.1 - Instruction nameSpecifies the mnemonic opcode of the instruction.

2.6.2 - SyntaxSpecifies the mnemonic opcode and the requiredformal operands of the instruction. Instructionscan have either none, one, two or three operandswhich are separated from each other by commas:MNEMONIC {op1 {,op2 {,op3 } } }.The operand syntax depends on the addressingmode. All of the available addressing modes are

summarized at the end of each single instructiondescription.

2.6.3 - OperationThe following symbols are used to represent datamovement, arithmetic or logical operators (seeTable 22).Missing or existing parentheses signifies that theoperand specifies an immediate constant value,an address, or a pointer to an address as follows:opX Specifies the immediate constant value

of opX.(opX) Specifies the contents of opX.(opXn) Specifies the contents of bit n of opX.((opX)) Specifies the contents of the contents of

opX (i.e. opX is used as pointer to theactual operand).

The following abbreviations are used to describe operands:

Table 22 : Instruction operation symbols

Diadic operations

operator (opY)

(opx)


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2.6.4 - Data types

Specifies the particular data type according to theinstruction. Basically, the following data types areused: BIT, BYTE, WORD, DOUBLEWORD

Except for those instructions which extend bytedata to word data, all instructions have only oneparticular data type.

Note that the data types mentioned here do nottake into account accesses to indirect addresspointers or to the system stack which are alwaysperformed with word data. Moreover, no data typeis specified for System Control Instructions and

for those of the branch instructions which do notaccess any explicitly addressed data.

2.6.5 - Description

Describes the operation of the instruction.

2.6.6 - Condition code

The following table summarizes the 16 possiblecondition codes that can be used within Call andBranch instructions and shows the mnemonicabbreviations, the test executed for a specific con-dition and the 4-bit condition code number.

Table 24 : Condition codes

Condition Code Mnemonic cc Test Description

Condition Code Number c

cc_UC 1 = 1 Unconditional 0h

cc_Z Z = 1 Zero 2h

cc_NZ Z = 0 Not zero 3h

cc_V V = 1 Overflow 4h

cc_NV V = 0 No overflow 5h

cc_N N = 1 Negative 6h

cc_NN N = 0 Not negative 7h

cc_C C = 1 Carry 8h

cc_NC C = 0 No carry 9h

cc_EQ Z = 1 Equal 2h

cc_NE Z = 0 Not equal 3h

cc_ULT C = 1 Unsigned less than 8h

cc_ULE (Z v C) = 1 Unsigned less than or equal Fh

cc_UGE C = 0 Unsigned greater than or equal

9h

cc_UGT (Z v C) = 0 Unsigned greater than Eh

cc_SLT (N ⊕ V) = 1 Signed less than Ch

cc_SLE (Z v (N ⊕ V)) = 1 Signed less than or equal Bh

cc_SGE (N ⊕ V) = 0 Signed greater than or equal Dh

cc_SGT (Z v (N ⊕ V)) = 0 Signed greater than Ah

cc_NET (Z v E) = 0 Not equal AND not end of table

1h


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2.6.7 - Flags This section shows the state of the N, C, V, Z andE flags in the PSW register. The resulting state ofthe flags is represented by the following symbols(see Table 25). If the PSW register is specified as the destinationoperand of an instruction, the flags can not beinterpreted as described. This is because the PSW register is modifiedaccording to the data format of the instruction:– For word operations, the PSW register is over-

written with the word result.

– For byte operations, the non-addressed byte iscleared and the addressed byte is overwritten.

– For bit or bit-field operations on the PSW regis-ter, only the specified bits are modified.

If the flags are not selected as destination bits,they stay unchanged i.e. they maintain the stateexisting after the previous instruction.

In all cases, if the PSW is the destination operandof an instruction, the PSW flags do NOT representthe flags of this instruction, in the normal way.

Table 25 : List of flags

Symbol Description

* The flag is set according to the following standard rules

N = 1 : Most significant bit of the result is set

N = 0 : Most significant bit of the result is not set

C = 1 : Carry occurred during operation

C = 0 : No Carry occurred during operation

V = 1 : Arithmetic Overflow occurred during operation

V = 0 : No Arithmetic Overflow occurred during operation

Z = 1 : Result equals zero

Z = 0 : Result does not equal zero

E = 1 : Source operand represents the lowest negative number, either 8000h for word data or 80h for byte data.

E = 0 : Source operand does not represent the lowest negative number for the specified data type

“S” The flag is set according to non-standard rules. Individual instruction pages or the ALU status flags description.

“-” The flag is not affected by the operation

“0” The flag is cleared by the operation.

“NOR” The flag contains the logical NORing of the two specified bit operands.

“AND” The flag contains the logical ANDing of the two specified bit operands.

“'OR” The flag contains the logical ORing of the two specified bit operands.

“XOR” The flag contains the logical XORing of the two specified bit operands.

“B” The flag contains the original value of the specified bit operand.

“B” The flag contains the complemented value of the specified bit operand


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2.6.8 - Addressing modesSpecifies available combinations of addressingmodes. The selected addressing mode combina-tion is generally specified by the opcode of thecorresponding instruction. However, there are some arithmetic and logicalinstructions where the addressing mode combina-tion is not specified by the (identical) opcodes butby particular bits within the operand field.In the individual instruction description, theaddressing mode is described in terms of mne-monic, format and number of bytes.

– Mnemonic gives an example of which operandsthe instruction will accept.

– Format specifies the format of the instruction asused in the assembler listing. Figure 3 showsthe reference between the instruction formatrepresentation of the assembler and the corre-sponding internal organization of the instructionformat (N = nibble = 4 bits). The following sym-bols are used to describe the instruction for-mats:

Table 26 : Instruction format symbols

00h through FFh Instruction Opcodes

0, 1 Constant Values

:.... Each of the 4 characters immediately following a colon represents a single bit

:..ii 2-bit short GPR address (Rwi)

ss 8-bit code segment number (seg).

:..## 2-bit immediate constant (#data2)

:.### 3-bit immediate constant (#data3)

c 4-bit condition code specification (cc)

n 4-bit short GPR address (Rwn or Rbn)

m 4-bit short GPR address (Rwm or Rbm)

q 4-bit position of the source bit within the word specified by QQ

z 4-bit position of the destination bit within the word specified by ZZ

# 4-bit immediate constant (#data4)

QQ 8-bit word address of the source bit (bitoff)

rr 8-bit relative target address word offset (rel)

RR 8-bit word address reg

ZZ 8-bit word address of the destination bit (bitoff)

## 8-bit immediate constant (#data8)

@@ 8-bit immediate constant (#mas

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FAMILY PROGRAMMING MANUALa 4-bit word GPR address relative to the base address (CP), while ’Rb’ specifies a 4 bit byte GPR address relative to the base address (CP). reg Specifies