Files_ECE_Manual_III_EC2208 - Electronics Circuit 1 Laboratory

8/12/2019 Files_ECE_Manual_III_EC2208 - Electronics Circuit 1 Laboratory

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EC2208 Electronic circuits I- Sudharsan Engineering college

1

SUDHARSAN ENGINEERING COLLEGE

ELECTRONIC CIRCUITS I

LAB MANUAL

SUB CODE: EC2208

PREPARED BY

D.RAMESH, Asst. HOD/ECE

M.KARTHIGA, Asst. Prof/ECE


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Circuit Diagram

CE Amplifier with Fixed Bias

Pin Diagram

Bottom view of BC107

B

E

C


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Ex. no: 1. COMMON EMITTER AMPLIFIER WITH FIXED BIAS

Date:

Aim

To design and construct BJT Common Emitter Amplifier using fixed bias .To measure the gain and to plot the frequency response and to determine the GainBandwidth product (GBW).

Apparatus Required

S.No Equipments / Components Range / Details Qty

1. Power Supply (030) V 1

2. Resistor 5.1K, 3M 1

3. Capacitor 1 F 1

4. Transistor BC 107 1

5. AFO (01) MHz 1

6. CRO (020) MHz 1

Fixed Bias with Emitter Resistor

The fixed bias circuit is modified by attaching an external resistor to the emitter. This resistor

introduces negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the voltage

across the base resistor is

VRb= VCC- IeRe- Vbe


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Tabulation

VS=

Frequency (Hz) Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB

Model Graph


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From Ohm's law, the base current is

Ib= VRb/ Rb.

The way feedback controls the bias point is as follows. If Vbe is held constant and temperature

increases, emitter current increases. However, a larger Ie increases the emitter voltage Ve= IeRe,

which in turn reduces the voltage VRbacross the base resistor. A lower base-resistor voltage dropreduces the base current, which results in less collector current because Ic= IB. Collector current

and emitter current are related by Ic= Iewith 1, so increase in emitter current with temperatureis opposed, and operating point is kept stable.

Similarly, if the transistor is replaced by another, there may be a change in I C (corresponding tochange in -value, for example). By similar process as above, the change is negated and operatingpoint kept stable.

For the given circuit,

IB= (VCC- Vbe)/(RB+ (+1)RE).

Merits:

The circuit has the tendency to stabilize operating point against changes in temperature and -value.

Demerits:

In this circuit, to keep ICindependent of the following condition must be met:

which is approximately the case if ( + 1 )RE>> RB.

As -value is fixed for a given transistor, this relation can be satisfied either by keeping REverylarge, or making RBvery low.

If REis of large value, high VCCis necessary. This increases cost as well as precautionsnecessary while handling.

If RBis low, a separate low voltage supply should be used in the base circuit. Using twosupplies of different voltages is impractical.

In addition to the above, RE causes ac feedback which reduces the voltage gain of theamplifier.

Usage:The feedback also increases the input impedance of the amplifier when seen from thebase,

which can be advantageous. Due to the above disadvantages, this type of biasing circuit is used only

with careful consideration of the trade-offs involved.


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Design

Choose = 250, VCC= 12V, IC= 1 mA

By applying KVL to output side,

VCCICRCVCE= 0

VCC= ICRCVCE

Assume equal drops across RCand VCEVRC= VCE= 6V, ICRC= 6V

RC= 6V/10-3

= 6K

Choosing a standard value for RCas 5.1

By applying KVL to the input side,

VCCIBRBVBE= 0

IB= IC/ = 1mA/250 = 4A

RB = (VCCVBE) / IB

=(12 0.7)/4x10-6=2.825M 3M

Design of input capacitor

F = 1/2hieC

Take F = 100Hz and hie= 1.6 K

C1 = 1/ (2X 1.6 K X 100) = 0.9F 1F

Calculation

Bandwidth = fH- fL


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Procedure

1) Connect the circuit as per the circuit diagram2) Set Vin = 50mV in the signal generator. Keeping input voltage constant, vary thefrequency from 1Hz to 1MHzin regular steps.

3) Note down the corresponding output voltage.4) Plot the graph: Gain in dB Vs Frequency in Hz.5) Calculate the Bandwidth from the Frequency response graph

To plot the Frequency Response

1) The frequency response curve is plotted on a semi-log scale.2) The mid frequency voltage gain is divided by 2 and these points are marked in thefrequency response curve.

3)

The high frequency point is called the upper 3dB point.4) The lower frequency point is called the lower 3dB point.5) The difference between the upper 3dB point and the lower 3dB point in thefrequency scale gives the bandwidth of the amplifier.

6) From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH- fL

Result

Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and the

frequency response curve is plotted.

The bandwidth is found to be __________________


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Circuit Diagram

CE Amplifier with Self Bias

Design

Drop across RE(VRE) is assumed to be 1V.

Drop across VCEwith the supply of 12V is given by 12V 1V = 11V

Assume equal drops across ICRCand VCE

So ICRC= VRC= 11/2 = 5.5V

Assume IC= 1 mA,

Then RC= VRC/ IC= 5.5V / 1mA = 5.5 K

Instead of using 5.5 K , we can use a standard value of 4.7 K

VRE= 1V, IEIC= 1mA

RE= VRE/IE= 1V/1mA = 1K


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Ex. no: 2. COMMON EMITTER AMPLIFIER WITH SELF BIASDate:

Aim

To design and construct BJT Common Emitter Amplifier using voltage bias (self bias) with

and without bypassed emitter resistor.To measure the gain and to plot the frequency response and to determine the GainBandwidth product (GBW).

Apparatus Required

S.No Equipments / Components Range / Details Qty

1. Power Supply (030) V 1

2. Resistor 1K, 61K, 10K, 4.7K 1

3. Capacitor 1F 1

4. Transistor BC 107 1

5. AFO (01) MHz 1

6. CRO (020) MHz 1

Theory

Voltage divider bias (Self bias)

A combination of fixed and self-bias can be used to improve stability and at the same time

overcome some of the disadvantages of the other two biasing methods. One of the most widely

used combination-bias systems is the voltage-divider type. The voltage divider is formed using

external resistors R1and R2. The voltage across R2forward biases the emitter junction. By proper

selection of resistors R1and R2, the operating point of the transistor can be made independent of

. In this circuit, the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. However, even with a fixed

base voltage, collector current varies with temperature (for example) so an emitter resistor is

added to stabilize the Q-point. However, to provide long-term or dc thermal stability, and at the

same time, allow minimal ac signal degeneration, the bypass capacitor (Cbp) is placed across R3.

If Cbp is large enough, rapid signal variations will not change its charge materially and no

degeneration of the signal will occur.

Merits

Unlike above circuits, only one dc supply is necessary. Operating point is almost independent of variation. Operating point stabilized against shift in temperature.


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Tabulation

Model Graph

Frequency (Hz) Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB


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Procedure

To plot the Frequency Response

The frequency response curve is plotted on a semi-log scale.

1) The mid frequency voltage gain is divided by 2 and these points are marked in thefrequency response curve.

2) The high frequency point is called the upper 3dB point.3) The lower frequency point is called the lower 3dB point.4) The difference between the upper 3dB point and the lower 3dB point in the frequency scale

gives the bandwidth of the amplifier.

5) From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH- fL


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Design of R1and R2

Drop across VBE = 0.7V

Drop across R2(VR2) = VBE+ VRE= 1.7V

Assume R2= 10 K

VR2= VCC.R2/ (R1+R2)

R1= (12 X 10) / (1.7 10) = 60.5 K

R1is assumed to be 61 K

Design of input capacitor

F = 1/2hieC

Take F = 100Hz and hie= 1.6 K

C1 = 1/ (2X 1.6 K X 100) = 0.9F 1F

Calculation

Bandwidth = fH- fL


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Result

Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency response

curve is plotted.

Bandwidth =


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Circuit diagram:

Design:

Since voltage amplification is done in the transistor amplifier circuit, we assume equal drops

across VCEand Emitter Resistance RE. VRE= 6V. The quiescent current of 1mA is assumed.

We assume a standard supply of Vcc= 12V.

Drop across REis assumed to be VRE =6V

Drop across VCEis VCCVRE =6VWe know that ICQ=IE,

Now RE= VRE = 6V = 6K

IE 1X 10-

Design of R1& R2Drop across REis 6VDrop across VBEis 0.6VDrop across the resistance R2is VR2= VBE+ VRE=6.6VAssume R2=10K

VCCR2= 6.6 V

R1+ R2

12 X 10 X 103

= 6.6V

R1+ 10 X 103

120 X 103

= R1+ 10 X 103

6.6

18.18 X 103= R1+ 10 X 10

3R1=

8 K(3.3 K + 4.7 K)


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Ex. no: 3. COMMON COLLECTOR TRANSISTOR AMPLIFIER

Date:

Aim:

1.To design and construct BJT Common Collector Amplifier using voltage divider bias (self-bias).

2. To measure the gain and to plot the frequency response & to determination of GainBandwidth Product

Apparatus required:

1.Transistors - BC107

2.Regulated Power Supply -3.Audio Frequency Oscillator

4.Resistors - 6K,8K,10K5.Capacitors - 47F

6.CRO


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Tabular column

Vs =

Model graph (frequency response)

Frequency VO Gain = VO/ VS Gain = 20 log (VO/VS)(Hz) (Volts) (dB)


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Circuit diagram:

Design:

Such a DC the ICBOof the 1st

stage is multiplied by (+1) times and this will be input Base currentfor the 2

ndstage. Hence the 2

ndstage IEcurrent will be IE= (+1)

2ICO

For silicon transistor ICBOis the order of 10nA at room temperature =100. Now,

IE= (101)2X 10 nA IE

105nA0.1mA

This current will get double with every 100rise in temperature. So to reduce the effect of ICBOthe

1st

stage ICBO

flowing through the emitter of the 1st

stage is not allowing to enter the 2nd

stage by

paralleling a resistor between B & E of the 2ndstage T2.So the ICBO(+1) will flow through thisresistance and a part of this current might flow through hie+ dcRE. This shunting resistance willbe the range of 1 to 4.7 K.

Biasing Design:

Assume R2= 10Kand Ic= 1mA.

Since voltage amplification is done in the Darlington transistor amplifier circuit, we

assume equal drops across VCEand load resistance RC. The ICQ= 1mA is assumed. We assumestandard supply of 12V.

Drop across Reis assumed to be 1V. The drop across VCEwith a supply of 1.2 V is given by

12 1 = 1V.It is equal to VRC& VCE= 5.5V RC=

VRC= 5.5 K(4.7 K)ICDesign of

R1& R2:Drop across REis 1V.Drop across VBE1&VBE2 is 0.6V.Drop across the resistance R2is VRE+ VBE1+ VBE2


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Ex. no: 4. DARLINGTON COMMON EMITTER AMPLIFIER

Date:

Aim:

1. To design a Darlington amplifier using BJT and to measure the gain and input resistance.2. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW).

Apparatus required:

1.Transistors - BC 107

2.Resistors - 1K,4.7K,47K,10K (all are W)3.Capacitors - 47F, 100F4.CRO5.AFO6.RPS7.Connecting wires & Breadboard


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Tabular column:

Vs =

Frequency VO Gain = VO/ VS Gain = 20 log (VO/VS)

(Hz) (Volts) (dB)

Model graph (frequency response):


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Design continuation:

= 1 + 0.6 + 0.6 VR2= 2.2VR2is assumed to be 10 K

VCCR2

= 2.2V R1+

R2

1.2 X 10 X 103= 2.2

R1+ 10 X 103

120 X 103= R1+ 10 X 10

32.2

54.5 X 103= R1+ 10 X 10

3R1=

54.5 X 10310 X 10

3

R1= 44.5 X 103

R1is rounded to be 47 K


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Procedure:

1. Connect the circuit as per the circuit diagram.2. Set VS= 5 mV using AFO.3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular

steps and note down the corresponding output voltage.

4. Plot the graph gain Vs frequency.5. Calculate bandwidth from the graph.

Result:

1. The frequency response curve is plotted on a log scale.2. From the graph the bandwidth isobtained Bandwidth = fH- fL=

Specifications:

1. Transistor - BC107, 50V1A, 3W, 300 MHz

2. Regulated Power Supply (0- 30), 1A


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Circuit diagram:

Pin Details


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Ex. no: 5. COMMON DRAIN AMPLIFIERDate:

Aim:

To design a common drain amplifier and to measure the gain, input resistance and outputresistance with and without Bootstrapping.

Apparatus required:

1. Transistor - BC-107

2. Regulated Power supply - 13. Audio Frequency Oscillator - 14. Resistors - 4.7K, 2.7K, 1M5. Capacitor - 1F6. CRO7. Bread board and connecting wires

Theory:

Here input is applied between gate and source & output between source and Drain. Here Vs = VG+

VGS. When a signal is applied to JFET gate via Cin,VGvaries with the signal. As VGSis fairlyconstant and Vs varies with Vi. Here output voltage follows the change in the signal voltage appliedto the gate, the circuit is also called as Source follower


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Bias design:

VDD= 12 V, IDSS = 9.5mA, ID = 1mA, VP= -4V, Ci= 1F

VGS= IDRS ,ID = IDSS{1-(VGS/VP)}2

RS= 2.7K , Voltage drop across R S= 2.7V

RD DS DD

-RS=12-2.7=9.3V.

Assume equal drops across VRD& VDS

VRD= VDS= 4.65V

RD= VRD/ID= 4.65K

Instead of 4.65K, we can select standard value = 4.7K

FET input is always reverse bias. So choose the value of resistance RGvery large with inThe

range of 1Mto 10M


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Procedure:

1. Connect the circuit as shown in the circuit diagram2. Set Vs= 50 mv in AFO3. Keeping the input voltage constant, vary the frequency from 0 Hz to1MHz in regular

steps and note down the corresponding output voltage.

4. Plot the graph: gain Vs Frequency5. Calculate the bandwidth from the Graph


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Tabulation

VS=

Frequency (Hz) VO(V) Gain = VO/ VS Gain = 20 log(VO/VS)_ dB

Model Graph


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Result:

Thus a common drain amplifier is designed and the gain, input resistance and output resistance

are calculated using the measured parameters.


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Circuit DiagramDifferential Amplifier

Common mode Configuration

Differential mode Configuration


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Ex. no: 6. DIFFERENTIAL AMPLIFIER

Date:

Aim

To construct the Differential Amplifier in

a) Common mode andb) Differential mode, and to find the common mode rejection ratio (CMRR).

Apparatus required

1. Power Supply2. CRO3. Function Generator4.Transistors - BC107 -1 no

5.Resistors - 1K - 2 nos.470 -1 no.

Formula

C.M.R.R = Ad/Ac

C.M.R.R in dB = 20 log Ad/Ac

Ad= Differential mode gainAc = Common mode gain

Theory

The Differential amplifier amplifies the difference between two input voltage signals. Hence it is

called differential amplifier.V1 and V2 are input voltages, Vo is proportional to difference between

two input signals.

If we apply two input voltages equal in all respects then in ideal case output should be zero. But

output voltage depends on the average common level of the inputs. Such an average level of two

input signals is called common mode signal

Higher the value of C.M.R.R, better the performance of the differential amplifier. To improve

C.M.R.R we have to increase differential mode gain and decrease common mode gain


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Model Calculation

For common mode signal

Gain Ac = Vo / Vi

Ac =

For differential mode signal

Gain Ad = Vo / Vi

Ad =

CMRR = 20 log (Ad / Ac)

=


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Procedure

1. Connections are given as per the circuit diagram2. Set Vi=5mV and note down Vo in both differential mode & common mode3. Calculate the gain for both the modes4.

Calculate C.M.R.R

Formulae

For common mode signal: Gain Ac = Vo / Vi

For differential mode signal: Gain Ad = Vo / Vi

Common Mode Rejection Ratio: CMRR = 20 log (Ad / Ac)

Result

Thus a differential amplifier is constructed in both common mode and differential mode and thecorresponding gains are obtained and the CMRR is calculated.

CMRR =


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Circuit diagram:

Bias design:

Since voltage amplification is done in the transistor amplifier circuit, We as equal drops

across VCE& load resistance RE. The quiescent current of 1mA is assumed, we assume a standardsupply of 12V.

Drop across REis assumed to be 1V,the drop across VCEwith a supply of 12V is given by 12V-

1V=11V

It is equal to 11/2=5.5V

Now the voltage across the resistance REis 5.5V

VCE= 5.5V

VC= 5.5V IC=1mA

RC= 5.5V/1mA = 5.5K

Instead of using 5.5K, We can use a standard value of 4.7K. It

is assumed that RBB/ (dc+1) = RE/ 10

Hence RBB/ (dc+1) is neglected when compared RE.

Hence VBB= IERE+VBE

Hence VBEis neglected when compared to IERE

Hence IE= VBB/ RE.


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Ex. no: 7. CLASS - A AMPLIFIER

Date:

Aim

To design and construct a ClassA power amplifier.To observe the output waveform and to measure the maximum power output and to determine

the efficiency

Apparatus required:

1. Transistor - BC107 - 1

2. Resistors - 1K, 4.7K, 61K, 10K (all are W)3. Capacitors - 1f,100f(all are electrolytic)

4. CRO - (0-20MHz)

5. AFO - (0-1MHz)6. Regulated Power Supply7. Breadboard & Connecting Wires

Theory:

The Power amplifier is said to be class-A amplifier if the Q-point & the input signal are selected

such that the output signal is obtained for a full input cycle. For this, position of the Q-point is

approximately at the midpoint of the load line.

For all the values of input signal, the transistor remains in the active region &never enters into cut-

off or saturation region. When an a.c input signal is applied, the collector voltage varies

sinusoidally hence the collector current also varies sinusoidally. The collector current flows for

360(full cycle)of the input signal. In other words, the angle of the collector current flow is 360 i.e.

one full cycle.

DESIGN OF R1& R2:

Voltage drop across RE= VRE= 1V

Drop across VBE= 0.7V

Drop across the resistance R2= VBE+VRE= VR2

VR2=1.7V ; R2is assumed to be 10K

VCCR2/ (R1+ R2) = VR2

10*12K/(R1+10K)=1.7V

R1=60.5V61K


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Tabular column:

VI=

Frequency V0 Gain = V0/ Vi Gain (dB) = 20 log V0/ Vi dB(KHz) (mV)

Model graph:


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Procedure:

1. Connect the circuit as per the circuit diagram.2. Set VS=10mV using AFO.

3.Keeping the input voltage constant, vary the frequency from few Hz to 1MHz in regular steps &note down the correspondingly output voltage.

4. Plot the graph: gain Vs frequency.5. Calculate bandwidth from the graph.

Result:

The class-A amplifier is designed, constructed and the output waveform is observed. The maximumpower output and the efficiency are determined.


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Circuit diagram

Pin Diagram

Bottom view of BC 107 / BC 178

B

E

C

3-d view


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Ex. no: 8. CLASSB POWER AMPLIFIER

Date:

Aim:

To design and construct a Class B (complementary symmetry) power amplifier.To observe

the output waveform with crossover Distortion and to measure the maximum power output andto determine the efficiency.

Apparatus required:

1.Power Supply - (030) V2. CRO - (020) MHz3.Function Generator - (01) MHz4.Resistor - 47 K - 1No

1 K - 1No5.Transistors - BC 107 - 1No

BC 178 - 1No

Theory:

The figure illustrates a ClassB Power Amplifier, which employs one PNP, and one NPN transistorand require no transformed. This type of amplifier uses complementary symmetry. i.e., the two

transistor have identical characteristics but one is PNP and the other NPN.

Its operation can be explained by referring to the figure. When the signal voltage is positive, T1(the

NPN transistor) conducts, while T2 (the PNP transistor) is cut off. When the signal voltage is

negative, T2conducts while T1is cut off. The load current is

iL= ic1ic2

some advantages of the circuit are that the transformer less operation saves on weight and cost and

balanced pushpull input signals are not required. The disadvantage is obtaining pause of transistormatched closely enough to achieve low distortion.

Procedure:

1. Connect the circuit as per the diagram.2. Set VS= 50mV(say) using the signal generator.3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz. Inregular steps. Note down the corresponding output voltage.4. Plot the graph i.e., gain (dB) Vs frequency (on a semilog graph)


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Model graph:

Tabular column:

VI= mV I = mA

Frequency V0 Gain = V0/ Vi Gain (dB) = 20 log V0/ Vi dB(KHz) (mV)


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Formulae

Result

Thus a ClassB (complementary symmetry) power amplifier is constructed and the

output waveforms are observed and the maximum power output and efficiency is calculated.


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Circuit diagram:


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Ex. no: 9. HALF WAVE RECTIFIER

Date:

Aim

1. To design a Half wave rectifier with simple capacitor filter.2. To measure the DC voltage under load and ripple factor and to compare with calculatedvalues.

Apparatus Required

1. CRO - (0-20 MHz)

2.Multimeter

3.Diode - 1N4007

4.Transformer - 230V / 120- 12v, 200 mA

5.Resistor - 500-1/4W(carbon film resistors)

6.Capacitor - 100F /25V

7.Connecting Wires and Bread Board

Procedure

Half wave rectifier

(i) Without Capacitor1.Test your transformer: Give 230v, 50Hz source to the primary coil of the transformer and

observe the AC waveform of rated value without any distortion at the secondary of the

transformer.

2.Connect the half wave rectifier as shown in figure.3.Measure the Vdc&Vacusing DC and AC Voltmeters.

4. Calculate the Ripple factor r = Vac/Vdc

Note:The rectifier output consists of both AC & DC components. To block DC component100f

(Electrolytic) Condenser is used.

5. Compare the theoretical ripple factor with the practical ripple factor.


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Model Graph

VI(v)

T(m sec)

Input Wave Form

Vo(V) With filter

Without filter

T(m sec)

Half Wave Rectifier Output


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(ii) With Capacitor1. Connect the half wave rectifier with filter circuit as shown in fig.2. Assume r= 10% of ripple peak-to-peak voltage for R= 500. Calculate C using theformula r = 1/23fRC3. Connect CRO across load.4. Keep the CRO switch in ground mode and observe the horizontal line and adjust it tothe X-axis.

5. Switch the CRO into DC mode and observe the waveform.

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the

corresponding dc output voltages and the ripple factors are measured and verified with the

theoretical values.

Ripple Factor

Theoretical Practical

Specifications:

1. Diode 1N4007 (700V- PIV, Idc= 1A)

2. RPS (0-30),1A


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Circuit diagram:


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Ex. no: 10. FULL WAVE RECTIFIER

Date:

Aim

1. To design a Full wave rectifier with and without simple capacitor filter.2. To measure the DC voltage under load and ripple factor and to compare withcalculated

Apparatus Required

1. CRO - (0-20 MHz)

2.Multimeter -

3.Diode - 1N4007

4.Transformer - 230V / 120- 12v, 200 mA

5.Resistor - 500-1/4W(carbon film resistors)

6.Capacitor - 100F /25V

7.Connecting Wires and Bread Board

Procedure

Full wave rectifier

(i) Without Capacitor1. Test your transformer: Give 230v, 50Hz source to the primary coil of the transformerand observe the AC waveform of rated value without any distortion at the secondary of the

transformer.

2. Connect the full wave rectifier as shown in figure.3. Measure the Vdc&Vacusing DC and AC Voltmeters.4. Calculate the Ripple factorr = Vac/Vdc

Note:The rectifier output consists of both AC&DC components. To block DC component

100f (Electrolytic) Condenser is used.

5. Compare the theoretical ripple factor with the practical ripple factor.


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Model graph:

VI(v)

t (m sec)

Input Wave Form

VO(V)With filter

Without filter

t (m sec)

Full Wave Rectifier Output


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(ii) With capacitor:1. To plot ripple peak-to-peak voltage Vs. Idc to choose C a ripple factor of 0.15 isassumed.

2. To get a variable load resistance a number of 500, 5W of resistance are to beconnected in parallel. Hence Idc= Vdc/( N X 500). Where N is number of 500resistances

connected in parallel.

3. Plot the graph IdcVs ripple peak to peak.4. The above steps are repeated for the various values of capacitance.

Result

Thus the Full wave rectifier is designed with and without capacitor filter and the corresponding dc

output voltages and the ripple factors are measured and verified with the theoretical values.

Ripple Factor

Theoretical Practical

Specifications:

1. Diode 1N4007 (700V- PIV, Idc= 1A)

2 RPS (0-30) 1A

Documents

Files_ECE_Manual_III_EC2208 - Electronics Circuit 1 Laboratory