Flash MCU with EEPROM HT66F20-1/HT66F30-1 HT68F20 … · integrated SPI or I2C interface functions, two popular interfaces which provide designers with a ... , Low Voltage Reset and

Flash MCU with EEPROM

HT66F20-1/HT66F30-1HT68F20-1/HT68F30-1

Revision: V1.40 Date: �ove��e� �� 01��ove��e� �� 01�

Rev. 1.40 � �ove��e� �� 01� Rev. 1.40 � �ove��e� �� 01�

HT66F20-1/HT66F30-1/HT68F20-1/HT68F30-1Flash MCU with EEPROM


Table of Contents

Features ............................................................................................................ 7CPU Featu�es ......................................................................................................................... 7Pe�iphe�al Featu�es ................................................................................................................. 7

General Description ......................................................................................... 8Selection Table ................................................................................................. 8Block Diagram .................................................................................................. 9Pin Assignment .............................................................................................. 10Pin Description .............................................................................................. 12Absolute Maximum Ratings .......................................................................... 16D.C. Characteristics ....................................................................................... 16

HT��F�0-1/HT��F�0-1 ......................................................................................................... 1�HT�8F�0-1/HT�8F�0-1 ......................................................................................................... 18

A.C. Characteristics ....................................................................................... 19HT��F�0-1/HT��F�0-1 ......................................................................................................... 19HT�8F�0-1/HT�8F�0-1 ......................................................................................................... �1

A/D Converter Characteristics ...................................................................... 22HT��F�0-1/HT��F�0-1 ......................................................................................................... ��

Comparator Electrical Characteristics ........................................................ 22Power on Reset Electrical Characteristics .................................................. 23System Architecture ...................................................................................... 23

Clocking and Pipelining ......................................................................................................... ��P�og�a� Counte� ................................................................................................................... �4Stack ..................................................................................................................................... �5A�ith�etic and Logic Unit – ALU ........................................................................................... �5

Flash Program Memory ................................................................................. 26St�uctu�e ................................................................................................................................ ��Special Vecto�s ..................................................................................................................... ��Look-up Ta�le ........................................................................................................................ �7Ta�le P�og�a� Exa�ple ........................................................................................................ �7In Ci�cuit P�og�a��ing ......................................................................................................... �8

Data Memory .................................................................................................. 29St�uctu�e ................................................................................................................................ �9

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Special Function Register Description ........................................................ 35Indi�ect Add�essing Registe�s – IAR0� IAR1 ......................................................................... �5Me�o�y Pointe�s – MP0� MP1 .............................................................................................. �5Bank Pointe� – BP ................................................................................................................. ��Accu�ulato� – ACC ............................................................................................................... ��P�og�a� Counte� Low Registe� – PCL .................................................................................. ��Look-up Ta�le Registe�s – TBLP� TBHP� TBLH ..................................................................... �7Status Registe� – STATUS .................................................................................................... �7

EEPROM Data Memory .................................................................................. 38EEPROM Data Me�o�y St�uctu�e ........................................................................................ �8EEPROM Registe�s .............................................................................................................. �9Reading Data f�o� the EEPROM ......................................................................................... 41W�iting Data to the EEPROM ................................................................................................ 41W�ite P�otection ..................................................................................................................... 41EEPROM Inte��upt ................................................................................................................ 41P�og�a��ing Conside�ation ................................................................................................. 4�P�og�a��ing Exa�ples ........................................................................................................ 4�

Oscillator ........................................................................................................ 43Oscillato� Ove�view ............................................................................................................... 4�System Clock Configurations ................................................................................................ 4�Exte�nal C�ystal/Ce�a�ic Oscillato� – HXT ........................................................................... 44Exte�nal RC Oscillato� – ERC ............................................................................................... 45Inte�nal RC Oscillato� – HIRC ............................................................................................... 45Exte�nal ��.7�8kHz C�ystal Oscillato� – LXT ........................................................................ 4�LXT Oscillato� Low Powe� Function ...................................................................................... 47Inte�nal ��kHz Oscillato� – LIRC ........................................................................................... 47Supple�enta�y Clocks .......................................................................................................... 47

Operating Modes and System Clocks ......................................................... 48Syste� Clocks ...................................................................................................................... 48Syste� Ope�ation Modes ...................................................................................................... 50Cont�ol Registe� .................................................................................................................... 51Fast Wake-up ........................................................................................................................ 5�Ope�ating Mode Switching .................................................................................................... 54Stand�y Cu��ent Conside�ations ........................................................................................... 57Wake-up ................................................................................................................................ 57P�og�a��ing Conside�ations ................................................................................................ 58

Watchdog Timer ............................................................................................. 58Watchdog Ti�e� Clock Sou�ce .............................................................................................. 58Watchdog Ti�e� Cont�ol Registe� ......................................................................................... 59Watchdog Ti�e� Ope�ation ................................................................................................... �0

Reset and Initialisation .................................................................................. 61Reset Functions .................................................................................................................... �1Reset Initial Conditions ......................................................................................................... �4

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Input/Output Ports ......................................................................................... 71I/O Po�t Registe� List ............................................................................................................. 71Pull-high Resisto�s ................................................................................................................ 7�Po�t A Wake-up ..................................................................................................................... 7�I/O Po�t Cont�ol Registe�s ..................................................................................................... 7�Pin-�e�apping Functions ...................................................................................................... 74Pin-�e�apping Registe�s ....................................................................................................... 74I/O Pin St�uctu�es .................................................................................................................. 75P�og�a��ing Conside�ations ................................................................................................ 7�

Timer Modules – TM ...................................................................................... 76Int�oduction ........................................................................................................................... 7�TM Ope�ation ........................................................................................................................ 77TM Clock Sou�ce ................................................................................................................... 77TM Inte��upts ......................................................................................................................... 77TM Exte�nal Pins ................................................................................................................... 78TM Input/Output Pin Cont�ol ................................................................................................. 78P�og�a��ing Conside�ations ................................................................................................ 8�

Compact Type TM – CTM .............................................................................. 83Co�pact TM Ope�ation ......................................................................................................... 8�Co�pact Type TM Registe� Desc�iption................................................................................ 84Co�pact Type TM Ope�ating Modes .................................................................................... 87Co�pa�e Match Output Mode ............................................................................................... 87Ti�e�/Counte� Mode ............................................................................................................. 90PWM Output Mode ................................................................................................................ 90

Standard Type TM – STM .............................................................................. 93Standa�d TM Ope�ation ......................................................................................................... 9�Standa�d Type TM Registe� Desc�iption ............................................................................... 94Standa�d Type TM Ope�ating Modes .................................................................................... 98Co�pa�e Match Output Mode ............................................................................................... 98Ti�e�/Counte� Mode ........................................................................................................... 101PWM Output Mode .............................................................................................................. 101Single Pulse Mode .............................................................................................................. 104Captu�e Input Mode ............................................................................................................ 10�

Enhanced Type TM – ETM ........................................................................... 107Enhanced TM Ope�ation ..................................................................................................... 107Enhanced Type TM Registe� Desc�iption ............................................................................ 108Enhanced Type TM Ope�ating Modes..................................................................................114Co�pa�e Match Output Mode ..............................................................................................115Ti�e�/Counte� Mode ........................................................................................................... 1�0PWM Output Mode .............................................................................................................. 1�0Single Pulse Output Mode .................................................................................................. 1��Captu�e Input Mode ............................................................................................................ 1�8

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Analog to Digital Converter ........................................................................ 131A/D Ove�view ...................................................................................................................... 1�1A/D Conve�te� Registe� Desc�iption .................................................................................... 1�1A/D Conve�te� Data Registe�s – ADRL� ADRH ................................................................... 1��A/D Conve�te� Cont�ol Registe�s – ADCR0� ADCR1� ACERL ............................................. 1��A/D Ope�ation ..................................................................................................................... 1�5A/D Input Pins ..................................................................................................................... 1��Su��a�y of A/D Conve�sion Steps ..................................................................................... 1�7P�og�a��ing Conside�ations .............................................................................................. 1�8A/D T�ansfe� Function ......................................................................................................... 1�8A/D P�og�a��ing Exa�ple ................................................................................................. 1�9

Comparators ................................................................................................ 141Co�pa�ato� Ope�ation ........................................................................................................ 141Co�pa�ato� Registe�s ......................................................................................................... 141Co�pa�ato� Inte��upt ........................................................................................................... 144P�og�a��ing Conside�ations .............................................................................................. 144

Serial Interface Module – SIM ..................................................................... 144SPI Inte�face ....................................................................................................................... 144I�C Inte�face ........................................................................................................................ 151I�C Bus Sta�t Signal ............................................................................................................. 157Slave Add�ess ..................................................................................................................... 157I�C Bus Read/W�ite Signal .................................................................................................. 157I�C Bus Slave Add�ess Acknowledge Signal ....................................................................... 157I�C Bus Data and Acknowledge Signal ............................................................................... 158

Peripheral Clock Output .............................................................................. 160Pe�iphe�al Clock Ope�ation ................................................................................................. 1�0

Interrupts ...................................................................................................... 161Inte��upt Registe�s ............................................................................................................... 1�1Inte��upt Ope�ation .............................................................................................................. 1�9Exte�nal Inte��upt ................................................................................................................. 17�Co�pa�ato� Inte��upt ........................................................................................................... 17�Multi-function Inte��upt ........................................................................................................ 17�A/D Conve�te� Inte��upt ....................................................................................................... 17�Ti�e Base Inte��upts ........................................................................................................... 17�Se�ial Inte�face Module Inte��upts ....................................................................................... 175Exte�nal Pe�iphe�al Inte��upt ............................................................................................... 175EEPROM Inte��upt .............................................................................................................. 175LVD Inte��upt ....................................................................................................................... 17�TM Inte��upts ....................................................................................................................... 17�Inte��upt Wake-up Function ................................................................................................. 17�P�og�a��ing Conside�ations .............................................................................................. 177

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Low Voltage Detector – LVD ....................................................................... 178LVD Registe� ....................................................................................................................... 178LVD Ope�ation ..................................................................................................................... 179

SCOM Function for LCD .............................................................................. 180LCD Ope�ation .................................................................................................................... 180LCD Bias Cont�ol ................................................................................................................ 181

Configuration Options ................................................................................. 182Application Circuits ..................................................................................... 183

HT��F�0-1/HT��F�0-1 ....................................................................................................... 18�HT�8F�0-1/HT�8F�0-1 ....................................................................................................... 184

Instruction Set .............................................................................................. 185Int�oduction ......................................................................................................................... 185Inst�uction Ti�ing ................................................................................................................ 185Moving and T�ansfe��ing Data ............................................................................................. 185A�ith�etic Ope�ations .......................................................................................................... 185Logical and Rotate Ope�ation ............................................................................................. 18�B�anches and Cont�ol T�ansfe� ........................................................................................... 18�Bit Ope�ations ..................................................................................................................... 18�Ta�le Read Ope�ations ....................................................................................................... 18�Othe� Ope�ations ................................................................................................................. 18�

Instruction Set Summary ............................................................................ 187Ta�le Conventions ............................................................................................................... 187

Instruction Definition ................................................................................... 189Package Information ................................................................................... 198

1�-pin DIP (�00�il) Outline Di�ensions ............................................................................. 1991�-pin �SOP (150�il) Outline Di�ensions ......................................................................... �011�-pin SSOP (150�il) Outline Di�ensions ......................................................................... �0��0-pin DIP (�00�il) Outline Di�ensions ............................................................................. �0��0-pin SOP (�00�il) Outline Di�ensions ........................................................................... �05�0-pin SSOP (150�il) Outline Di�ensions ......................................................................... �0��4-pin SKDIP (�00�il) Outline Di�ensions ........................................................................ �07�4-pin SOP (�00�il) Outline Di�ensions ........................................................................... �09�4-pin SSOP(150�il) Outline Di�ensions .......................................................................... �10

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Features

CPU Features• OperatingVoltage:

♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=20MHz:4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Fiveoscillators:♦ ExternalCrystal-HXT♦ External32.768kHzCrystal-LXT♦ ExternalRC-ERC♦ InternalRC-HIRC♦ Internal32kHzRC-LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Fullyintegratedinternal4MHz,8MHzand12MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 4-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:1K×16~2K×16

• DataMemory:64×8~96×8

• TrueEEPROMMemory:32×8~64×8

• WatchdogTimerfunction

• Upto22bidirectionalI/Olines

• Softwarecontrolled4-SCOMlinesLCDdriverwith1/2bias

• Dualpin-sharedexternalinterrupts

• MultipleTimerModulefortimemeasure,inputcapture,comparematchoutput,PWMoutputorsinglepulseoutputfunction

• SerialInterfacesModulewithDualSPIandI2Cinterfaces

• DualComparatorfunctions

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• 8-channel12-bitresolutionA/Dconverter–HT66F30-1/HT66F20-1

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• Widerangeofavailablepackagetypes

• Flashprogrammemorycanbere-programmedupto100,000times

• Flashprogrammemorydataretention>10years

• TrueEEPROMdatamemorycanbere-programmedupto1,000,000times

• TrueEEPROMdatamemorydataretention>10years

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General DescriptionTheHT66Fx0-1andHT68Fx0-1 seriesareFlashMemory typewith8-bithighperformanceRISCarchitecturemicrocontrollers,designedforawiderangeofapplications.OfferinguserstheconvenienceofFlashMemorymulti-programmingfeatures,thesedevicesalsoincludeawiderangeoffunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analog features includeamulti-channel12-bitA/Dconverteranddualcomparator functions.Multipleandextremely flexibleTimerModulesprovide timing,pulsegenerationandPWMgeneration functions.Communicationwith theoutsideworld iscatered forby including fullyintegratedSPIorI2Cinterfacefunctions, twopopular interfaceswhichprovidedesignerswithameansofeasycommunicationwithexternalperipheralhardware.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

AfullchoiceofHXT,LXT,ERC,HIRCandLIRCoscillatorfunctionsareprovidedincludingafully integratedsystemoscillatorwhichrequiresnoexternalcomponentsfor its implementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesusers theability tooptimisemicrocontrolleroperationandminimisepowerconsumption.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethatthedeviceswillfindexcellentuseinapplicationssuchaselectronicmetering,environmentalmonitoring,handheldinstruments,householdappliances,electronicallycontrolledtools,motordrivinginadditiontomanyothers.

Selection TableMost featuresarecommon toalldevices.Themain featuresdistinguishing themareProgramMemory,DataMemorycapacity,TMfeature,A/Dfunction,I/Ocountandpackagetyhpes.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. Program Memory

Data Memory

Data EEPROM I/O Ext.

Interrupt A/D Timer Module

SPI/I2C

Time Base Comp. Stack Package

HT�8F�0-1 1K×1� �4×8 ��×8 18 � --- 10-�it CTM×1 10-�it STM×1 √ � � 4 1�DIP/�SOP/SSOP

�0DIP/SOP/SSOP

HT�8F�0-1 �K×1� 9�×8 �4×8 �� --- 10-�it CTM×1 10-�it ETM×1 √ � � 4

1�DIP/�SOP/SSOP�0DIP/SOP/SSOP

�4SKDIP/SOP/SSOP

HT��F�0-1 1K×1� �4×8 ��×8 18 � 1�-�itx8 10-�it CTM×1 10-�it STM×1 √ � � 4 1�DIP/�SOP/SSOP

�0DIP/SOP/SSOP

HT��F�0-1 �K×1� 9�×8 �4×8 �� 1�-�itx8 10-�it CTM×1 10-�it ETM×1 √ � � 4

1�DIP/�SOP/SSOP�0DIP/SOP/SSOP

�4SKDIP/SOP/SSOP

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Block Diagram

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Note:OnlytheHT66F30-1andHT66F20-1deviceshaveA/Dfunction.

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Pin Assignment

HT66F20-1 & HT66F30-1

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Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.2.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe“/”signcanbeusedforhigherpriority.

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HT68F20-1 & HT68F30-1

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Note:1.Bracketedpinnamesindicatenon-defaultpinoutremappinglocations.2.Ifthepin-sharedpinfunctionshavemultipleoutputssimultaneously,itspinnamesattherightsideofthe“/”signcanbeusedforhigherpriority.

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Pin DescriptionThefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

HT66F20-1Pin Name Function OP I/T O/T Pin-Shared Mapping

PA0~PA7 Po�t A PAWUPAPU ST CMOS —

PB0~PB5 Po�t B PBPU ST CMOS —PC0~PC� Po�t C PCPU ST CMOS —A�0~A�7 ADC input ACERL A� — PA0~PA7VREF ADC �efe�ence input ADCR1 A� — PB5C0-� C1- Co�pa�ato� 0� 1 input

CP0CCP1C

A� — PA�� PC�C0+� C1+ Co�pa�ato� 0� 1 input A� — PA�� PC�C0X� C1X Co�pa�ato� 0� 1 output — CMOS PA0� PA5TCK0� TCK1 TM0� TM1 input — ST — PA�� PA4TP0_0 TM0 I/O TMPC0 ST CMOS PA0TP1_0� TP1_1 TM1 I/O TMPC0 ST CMOS PA1� PC0I�T0� I�T1 Ext. Inte��upt 0� 1 — ST — PA�� PA4PI�T Pe�iphe�al Inte��upt — ST — PC�PCK Pe�iphe�al Clock output — — CMOS PC�SDI SPI Data input — ST — PA�SDO SPI Data output — — CMOS PA5SCS SPI Slave Select — ST CMOS PB5SCK SPI Se�ial Clock — ST CMOS PA7SCL I�C Clock — ST �MOS PA7SDA I�C Data — ST �MOS PA�SCOM0~SCOM� SCOM0~SCOM� SCOMC — SCOM PC0� PC1� PC�� PC�OSC1 HXT/ERC pin CO HXT — PB1OSC� HXT pin CO — HXT PB�XT1 LXT pin CO LXT — PB�XT� LXT pin CO — LXT PB4RES Reset input CO ST — PB0VDD Powe� supply* — PWR — —AVDD ADC powe� supply* — PWR — —VSS G�ound** — PWR — —AVSS ADC g�ound** — PWR — —

Note:I/T:Inputtype; O/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power; CO:Configurationoption; ST:SchmittTriggerinputCMOS:CMOSoutput; NMOS:NMOSoutputSCOM:SoftwarecontrolledLCDCOM; AN:AnaloginputpinHXT:Highfrequencycrystaloscillator LXT:Lowfrequencycrystaloscillator*:VDDis thedevicepowersupplywhileAVDDis theADCpowersupply.TheAVDDpin isbondedtogetherinternallywithVDD.

**:VSSis thedevicegroundpinwhileAVSSis theADCgroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.

AsthePinDescriptionSummarytableappliestothepackagetypewiththemostpins,notalloftheabovelistedpinsmaybepresentonpackagetypeswithsmallernumbersofpins.

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PA0~PA7 Po�t A PAWU PAPU ST CMOS —

PB0~PB5 Po�t B PBPU ST CMOS —

PC0~PC7 Po�t C PCPU ST CMOS —

A�0~A�7 ADC input ACERL A� — PA0~PA7

VREF ADC �efe�ence input ADCR1 A� — PB5

C0-� C1- Co�pa�ato� 0� 1 inputCP0C CP1C

A� — PA�� PC�

C0+� C1+ Co�pa�ato� 0� 1 input A� — PA�� PC�

C0X� C1X Co�pa�ato� 0� 1 output — CMOS PA0� PA5

TCK0� TCK1 TM0� TM1 input — ST — PA�� PA4

TP0_0� TP0_1 TM0 I/O TMPC0 ST CMOS PA0� PC5

TP1A TM1 I/O TMPC0 ST CMOS PA1

TP1B_0� TP1B_1 TM1 I/O TMPC0 ST CMOS PC0� PC1

I�T0� I�T1 Ext. inte��upt 0� 1 — ST — PA�� PA4

PI�T Pe�iphe�al inte��upt PRM0 ST — PC� o� PC4

PCK Pe�iphe�al clock output PRM0 — CMOS PC� o� PC5

SDI SPI data input PRM0 ST — PA� o� PC0

SDO SPI data output PRM0 — CMOS PA5 o� PC1

SCS SPI slave select PRM0 ST CMOS PB5 o� PC�

SCK SPI se�ial clock PRM0 ST CMOS PA7 o� PC7

SCL I�C clock PRM0 ST �MOS PA7 o� PC7

SDA I�C data PRM0 ST �MOS PA� o� PC0

SCOM0~SCOM� SCOM0~SCOM� SCOMC — SCOM PC0� PC1� PC�� PC7

OSC1 HXT/ERC pin CO HXT — PB1

OSC� HXT pin CO — HXT PB�

XT1 LXT pin CO LXT — PB�

XT� LXT pin CO — LXT PB4

RES Reset input CO ST — PB0

VDD Powe� supply * — PWR — —

AVDD ADC powe� supply * — PWR — —

VSS G�ound ** — PWR — —

AVSS ADC g�ound ** — PWR — —

Note:I/T:Inputtype; O/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:Power; CO:Configurationoption; ST:SchmittTriggerinputCMOS:CMOSoutput; NMOS:NMOSoutputSCOM:SoftwarecontrolledLCDCOM; AN:AnaloginputpinHXT:Highfrequencycrystaloscillator; LXT:Lowfrequencycrystaloscillator*:VDDis thedevicepowersupplywhileAVDDis theADCpowersupply.TheAVDDpin isbondedtogetherinternallywithVDD.

**:VSSis thedevicegroundpinwhileAVSSis theADCgroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.


Rev. 1.40 14 �ove��e� �� 01� Rev. 1.40 15 �ove��e� �� 01�




PA0~PA7 Po�t A PAWUPAPU ST CMOS —

PB0~PB5 Po�t B PBPU ST CMOS —PC0~PC� Po�t C PCPU ST CMOS —C0-� C1- Co�pa�ato� 0� 1 input

CP0CCP1C

A� — PA�� PC�C0+� C1+ Co�pa�ato� 0� 1 input A� — PA�� PC�C0X� C1X Co�pa�ato� 0� 1 output — CMOS PA0� PA5TCK0� TCK1 TM0� TM1 input — ST — PA�� PA4TP0_0 TM0 I/O TMPC0 ST CMOS PA0TP1_0� TP1_1 TM1 I/O TMPC0 ST CMOS PA1� PC0I�T0� I�T1 Ext. Inte��upt 0� 1 — ST — PA�� PA4PI�T Pe�iphe�al Inte��upt — ST — PC�PCK Pe�iphe�al Clock output — — CMOS PC�SDI SPI Data input — ST — PA�SDO SPI Data output — — CMOS PA5SCS SPI Slave Select — ST CMOS PB5SCK SPI Se�ial Clock — ST CMOS PA7SCL I�C Clock — ST �MOS PA7SDA I�C Data — ST �MOS PA�SCOM0~SCOM� SCOM0~SCOM� SCOMC — SCOM PC0� PC1� PC�� PC�OSC1 HXT/ERC pin CO HXT — PB1OSC� HXT pin CO — HXT PB�XT1 LXT pin CO LXT — PB�XT� LXT pin CO — LXT PB4RES Reset input CO ST — PB0VDD Powe� supply — PWR — —VSS G�ound — PWR — —

Note:I/T:InputtypeO/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:PowerCO:ConfigurationoptionST:SchmittTriggerinputCMOS:CMOSoutputNMOS:NMOSoutputSCOM:SoftwarecontrolledLCDCOMAN:AnaloginputpinHXT:HighfrequencycrystaloscillatorLXT:Lowfrequencycrystaloscillator


Rev. 1.40 14 �ove��e� �� 01� Rev. 1.40 15 �ove��e� �� 01�




PA0~PA7 Po�t A PAWU PAPU ST CMOS —

PB0~PB5 Po�t B PBPU ST CMOS —

PC0~PC7 Po�t C PCPU ST CMOS —

C0-� C1- Co�pa�ato� 0� 1 inputCP0C CP1C

A� — PA�� PC�

C0+� C1+ Co�pa�ato� 0� 1 input A� — PA�� PC�

C0X� C1X Co�pa�ato� 0� 1 output — CMOS PA0� PA5

TCK0� TCK1 TM0� TM1 input — ST — PA�� PA4

TP0_0� TP0_1 TM0 I/O TMPC0 ST CMOS PA0� PC5

TP1A TM1 I/O TMPC0 ST CMOS PA1

TP1B_0� TP1B_1 TM1 I/O TMPC0 ST CMOS PC0� PC1

I�T0� I�T1 Ext. inte��upt 0� 1 — ST — PA�� PA4

PI�T Pe�iphe�al inte��upt PRM0 ST — PC� o� PC4

PCK Pe�iphe�al clock output PRM0 — CMOS PC� o� PC5

SDI SPI data input PRM0 ST — PA� o� PC0

SDO SPI data output PRM0 — CMOS PA5 o� PC1

SCS SPI slave select PRM0 ST CMOS PB5 o� PC�

SCK SPI se�ial clock PRM0 ST CMOS PA7 o� PC7

SCL I�C clock PRM0 ST �MOS PA7 o� PC7

SDA I�C data PRM0 ST �MOS PA� o� PC0

SCOM0~SCOM� SCOM0~SCOM� SCOMC — SCOM PC0� PC1� PC�� PC7

OSC1 HXT/ERC pin CO HXT — PB1

OSC� HXT pin CO — HXT PB�

XT1 LXT pin CO LXT — PB�

XT� LXT pin CO — LXT PB4

RES Reset input CO ST — PB0

VDD Powe� supply — PWR — —

VSS G�ound — PWR — —

Note:I/T:InputtypeO/T:OutputtypeOP:Optionalbyconfigurationoption(CO)orregisteroptionPWR:PowerCO:ConfigurationoptionST:SchmittTriggerinputCMOS:CMOSoutputNMOS:NMOSoutputSCOM:SoftwarecontrolledLCDCOMAN:AnaloginputpinHXT:HighfrequencycrystaloscillatorLXT:Lowfrequencycrystaloscillator


Rev. 1.40 1� �ove��e� �� 01� Rev. 1.40 17 �ove��e� �� 01�



Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOHTotal....................................................................................................................................-80mAIOLTotal..................................................................................................................................... 80mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. Characteristics

HT66F20-1/HT66F30-1Ta=25˚C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDDOpe�ating Voltage (HXT� ERC� HIRC) —

fSYS=8MHz �.� — 5.5 V

fSYS=1�MHz �.7 — 5.5 V

fSYS=�0MHz 4.5 — 5.5 V

IDD1Ope�ating Cu��ent� �o��al Mode� fSYS=fH (HXT� ERC� HIRC)

�V �o load� fSYS=fH=4MHz�ADC off� WDT ena�le

— 0.7 1.1 �A

5V — 1.8 �.7 �A

�V �o load� fSYS=fH=8MHz�ADC off� WDT ena�le

— 1.� �.4 �A

5V — �.� 5.0 �A

�V �o load� fSYS=fH=1�MHz�ADC off� WDT ena�le

— �.� �.� �A

5V — 5.0 7.5 �A

IDD�Ope�ating Cu��ent� �o��al Mode� fSYS=fH (HXT) 5V �o load� fSYS=fH=�0MHz�

ADC off� WDT ena�le — �.0 9.0 �A

IDD�Ope�ating Cu��ent� Slow Mode�fSYS=fL (LXT� LIRC)

�V �o load� fSYS=fL� ADC off�WDT ena�le

— 10 �0 μA

5V — �0 50 μA

IIDLE0IDLE0 Mode Stand�y Cu��ent(LXT o� LIRC on)

�V �o load� ADC off� WDT ena�le

— 1.5 �.0 μA

5V — �.0 �.0 μA

IIDLE1IDLE1 Mode Stand�y Cu��ent(HXT� ERC� HIRC)

�V �o load� ADC off� WDT ena�le� fSYS=1�MHz on

— 0.55 0.8� �A

5V — 1.�0 �.00 �A

ISLEEP0SLEEP0 Mode Stand�y Cu��ent(LXT and LIRC off)

�V �o load� ADC off� WDT disa�le

— — 1 μA

5V — — � μA

ISLEEP1SLEEP1 Mode Stand�y Cu��ent(LXT o� LIRC on)

�V �o load� ADC off� WDT ena�le

— 1.5 �.0 μA

5V — �.5 5.0 μA

Rev. 1.40 1� �ove��e� �� 01� Rev. 1.40 17 �ove��e� �� 01�





VIL1Input Low Voltage fo� I/O Po�ts o� Input Pins except RES pin — — 0 — 0.�VDD V

VIH1Input High Voltage fo� I/O Po�ts o� Input Pins except RES pin — — 0.7VDD — VDD V

VIL� Input Low Voltage (RES) — — 0 — 0.4VDD V

VIH� Input High Voltage (RES) — — 0.9VDD — VDD V

VLVR LVR Voltage Level —

LVR Ena�le� �.10V option -5% �.10 +5% V



LVR Ena�le� 4.�0V option -5% 4.�0 +5% V

VLVD LVD Voltage Level —

LVDE�=1� VLVD=�.0V -5% �.00 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=�.4V -5% �.40 +5% V

LVDE�=1� VLVD=�.7V -5% �.70 +5% V

LVDE�=1� VLVD=�.0V -5% �.00 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=4.4V -5% 4.40 +5% V

ILVAdditional Powe� Consu�ption if LVR and LVD is Used —

LVR ena�le� LVDE�=0 — �0 90 μA

LVR disa�le� LVDE�=1 — 75 115 μA

LVR ena�le� LVDE�=1 — 90 1�5 μA

VOL Output Low Voltage I/O Po�t�V IOL=9�A — — 0.� V

5V IOL=�0�A — — 0.5 V

VOH Output High Voltage I/O Po�t�V IOH=-�.��A �.7 — — V

5V IOH=-7.4�A 4.5 — — V

RPH Pull-high Resistance fo� I/O Po�ts�V

—�0 �0 100 kΩ

5V 10 �0 50 kΩ

ISCOM SCOM Ope�ating Cu��ent 5V

SCOMC� ISEL[1:0]=00 17.5 �5.0 ��.5 μA

SCOMC� ISEL[1:0]=01 �5 50 �5 μA

SCOMC� ISEL[1:0]=10 70 100 1�0 μA

SCOMC� ISEL[1:0]=11 140 �00 ��0 μA

VSCOM VDD/� Voltage fo� LCD COM 5V �o load 0.475 0.500 0.5�5 VDD

V1�5 1.�5V Refe�ence with Buffe� Voltage — — -�% 1.�5 +�% V

I1�5Additional Powe� Consu�ption if 1.�5V Refe�ence with Buffe� is used — — — �00 �00 μA

Rev. 1.40 18 �ove��e� �� 01� Rev. 1.40 19 �ove��e� �� 01�



HT68F20-1/HT68F30-1Ta=25˚C



VDDOpe�ating Voltage (HXT� ERC� HIRC) —

fSYS=8MHz �.� — 5.5 V

fSYS=1�MHz �.7 — 5.5 V

fSYS=�0MHz 4.5 — 5.5 V

IDD1

Ope�ating Cu��ent��o��al Mode� fSYS=fH(HXT� ERC� HIRC)

�V �o load� fSYS=fH=4MHz�WDT ena�le

— 0.7 1.1 �A

5V — 1.8 �.7 �A

�V �o load� fSYS=fH=8MHz�WDT ena�le

— 1.� �.4 �A

5V — �.� 5.0 �A

�V �o load� fSYS=fH=1�MHz�WDT ena�le

— �.� �.� �A

5V — 5.0 7.5 �A

IDD�Ope�ating Cu��ent��o��al Mode� fSYS=fH (HXT) 5V �o load� fSYS=fH=�0MHz�

WDT ena�le — �.0 9.0 �A

IDD�Ope�ating Cu��ent� Slow Mode�fSYS=fL (LXT� LIRC)

�V �o load� fSYS=fL�WDT ena�le

— 10 �0 μA

5V — �0 50 μA

IIDLE0IDLE0 Mode Stand�y Cu��ent(LXT o� LIRC on)

�V�o load� WDT ena�le

— 1.5 �.0 �A

5V — �.0 �.0 �A

IIDLE1IDLE1 Mode Stand�y Cu��ent(HXT� ERC� HIRC)

�V �o load� WDT ena�le� fSYS=1�MHz on

— 0.55 0.8� �A

5V — 1.�0 �.00 �A

ISLEEP0SLEEP0 Mode Stand�y Cu��ent(LXT and LIRC off)

�V�o load� WDT disa�le

— — 1 μA

5V — — � μA

ISLEEP1SLEEP1 Mode Stand�y Cu��ent(LXT o� LIRC on)

�V�o load� WDT ena�le

— 1.5 �.0 μA

5V — �.5 5.0 μA

VIL1Input Low Voltage fo� I/O Po�ts o� Input Pins except RES pin — — 0 — 0.�VDD V

VIH1Input High Voltage fo� I/O Po�tso� Input Pins except RES pin — — 0.7VDD — VDD V

VIL� Input Low Voltage (RES) — — 0 — 0.4VDD V

VIH� Input High Voltage (RES) — — 0.9VDD — VDD V

VLVR LVR Voltage Level —




LVR Ena�le� 4.�0V option -5% 4.�0 +5% V

VLVD LVD Voltage Level —

LVDE�=1� VLVD=�.0V -5% �.00 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=�.4V -5% �.40 +5% V

LVDE�=1� VLVD=�.7V -5% �.70 +5% V

LVDE�=1� VLVD=�.0V -5% �.00 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=�.�V -5% �.�0 +5% V

LVDE�=1� VLVD=4.4V -5% 4.40 +5% V

Rev. 1.40 18 �ove��e� �� 01� Rev. 1.40 19 �ove��e� �� 01�





ILVAdditional Powe� Consu�ption if LVR and LVD is used —

LVR ena�le� LVDE�=0 — �0 90 μA

LVR disa�le� LVDE�=1 — 75 115 μA

LVR ena�le� LVDE�=1 — 90 1�5 μA

VOL Output Low Voltage I/O Po�t�V IOL=9�A — — 0.� V

5V IOL=�0�A — — 0.5 V

VOH Output High Voltage I/O Po�t�V IOH=-�.��A �.7 — — V

5V IOH=-7.4�A 4.5 — — V

RPH Pull-high Resistance fo� I/O Po�ts�V

—�0 �0 100 kΩ

5V 10 �0 50 kΩ

ISCOM SCOM Ope�ating Cu��ent 5V

SCOMC� ISEL[1:0]=00 17.5 �5.0 ��.5 μA

SCOMC� ISEL[1:0]=01 �5 50 �5 μA

SCOMC� ISEL[1:0]=10 70 100 1�0 μA

SCOMC� ISEL[1:0]=11 140 �00 ��0 μA

VSCOM VDD/� Voltage fo� LCD COM 5V �o load 0.475 0.500 0.5�5 VDD

A.C. Characteristics

HT66F20-1/HT66F30-1Ta=25˚C



fCPU Ope�ating Clock —

�.�V~5.5V DC — 8 MHz

�.7V~5.5V DC — 1� MHz

4.5V~5.5V DC — �0 MHz

fSYS Syste� Clock (HXT) —

�.�V~5.5V 0.4 — 8 MHz

�.7V~5.5V 0.4 — 1� MHz

4.5V~5.5V 0.4 — �0 MHz

fHIRC Syste� Clock (HIRC)

�V/5V Ta=25˚C -�% 4 +�% MHz�V/5V Ta=25˚C -�% 8 +�% MHz

5V Ta=25˚C -�% 1� +�% MHz�V/5V Ta=0~70˚C -5% 4 +5% MHz�V/5V Ta=0~70˚C -4% 8 +4% MHz

5V Ta=0~70˚C -5% 1� +�% MHz�.�V~�.�V Ta=0~70˚C -7% 4 +7% MHz�.0V~5.5V Ta=0~70˚C -5% 4 +9% MHz�.�V~�.�V Ta=0~70˚C -�% 8 +4% MHz�.0V~5.5V Ta=0~70˚C -4% 8 +9% MHz�.0V~5.5V Ta=0~70˚C -�% 1� +7% MHz�.�V~�.�V Ta=-40˚C~85˚C -1�% 4 +8% MHz�.0V~5.5V Ta=-40˚C~85˚C -10% 4 +9% MHz�.�V~�.�V Ta=-40˚C~85˚C -15% 8 +4% MHz�.0V~5.5V Ta=-40˚C~85˚C -8% 8 +9% MHz�.0V~5.5V Ta=-40˚C~85˚C -1�% 1� +7% MHz

Rev. 1.40 �0 �ove��e� �� 01� Rev. 1.40 �1 �ove��e� �� 01�





fERC Syste� Clock (ERC)

5V Ta=25˚C, R=120kΩ* -�% 8 +�% MHz

5V Ta=0~70˚C, R=120kΩ* -5% 8 +�% MHz

5V Ta=-40˚C~85˚C, R=120kΩ* -7% 8 +9% MHz

�.0V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -9% 8 +10% MHz

�.�V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -15% 8 +10% MHz

fLXT Syste� Clock (LXT) — — — ��.7�8 — kHz

fLIRC Syste� Clock (LIRC)5V Ta=25˚C -10% �� +10% kHz

�.�V~5.5V Ta=-40˚C~85˚C -50% �� +�0% kHz

fTIMER Ti�e� Input Pin F�equency — — — — 1 fSYS

tRES Exte�nal Reset Low Pulse Width — — 1 — — μs

tI�T Inte��upt Pulse Width — — 1 — — tSYS

tLVR Low Voltage Width to Reset — — 1�0 �40 480 μs

tLVD Low Voltage Width to Inte��upt — — �0 45 90 μs

tLVDS LVDO sta�le ti�e — — 15 — — μs

tBGS VBG Tu�n on Sta�le Ti�e — — �00 — — μs

tEERD EEPROM Read Ti�e — — — 45 90 μs

tEEWR EEPROM W�ite Ti�e — — — � 4 �s

tSSTSyste� Sta�t-up Ti�e� Pe�iod(Wake-up f�o� HALT) —

fSYS=HXT o� LXT — 10�4 —

tSYSfSYS=ERC o� HIRC — 15~1� —

fSYS=LIRC OSC — 1~� —

Note:1.tSYS=1/fSYS

2.*ForfERC,astheresistortolerancewillinfluencethefrequencyaprecisionresistorisrecommended.3.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

Rev. 1.40 �0 �ove��e� �� 01� Rev. 1.40 �1 �ove��e� �� 01�



HT68F20-1/HT68F30-1Ta=25˚C



fCPU Ope�ating Clock —�.�V~5.5V DC — 8 MHz�.7V~5.5V DC — 1� MHz4.5V~5.5V DC — �0 MHz

fSYS Syste� Clock (HXT) —�.�V~5.5V 0.4 — 8 MHz�.7V~5.5V 0.4 — 1� MHz4.5V~5.5V 0.4 — �0 MHz

fHIRC Syste� Clock (HIRC)

�V/5V Ta=25˚C -�% 4 +�% MHz�V/5V Ta=25˚C -�% 8 +�% MHz

5V Ta=25˚C -�% 1� +�% MHz�V/5V Ta=0~70˚C -5% 4 +5% MHz�V/5V Ta=0~70˚C -4% 8 +4% MHz

5V Ta=0~70˚C -5% 1� +�% MHz�.�V~�.�V Ta=0~70˚C -7% 4 +7% MHz�.0V~5.5V Ta=0~70˚C -5% 4 +9% MHz�.�V~�.�V Ta=0~70˚C -�% 8 +4% MHz�.0V~5.5V Ta=0~70˚C -4% 8 +9% MHz�.0V~5.5V Ta=0~70˚C -�% 1� +7% MHz�.�V~�.�V Ta=-40˚C~85˚C -1�% 4 +8% MHz�.0V~5.5V Ta=-40˚C~85˚C -10% 4 +9% MHz�.�V~�.�V Ta=-40˚C~85˚C -15% 8 +4% MHz�.0V~5.5V Ta=-40˚C~85˚C -8% 8 +9% MHz�.0V~5.5V Ta=-40˚C~85˚C -1�% 1� +7% MHz

fERC Syste� Clock (ERC)

5V Ta=25˚C, R=120kΩ* -�% 8 +�% MHz5V Ta=0~70˚C, R=120kΩ* -5% 8 +�% MHz5V Ta=-40˚C~85˚C, R=120kΩ* -7% 8 +9% MHz

�.0V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -9% 8 +10% MHz�.�V~5.5V Ta=-40˚C~85˚C, R=120kΩ* -15% 8 +10% MHz

fLXT Syste� Clock (LXT) — — — ��.7�8 — kHz

fLIRC Syste� Clock (LIRC)5V Ta=25˚C -10% �� +10% kHz

�.�V~5.5V Ta=-40˚C~85˚C -50% �� +�0% kHzfTIMER Ti�e� Input Pin F�equency — — — — 1 fSYS

tRES Exte�nal Reset Low Pulse Width — — 1 — — μstI�T Inte��upt Pulse Width — — 1 — — tSYS

tLVR Low Voltage Width to Reset — — 1�0 �40 480 μstLVD Low Voltage Width to Inte��upt — — �0 45 90 μstLVDS LVDO sta�le ti�e — — 15 — — μstBGS VBG Tu�n on Sta�le Ti�e — — �00 — — μstEERD EEPROM Read Ti�e — — — 45 90 μstEEWR EEPROM W�ite Ti�e — — — � 4 �s

tSSTSyste� Sta�t-up Ti�e� Pe�iod (Wake-up f�o� HALT) —

fSYS=HXT o� LXT — 10�4 —tSYSfSYS=ERC o� HIRC — 15~1� —

fSYS=LIRC OSC — 1~� —

Note:1.tSYS=1/fSYS

2.*ForfERC,astheresistortolerancewillinfluencethefrequencyaprecisionresistorisrecommended.3.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.

Rev. 1.40 �� ove��e� �� 01� Rev. 1.40 �� ove��e� �� 01�



A/D Converter Characteristics

HT66F20-1/HT66F30-1Ta=25˚C


Min. Typ. Max. UnitVDD Condition

AVDD A/D Conve�te� Ope�ating Voltage — — �.7 — 5.5 VVADI A/D Conve�te� Input Voltage — — 0 — VREF VVREF A/D Conve�te� Refe�ence Voltage — — � — AVDD VD�L Diffe�ential non-linea�ity 5V tADCK=1.0μs — ±1 +� LSBI�L Integ�al non-linea�ity 5V tADCK=1.0μs — ±� +4 LSB

IADCAdditional Powe� Consu�ption if A/D Conve�te� is used

�V �o load (tADCK=0.5μs ) — 0.90 1.�5 �A5V �o load (tADCK=0.5μs ) — 1.�0 1.80 �A

tADCK A/D Conve�te� Clock Pe�iod — — 0.5 — 10 μs

tADCA/D Conve�sion Ti�e (Include Sa�ple and Hold Ti�e) — 1� �it A/D Conve�te� — 1� — tADCK

tADS A/D Conve�te� Sa�pling Ti�e — — — 4 — tADCK

tO��ST A/D Conve�te� On-to-Sta�t Ti�e — — � — — μs

Comparator Electrical CharacteristicsTa=25˚C



VCMP Co�pa�ato� ope�ating voltage — — �.� — 5.5 V

ICMP Co�pa�ato� ope�ating cu��ent �V — — �7 5� μA5V — — 1�0 �00 μA

VCMPOS Co�pa�ato� input offset voltage — — -10 — +10 �VVHYS Hyste�esis width — �0 40 �0 �VVCM Co�pa�ato� co��on �ode voltage �ange — — VSS — VDD-1.4V VAOL Co�pa�ato� open loop gain — — �0 80 — dB

tPD Co�pa�ato� �esponse ti�e�V

With 100�V ove�d�ive(�ote) — �70 5�0 ns5V

Note:MeasuredwithcomparatoroneinputpinatVCM=(VDD-1.4)/2whiletheotherpininputtransitionfromVSSto(VCM+100mV)orfromVDDto(VCM-100mV).

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Power on Reset Electrical CharacteristicsTa=25˚C



VPOR VDD Sta�t Voltage to ensu�e Powe�-on Reset — — — — 100 �VRRVDD VDD Rise Rate to ensu�e Powe�-on Reset — — 0.0�5 — — V/�s

tPORMini�u� Ti�e fo� VDD to �e�ain at VPOR to ensu�e Powe�-on Reset — — 1 — — �s

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System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofdevicestakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthesedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derived fromeitheraHXT,LXT,HIRC,LIRCorERCoscillator issubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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System Clocking and Pipelining

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionis executed except for instructions, such as “JMP” or “CALL” that demand a jump to anon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

DeviceProgram Counter

Program Counter High Byte PCL Register

HT��F�0-1/HT�8F�0-1 PC9~PC8 PCL7~PCL0HT��F�0-1/HT�8F�0-1 PC10~PC8 PCL7~PCL0

Program CounterThelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly;however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleis

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neededtopre-fetch.

StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackhasfourlevelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallor interruptacknowledgesignal, thecontentsof theProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

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Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

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Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthesedevicesseriestheProgramMemoryareFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberof times,allowing theuser theconvenienceofcodemodificationon thesamedevice.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof1K×16bits to2K×16bits.TheProgramMemory isaddressedbytheProgramCounterandalsocontainsdata, tableinformationandinterruptentries.Tabledata,whichcanbesetup inany locationwithin theProgramMemory, isaddressedbyaseparatetablepointerregister.

Device CapacityHT��F�0-1 / HT�8F�0-1 1K×1�

HT��F�0-1 / HT�8F�0-1 �K×1�

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000Hisreservedforusebythesedevicesresetforprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.

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Program Memory Structure

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Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas“0”.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"700H"whichreferstothestartaddressof thelastpagewithinthe2KProgramMemoryof theHT6xF30-1.Thetablepointer issetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"706H"or6locationsafterthestartofthelastpage.Notethatthevalueforthetablepointerisreferencedtothefirstaddressofthepresentpageifthe"TABRD[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRD[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

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Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 ::mov a,06h ; initialise low table pointer - note that this address ; is referencedmov tblp, a ; to the last page or present page mov a, 07h ; initialise high table pointermov tbhp, a::tabrdl tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address “706H” transferred to ; tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “705H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register tempreg2::org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::

In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovides theuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.

Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga5-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,and thenprogrammingorupgradingtheprogramatalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

MCU Programming Pins FunctionPA0 Se�ial Data Input/OutputPA� Se�ial ClockRES Device ResetVDD Powe� SupplyVSS G�ound

TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis5-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandonelineforthereset.Thetechnicaldetailsregardingtheincircuitprogrammingofthedeviceisbeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

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Duringtheprogrammingprocess theRESpinwillbeheld lowbytheprogrammerdisablingthenormaloperationof themicrocontrollerandtakingcontrolof thePA0andPA2I/Opinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

Programmer Pin MCU PinsRES PB0DATA PA0CLK PA�

Programmer and MCU Pins

Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.

ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,which isonlyaccessible inBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforalldevicesistheaddress00H.

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Special PurposeData Memory

General PurposeData Memory

00H

5FH

60H

BFH

EEC at 40H in bank 1

Special PurposeData Memory

General PurposeData Memory

00H

5FH

60H

9FH

EEC at 40H in bank 1

HT66F20-1/HT68F20-1

HT66F30-1/HT68F30-1

Data Memory Structure

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HT66F20-1 Special Purpose Data Memory

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Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section dataadres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 codeorg 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbyMP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

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Bank Pointer – BPTheDataMemoryisdividedintotwobanks.SelectingtheDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0or1.

TheDataMemoryis initialised toBank0afterareset,exceptforaWDTtime-outreset in thePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.DirectlyaddressingtheDataMemorywillalways result inBank0beingaccessed irrespectiveof thevalueof theBankPointer.Accessingdatafrombanksother thanBank0mustbeimplementedusingIndirectaddressing.

AsboththeProgramMemoryandDataMemorysharethesameBankPointerRegister,caremustbetakenduringprogramming.

• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas“0”Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

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Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointerandindicates thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Rev. 1.40 �8 �ove��e� �� 01� Rev. 1.40 �9 �ove��e� �� 01�



STATUS Register

Bit 7 6 5 4 3 2 1 0�a�e — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

" x" unknownBit7,6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

EEPROM Data MemoryAlldevicescontainanareaof internalEEPROMDataMemory.EEPROM,whichstands forElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityisupto64×8bits.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemory isnotdirectlymapped intomemoryspaceand isthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperations to theEEPROMarecarriedout insinglebyteoperationsusinganaddressanddataregisterinBank0andasinglecontrolregisterinBank1.

Device Capacity AddressHT��F�0-1/HT�8F�0-1 ��×8 00H~1FHHT��F�0-1/HT�8F�0-1 �4×8 00H~�FH

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EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbeaddresseddirectlyandcanonlybereadfromorwritten to indirectlyusing theMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

EEPROM Register List• HT66F20-1/HT68F20-1

NameBit

7 6 5 4 3 2 1 0EEA — — — D4 D� D� D1 D0EED D7 D� D5 D4 D� D� D1 D0EEC — — — — WRE� WR RDE� RD

• HT66F30-1/HT68F30-1

NameBit

7 6 5 4 3 2 1 0EEA — — D5 D4 D� D� D1 D0EED D7 D� D5 D4 D� D� D1 D0EEC — — — — WRE� WR RDE� RD

EEA Register• HT66F20-1/HT68F20-1

Bit 7 6 5 4 3 2 1 0�a�e — — — D4 D� D� D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — x x x x x

“x” unknownBit7~5 Unimplemented,readas“0”Bit4~0 D4~D0:DataEEPROMaddress

DataEEPROMaddressbit4~bit0

• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — — D5 D4 D� D� D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — x x x x x x

“x” unknownBit7~6 Unimplemented,readas“0”Bit5~0 D5~D0:DataEEPROMaddress


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EEC Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — WRE� WR RDE� RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Undefined,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

EED Register

Bit 7 6 5 4 3 2 1 0�a�e D7 D� D5 D4 D� D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x” unknownBit7~0 D7~D0:DataEEPROMaddress


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Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethigh toenable thewritefunction.TheEEPROMaddressof thedata tobewrittenmust thenbeplacedintheEEAregisterandthedataplacedintheEEDregister.IftheWRbitintheEECregisterisnowsethigh,aninternalwritecyclewillthenbeinitiated.SettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates, theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteor read interrupt isgeneratedwhenanEEPROMwriteor readcyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.Howeveras theEEPROMiscontainedwithinaMulti-functionInterrupt, theassociatedmulti-function interruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-function interrupt request flagwillbothbeset. If theglobal,EEPROMandMulti-function interruptsareenabledand thestack isnot full,a jumptotheassociatedMulti-functionInterruptvectorwill takeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.MoredetailscanbeobtainedintheInterruptsection.

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Programming ConsiderationCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

Programming Examples

Reading Data from the EEPROM – Polling MethodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BPMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A

Writing Data from the EEPROM – Polling MethodMOV A,EEPROM_ADRES ;userdefinedaddressMOV EEA,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;startWriteCycle-setWRbitBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BP

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OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellas fully integrated internaloscillators, requiringnoexternalcomponents,areprovided to formawide rangeof both fast and slow systemoscillators.All oscillatoroptionsareselected throughtheconfigurationoptions.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywith it thedisadvantageofhigherpowerrequirements,while theoppositeisofcoursetruefor thelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thesedeviceshavetheflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq. Pins

Exte�nal C�ystal HXT 400kHz~�0MHz OSC1/OSC�

Exte�nal RC ERC 8MHz OSC1

Inte�nal High Speed RC HIRC 4� 8� 1�MHz —

Exte�nal Low Speed C�ystal LXT ��.7�8kHz XT1/XT�

Inte�nal Low Speed RC LIRC ��kHz —

Oscillator Types

System Clock ConfigurationsTherearefivemethodsofgeneratingthesystemclock, threehighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsare theexternalcrystal/ceramicoscillator,externalRCnetworkoscillatorandtheinternal4MHz,8MHzor12MHzRCoscillator.Thetwolowspeedoscillatorsare the internal32kHzRCoscillatorand theexternal32.768kHzcrystaloscillator.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactual sourceclockused foreachof thehighspeedand lowspeedoscillators ischosenviaconfigurationoptions.Thefrequencyof theslowspeedorhighspeedsystemclock isalsodeterminedusing theHLCLKbitandCKS2~CKS0bits in theSMODregister.Note that twooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.

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System Clock Configurations

External Crystal/Ceramic Oscillator – HXTTheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer'sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

Rev. 1.40 44 �ove��e� �� 01� Rev. 1.40 45 �ove��e� �� 01�



Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C21�MHz 0pF 0pF8MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pF

�ote: 1. C1 and C� values a�e fo� guidance only.

Crystal Recommended Capacitor Values

External RC Oscillator – ERCUsingtheERCoscillatoronlyrequiresthataresistor,withavaluebetween56kΩand2.4MΩ,isconnectedbetweenOSC1andVDD,andacapacitor isconnectedbetweenOSC1andground,providinga lowcostoscillatorconfiguration.It isonly theexternalresistor thatdetermines theoscillationfrequency;theexternalcapacitorhasnoinfluenceoverthefrequencyandisconnectedforstabilitypurposesonly.Devicetrimmingduringthemanufacturingprocessandtheinclusionof internal frequencycompensationcircuitsareused toensure that the influenceof thepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresistance/frequencyreferencepoint,itcanbenotedthatwithanexternal120kΩresistorconnectedandwitha5Vvoltagepowersupplyandtemperatureof25˚Cdegrees, theoscillatorwillhaveafrequencyof8MHzwithinatoleranceof2%.HereonlytheOSC1pinisused,whichissharedwithI/OpinPB1,leavingpinPB2freeforuseasanormalI/Opin.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk,itisimportanttolocatethecapacitorandresistorasclosetotheMCUaspossible.

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External RC Oscillator — ERC

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesofeither4MHz,8MHzor12MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyofeither3Vor5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof4MHz,8MHzor12MHzwillhavea tolerancewithin2%.Note that if this internalsystemclockoption isselected,as itrequiresnoexternalpinsforitsoperation,I/OpinsPB1andPB2arefreeforuseasnormalI/Opins.

Rev. 1.40 4� �ove��e� �� 01� Rev. 1.40 47 �ove��e� �� 01�



External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoaddtwosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselected inconsultationwith thecrystalor resonatormanufacturer’sspecification.Theexternalparallelfeedbackresistor,Rp,isrequired.

SomeconfigurationoptionsdetermineiftheXT1/XT2pinsareusedfortheLXToscillatororasI/Opins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Opins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwith interconnectinglinesarealllocatedasclosetotheMCUaspossible.

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External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C2��.7�8kHz 10pF 10pF

�ote: 1. C1 and C� values a�e fo� guidance only.�. RP=5MΩ~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Rev. 1.40 4� �ove��e� �� 01� Rev. 1.40 47 �ove��e� �� 01�



LXT Oscillator Low Power FunctionTheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheTBCregister.

LXTLP Bit LXT Mode0 Quick Sta�t1 Low-powe�

AfterpowerontheLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally, theonlydifference is that itwill takemore time tostartup if in theLow-powermode.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviaconfigurationoption.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25˚Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary ClocksThelowspeedoscillators,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksourcetotwootherdevicesfunctions.ThesearetheWatchdogTimerandtheTimeBaseInterrupts.

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Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthesedeviceswithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationoftheirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedeviceshavemanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequency,fH,or lowfrequency,fL,source,and is selectedusing theHLCLKbit andCKS2~CKS0bits in theSMODregister.ThehighspeedsystemclockcanbesourcedfromeitheraHXT,ERCorHIRCoscillator,selectedviaaconfigurationoption.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfL.IffLisselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillators,selectedviaaconfigurationoption.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfor theperipheralcircuits, thesubstituteclock,fSUB,andtheTimeBaseclock, fTBC.Eachof these internalclocks issourcedbyeither theLXTorLIRCoscillators,selectedviaconfigurationoptions.ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.

Rev. 1.40 48 �ove��e� �� 01� Rev. 1.40 49 �ove��e� �� 01�



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System Clock Configurations

Note:WhenthesystemclocksourcefSYSisswitchedtofLfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

TogetherwithfSYS/4itisalsousedasoneoftheclocksourcesfortheWatchdogtimer.ThefTBCclockisusedasasourcefortheTimeBaseinterruptfunctionsandfortheTMs.

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System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operation Mode

Description

CPU fSYS fSUB fS fTBC

�ORMAL Mode On fH~fH/�4 On On OnSLOW Mode On fL On On OnIDLE0 Mode Off Off On On/Off OnIDLE1 Mode Off On On On OnSLEEP0 Mode Off Off Off Off OffSLEEP1 Mode Off Off On On Off

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,eithertheHXT,ERCorHIRCoscillators.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbits in theSMODregister.Althoughahighspeedoscillator isused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEP0ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP0modetheCPUwillbestopped,andthefSUBandfSclockswillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustsetto"0".IftheLVDENissetto"1",itwon’tentertheSLEEP0Mode.

SLEEP1 ModeTheSLEEP1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.However,thefSUBandfSclockswillcontinuetooperateiftheLVDENis"1"ortheWatchdogTimerfunctionisenabledandifitsclocksourceischosenviaconfigurationoptiontocomefromthefSUB.

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IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheWDTCregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimer,TMsandSIM.IntheIDLE0Mode,thesystemoscillatorwillbestopped.IntheIDLE0ModetheWatchdogTimerclock,fS,willeitherbeonoroffdependinguponthefSclocksource.IfthesourceisfSYS/4thenthefSclockwillbeoff,andifthesourcecomesfromfSUBthenfSwillbeon.

IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstruction isexecutedandwhentheIDLENbit intheSMODregisterishighandtheFSYSONbitintheWDTCregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimer,TMsandSIM.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fS,willbeon.IfthesourceisfSYS/4thenthefSclockwillbeon,andifthesourcecomesfromfSUBthenfSwillbeon.

Control RegisterAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthesedevices.

SMOD Register

Bit 7 6 5 4 3 2 1 0�a�e CKS� CKS1 CKS0 FSTE� LTO HTO IDLE� HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 0 1 1

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fL(fLXTorfLIRC)001:fL(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeeithertheLXTorLIRC,adividedversionof thehighspeedsystemoscillatorcanalsobechosenas thesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if thefSUBclocksource isinitiallyusedafterthesedeviceswakeup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

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Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesif theLXToscillatorisusedand1~2clockcyclesiftheLIRCoscillatorisused.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

This is thehighspeedsystemoscillator readyflagwhich indicateswhen thehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthesedevicesarepoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicespower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter1024clockcyclesiftheHXToscillatorisusedandafter15~16clockcyclesiftheERCorHIRCoscillatorisused.

Bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthesedeviceswillenter theIDLEMode.In theIDLE1ModetheCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbit ishigh.IfFSYSONbit is low,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthesedeviceswillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:Systemclockselection0:fH/2~fH/64orfL1:fH

Thisbit isusedtoselect if thefHclockor thefH/2~fH/64orfLclockisusedas thesystemclock.When thebit ishigh the fH clockwillbe selectedand if low thefH/2~fH/64orfLclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefLclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

Fast Wake-upTominimisepowerconsumptionthesedevicescanenter theSLEEPorIDLE0Mode,wherethesystemclocksource to thesedeviceswillbestopped.Howeverwhen thesedevicesarewokenupagain, itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelyeithertheLXTorLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntiltheoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunctionisfSUB,theFastWake-upfunctionisonlyavailableintheSLEEP1andIDLE0modes.WhenthesedevicesarewokenupfromtheSLEEP0mode,theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclock,andif theFastWake-upfunctionisenabled,thenitwilltakeonetotwotSUBclockcyclesoftheLIRCorLXToscillatorforthesystemtowake-up.Thesystemwill theninitiallyrununder thefSUBclocksourceuntil1024HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

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IftheERCorHIRCoscillatororLIRCoscillatorisusedasthesystemoscillatorthenitwill take15~16clockcyclesoftheERCorHIRCor1~2cyclesoftheLIRCtowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

System Oscillator

FSTEN Bit

Wake-up Time (SLEEP0 Mode)

Wake-up Time (SLEEP1 Mode)

Wake-up Time (IDLE0 Mode)

Wake-up Time (IDLE1 Mode)

HXT

0 10�4 HXT cycles 10�4 HXT cycles 1~� HXT cycles

1 10�4 HXT cycles1~� fSUB cycles (Syste� �uns with fSUB first fo� 10�4 HXT cycles and then switches ove� to �un with the HXT clock)

1~� HXT cycles

ERC x 15~1� ERC cycles 15~1� ERC cycles 1~� ERC cyclesHIRC x 15~1� HIRC cycles 15~1� HIRC cycles 1~� HIRC cyclesLIRC x 1~� LIRC cycles 1~� LIRC cycles 1~� LIRC cyclesLXT x 10�4 LTX cycles 10�4 LXT cycles 1~� LXT cycles

Wake-Up Times

NotethatiftheWatchdogTimerisdisabled,whichmeansthattheLXTandLIRCareallbothoff,thentherewillbenoFastWake-upfunctionavailablewhenthesedeviceswake-upfromtheSLEEP0Mode.

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Operating Mode SwitchingThesedevicescanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthesedevicesentertheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheWDTCregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfL.IftheclockisfromthefL,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofotherinternalfunctionssuchastheTMsandtheSIM.Theaccompanyingflowchartshowswhathappenswhenthesedevicesmovebetweenthevariousoperatingmodes.

NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto“0”andsettheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

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SLOW Mode to NORMAL Mode SwitchingInSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

Entering the SLEEP0 ModeThereisonlyonewayforthesedevicestoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstoppednomatteriftheWDTclocksourceoriginatesfromthefSUBclockorfromthesystemclock.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

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Entering the SLEEP1 ModeThereisonlyonewayforthesedevicestoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTorLVDon.When this instruction isexecutedunder theconditionsdescribedabove, thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefSUBclock.


• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefromthefSUBclockastheWDTisenabled.



Entering the IDLE0 ModeThereisonlyonewayforthesedevicestoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinWDTCregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheTimeBaseclockandfSUBclockwillbeon.


• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefromthefSUBclockandtheWDTisenabled.TheWDTwillstopifitsclocksourceoriginatesfromthesystemclock.



Entering the IDLE1 ModeThereisonlyonewayforthesedevicestoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinWDTCregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.


• TheWDTwillbeclearedandresumecountingif theWDTisenabledregardlessoftheWDTclocksourcewhichoriginatesfromthefSUBclockorfromthesystemclock.



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Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthesedevicestoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode, thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesigner if thepowerconsumptionis tobeminimised.SpecialattentionmustbemadetotheI/Opinsonthesedevices.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredif theconfigurationoptionshaveenabledtheLXTorLIRCoscillator.

In theIDLE1Mode thesystemoscillator ison, if thesystemoscillator is fromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• Anexternalreset

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

Ifthesystemiswokenupbyanexternalreset, thesedeviceswillexperienceafullsystemreset,however, if thesedevicesarewokenupbyaWDToverflow,aWatchdogTimer resetwillbeinitiated.Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthewake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe“HALT”instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthesedeviceswillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterrupt isenabledandthestack isnotfull, inwhichcase theregular interruptresponse takesplace. IfaninterruptrequestflagissethighbeforeenteringtheSLEEPorIDLEMode,thewake-upfunctionoftherelatedinterruptwillbedisabled.

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Programming ConsiderationsTheHXTandLXToscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandboththeHXTandLXToscillatorsneedtostart-upfromanoffstate.TheLXToscillatorusestheSSTcounterafterHXToscillatorhasfinisheditsSSTperiod.

• IfthesedevicesarewokenupfromtheSLEEP0ModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.Thesedeviceswillexecutefirst instructionafterHTOis“1”.Atthistime,theLXToscillatormaynotbestabilityiffSUB isfromLXToscillator.Thesamesituationoccursinthepower-onstate.TheLXToscillatorisnotreadyyetwhenthefirstinstructionisexecuted.

• IfthesedevicesarewokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLXTorLIRCoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasWDT,TMsandSIM,forwhichthefSYS isused.If thesystemclocksource is switched fromfH to fL, theclocksource to theperipheral functionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBandfSdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceisselectedfromfSUB.

Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fS,whichisinturnsuppliedbyoneoftwosourcesselectedbyconfigurationoption:fSUBorfSYS/4.ThefSUBclockcanbesourcedfromeither theLXTorLIRCoscillators,againchosenviaaconfigurationoption.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.

However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.TheotherWatchdogTimerclocksourceoption is thefSYS/4clock.TheWatchdogTimerclocksourcecanoriginatefromitsowninternalLIRCoscillator,theLXToscillatororfSYS/4.Itisdividedbyavalueof28to215,usingtheWS2~WS0bitsintheWDTCregistertoobtaintherequiredWatchdogTimertime-outperiod.

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Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.ThisregistertogetherwithseveralconfigurationoptionscontroltheoveralloperationoftheWatchdogTimer.

WDTC Register

Bit 7 � 5 4 � � 1 0�a�e FSYSO� WS� WS1 WS0 WDTE�� WDTE�� WDTE�1 WDTE�0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 1 1 1 0 1 0

Bit7 FSYSON:fSYSControlinIDLEMode0:Disable1:Enable

Bit6~4 WS2, WS1, WS0:WDTtime-outperiodselection000:256/fS

001:512/fS

010:1024/fS

011:2048/fS

100:4096/fS

101:8192/fS

110:16384/fS

111:32768/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

Bit3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDTSoftwareControl1010:DisableOther:Enable

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Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunkownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.SomeoftheWatchdogTimeroptions,suchasenable/disable,clocksourceselectionandclearinstructiontypeareselectedusingconfigurationoptions.Inadditiontoaconfigurationoptiontoenable/disabletheWatchdogTimer,therearealsofourbits,WDTEN3~WDTEN0,intheWDTCregistertoofferanadditionalenable/disablecontrolof theWatchdogTimer.TodisabletheWatchdogTimer,aswellastheconfigurationoptionbeingsettodisable, theWDTEN3~WDTEN0bitsmustalsobesettoaspecificvalueof"1010".AnyothervaluesforthesebitswillkeeptheWatchdogTimerenabled,irrespectiveoftheconfigurationenable/disablesetting.Afterpoweronthesebitswillhavethevalueof1010.IftheWatchdogTimerisuseditisrecommendedthattheyaresettoavalueof0101formaximumnoiseimmunity.NotethatiftheWatchdogTimerhasbeendisabled,thenanyinstructionrelatingtoitsoperationwillresultinnooperation.

WDT Configuration Option WDTEN3~WDTEN0 Bits WDTWDT Ena�le xxxx Ena�leWDT Disa�le Except 1010 Ena�leWDT Disa�le 1010 Disa�le

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.Thefirstisanexternalhardwarereset,whichmeansalowlevelontheRESpin,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthethirdisviaaHALTinstruction.

TherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhichmustbechosenbyconfigurationoption.Thefirstoptionistousethesingle"CLRWDT"instructionwhilethesecondistousethetwocommands"CLRWDT1"and"CLRWDT2".Forthefirstoption,asimpleexecutionof"CLRWDT"willclear theWDTwhilefor thesecondoption,both"CLRWDT1"and"CLRWDT2"mustbothbeexecutedalternatelytosuccessfullycleartheWatchdogTimer.Note that for thissecondoption, if"CLRWDT1" isused toclear theWatchdogTimer,successiveexecutionsofthisinstructionwillhavenoeffect,onlytheexecutionofa"CLRWDT2"instructionwillclear theWatchdogTimer.Similarlyafter the"CLRWDT2"instructionhasbeenexecuted,onlyasuccessive"CLRWDT1"instructioncancleartheWatchdogTimer.

Themaximumtimeoutperiod iswhenthe215divisionratio isselected.Asanexample,witha32.768kHzLXToscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround1secondforthe215divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.IfthefSYS/4clockisusedastheWatchdogTimerclocksource, itshouldbenotedthatwhenthesystementerstheSLEEPorIDLE0Mode,thentheinstructionclockisstoppedandtheWatchdogTimermaylose itsprotectingpurposes.Forsystemsthatoperate innoisyenvironments,usingthefSUBclocksourceisstronglyrecommended.

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Watchdog Timer

Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

Inadditiontothepower-onreset,situationsmayarisewhereit isnecessarytoforcefullyapplyaresetconditionwhenthe isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandtheisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof the registersremainunchangedallowing the toproceedwithnormaloperationaftertheresetlineisallowedtoreturnhigh.

Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresult indifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset,similartotheRESresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsThereare fiveways inwhichamicrocontroller resetcanoccur, througheventsoccurringbothinternallyandexternally:

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.

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Note:tRSTDispower-ondelay,typicaltime=100ms

Power-on Reset Timing Chart

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RES PinAstheresetpin issharedwithPB.0, the reset functionmustbeselectedusingaconfigurationoption.AlthoughthemicrocontrollerhasaninternalRCresetfunction, if theVDDpowersupplyrise timeisnotfastenoughordoesnotstabilisequicklyatpower-on, the internalresetfunctionmaybeincapableofprovidingproperresetoperation.For thisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationofthemicrocontrollerwillbeinhibited.AftertheRESlinereachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.

FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.AnywiringconnectedtotheRESpinshouldbekeptasshortaspossibletominimiseanystraynoiseinterference.

ForapplicationsthatoperatewithinanenvironmentwheremorenoiseispresenttheEnhancedResetCircuitshownisrecommended.

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Note:*ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.

**Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

Extern RES Circuit

MoreinformationregardingexternalresetcircuitsislocatedinApplicationNoteHA0075EontheHoltekwebsite.

PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.

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RES Reset Timing Chart

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Low Voltage Reset – LVRThesemicrocontrollerscontaina lowvoltageresetcircuit inorder tomonitor thesupplyvoltageofthesedevices,whichareselectedviaaconfigurationoption.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternally.TheLVRincludesthefollowingspecifications:ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheA.C.characteristics.IfthelowvoltagestatedoesnotexceedtLVR,theLVRwillignoreitandwillnotperformaresetfunction.OneofarangeofspecifiedvoltagevaluesforVLVRcanbeselectedusingconfigurationoptions.

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Low Voltage Reset Timing Chart

Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outResetduringnormaloperation is thesameasahardwareRESpinresetexceptthattheWatchdogtime-outflagTOwillbesetto“1”.

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WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

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Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbyERCorHIRC.ThetSSTis1024clockforHXTorLXT.ThetSSTis1~2clockforLIRC.

WDT Time-out Reset during SLEEP or IDLE Timing Chart

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Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF RESET Conditions0 0 Powe�-on �esetu u RES o� LVR �eset du�ing �ORMAL o� SLOW Mode ope�ation1 u WDT ti�e-out �eset du�ing �ORMAL o� SLOW Mode ope�ation1 1 WDT ti�e-out �eset du�ing IDLE o� SLEEP Mode ope�ation

“u” stands fo� unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition After RESETP�og�a� Counte� Reset to ze�oInte��upts All inte��upts will �e disa�ledWDT Clea� afte� �eset� WDT �egins countingTi�e�/Event Counte� Ti�e� Counte� will �e tu�ned offInput/Output Po�ts I/O po�ts will �e setup as inputs� and A�0~A�7 is as A/D input pin.Stack Pointe� Stack Pointe� will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

HT66F20-1

Register Reset(Power-on) RES or LVR Reset WDT Time-out

(Normal Operation)WDT Time-out

(IDLE)MP0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP1 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBHP - - - - - - x x - - - - - - u u - - - - - - u u - - - - - - u uSTATUS - - 0 0 x x x x - - u u u u u u - - 1u uuuu - - 1 1 u u u uSMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uI�TEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uWDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 u u u u u u u uTBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u uI�TC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uI�TC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uI�TC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

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Register Reset(Power-on) RES or LVR Reset WDT Time-out

(Normal Operation)WDT Time-out

(IDLE)MFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPB - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPBC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPCPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPCC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uADRL(ADREF=0) x x x x - - - - x x x x - - - - x x x x - - - - u u u u - - - -ADRL(ADREF=1) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH(ADREF=0) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH(ADREF=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u uADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 u u u u - u u uADCR1 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 u u - u - u u uACERL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uCP0C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uCP1C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uSIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - u u u u u u u -SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u uSIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSIMA/SIMC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uEEA - - - x xxxx - - - x xxxx - - - x xxxx - - - 0 0000EED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uTMPC0 - - 0 1 - - - 1 - - 0 1 - - - 1 - - 0 1 - - - 1 - - u u - - - uTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSCOMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Note:"u"standsforunchanged“x”standsforunknown“-”standsforunimplemented

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HT66F30-1 Register

Register Reset(Power-on)

RES or LVR Reset

WDT Time-out(Normal Operation)

WDT Time-out(IDLE)

MP0 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uMP1 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBHP - - - - - x x x - - - - - u u u - - - - - u u u - - - - - u u uSTATUS - - 0 0 x x x x - - u u u u u u - - 1 u u u u u - - 1 1 u u u uSMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uI�TEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uWDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 u u u u u u u uTBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u uI�TC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uI�TC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uI�TC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI1 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u uMFI� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPB - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPBC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPCPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uADRL(ADREF=0) x x x x - - - - x x x x - - - - x x x x - - - - u u u u - - - - ADRL(ADREF=1) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH(ADREF=0) x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uADRH(ADREF=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - u u u uADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 u u u u - u u uADCR1 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 0 u u - u - u u uACERL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uCP0C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uCP1C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uSIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - u u u u u u u -SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u uSIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSIMA/SIMC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

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RES or LVR Reset


WDT Time-out(IDLE)

TM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uEEA - - x x x x x x - - x x x x x x - - x x x x x x - - u u u u u uEED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uTMPC0 1 - 0 1 - - 0 1 1 - 0 1 - - 0 1 1 - 0 1 - - 0 1 u - u u - - u uPRM0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1BL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1BH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSCOMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Note:“-”standsfornotimplement

“u”standsforunchanged

“x”standsforunknown

HT68F20-1


RES or LVR Reset


WDT Time-out(IDLE)

MP0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uMP1 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBHP - - - - - - x x - - - - - - u u - - - - - - u u - - - - - - u uSTATUS - - 0 0 x x x x - - u u u u u u - - 1 u u u u u - - 1 1 u u u uSMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uI�TEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uWDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 u u u u u u u uTBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u uI�TC0 - 000 0000 - 000 0000 - 000 0000 - uuu uuuuI�TC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uI�TC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Rev. 1.40 �8 �ove��e� �� 01� Rev. 1.40 �9 �ove��e� �� 01�




RES or LVR Reset


WDT Time-out(IDLE)

PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPB - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPBC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPCPU - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uPC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uPCC - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - 1 1 1 1 - - - - u u u uCP0C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uCP1C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uSIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - u u u u u u u -SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u uSIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSIMA/SIMC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uEEA - - - x x x x x - - - x x x x x - - - x x x x x - - - 0 0000EED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uTMPC0 - - 0 1 - - - 1 - - 0 1 - - - 1 - - 0 1 - - - 1 - - u u - - - uTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSCOMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Note:"u"standsforunchanged"x"standsforunknown"–"standsforunimplemented

Rev. 1.40 �8 �ove��e� �� 01� Rev. 1.40 �9 �ove��e� �� 01�



HT68F30-1 Register


RES or LVR Reset


WDT Time-out(IDLE)

MP0 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uMP1 x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uBP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - uACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uPCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u uTBHP - - - - - x x x - - - - - u u u - - - - - u u u - - - - - u u uSTATUS - - 0 0 x x x x - - u u u u u u - - 1 u u u u u - - 1 1 u u u uSMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 u u u u u u u uLVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u uI�TEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uWDTC 0 111 1 0 1 0 0 111 1 0 1 0 0 111 1 0 1 0 u u u u u u u uTBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 u u u u u u u uI�TC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u uI�TC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uI�TC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uMFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u uMFI1 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u uMFI� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPBPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u uPB - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPBC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - u u u u u uPCPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uPCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u uCP0C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uCP1C 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 1 0 0 0 0 - - 1 u u u u u - - uSIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - u u u u u u u -SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u uSIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uSIMA/SIMC� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM0AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uEEA - - x x x x x x - - x x x x x x - - x x x x x x - - u u u u u uEED x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u uEEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u uTMPC0 1 - 0 1 - - 0 1 1 - 0 1 - - 0 1 1 - 0 1 - - 0 1 u - u u - - u u

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RES or LVR Reset


WDT Time-out(IDLE)

PRM0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u uTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1C� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uTM1BL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u uTM1BH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u uSCOMC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

Note:“-”standsfornotimplement

“u”standsforunchanged

“x”standsforunknown

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Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thesedevicesprovidebidirectionalinput/outputlineslabeledwithportnamesPA~PCTheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

I/O Port Register List

HT66F20-1/HT68F20-1 Register

Register Name

Bit

7 6 5 4 3 2 1 0PAWU PAWU7 PAWU � PAWU5 PAWU4 PAWU� PAWU� PAWU1 PAWU0PAPU PAPU7 PAPU� PAPU5 PAPU4 PAPU� PAPU� PAPU1 PAPU0

PA PA7 PA� PA5 PA4 PA� PA� PA1 PA0PAC PAC7 PAC� PAC5 PAC4 PAC� PAC� PAC1 PAC0

PBPU ― ― PBPU5 PBPU4 PBPU� PBPU� PBPU1 PBPU0PB — — PB5 PB4 PB� PB� PB1 PB0

PBC — — PBC5 PBC4 PBC� PBC� PBC1 PBC0PCPU — — — — PCPU� PCPU� PCPU1 PCPU0

PC — — — — PC� PC� PC1 PC0PCC — — — — PCC� PCC� PCC1 PCC0

HT66F30-1/HT68F30-1 Register

Register Name

Bit

7 6 5 4 3 2 1 0PAWU PAWU7 PAWU � PAWU5 PAWU4 PAWU� PAWU� PAWU1 PAWU0PAPU PAPU7 PAPU� PAPU5 PAPU4 PAPU� PAPU� PAPU1 PAPU0

PA PA7 PA� PA5 PA4 PA� PA� PA1 PA0PAC PAC7 PAC� PAC5 PAC4 PAC� PAC� PAC1 PAC0

PBPU — — PBPU5 PBPU4 PBPU� PBPU� PBPU1 PBPU0PB — — PB5 PB4 PB� PB� PB1 PB0

PBC — — PBC5 PBC4 PBC� PBC� PBC1 PBC0PCPU PCPU7 PCPU� PCPU5 PCPU4 PCPU� PCPU� PCPU1 PCPU0

PC PC7 PC� PC5 PC4 PC� PC� PC1 PC0PCC PCC7 PCC� PCC5 PCC4 PCC� PCC� PCC1 PCC0

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Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregisters,namelyPAPU~PCPU,andareimplementedusingweakPMOStransistors.

PAPU Register

Bit 7 6 5 4 3 2 1 0�a�e PAPU7 PAPU� PAPU5 PAPU4 PAPU� PAPU� PAPU1 PAPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

PBPU Register

Bit 7 6 5 4 3 2 1 0�a�e — — PBPU5 PBPU4 PBPU� PBPU� PBPU1 PBPU0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

PCPU Register

• HT66F20-1/HT68F20-1

Bit 7 6 5 4 3 2 1 0�a�e PCPU7 PCPU� PCPU5 PCPU4 PCPU� PCPU� PCPU1 PCPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — — — — PCPU� PCPU� PCPU1 PCPU0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~6 “—” Unimplemented,readas“0” PAPUn/PBPUn/PCPUn:Pull-highfunctioncontrol

0:disable 1:enable

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Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

PAWU Register

Bit 7 6 5 4 3 2 1 0�a�e PAWU7 PAWU� PAWU5 PAWU4 PAWU� PAWU� PAWU1 PAWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PortAwake-upcontrol 0:Disable 1:Enable

I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PCC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PAC Register

Bit 7 6 5 4 3 2 1 0�a�e PAC7 PAC� PAC5 PAC4 PAC� PAC� PAC1 PAC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

PBC Register

Bit 7 6 5 4 3 2 1 0�a�e — — PBC5 PBC4 PBC� PBC� PBC1 PBC0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 1 1 1 1 1 1

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PCC Register• HT66F20-1/HT68F20-1

Bit 7 6 5 4 3 2 1 0�a�e — — — — PCC� PCC� PCC1 PCC0R/W — — — — R/W R/W R/W R/WPOR — — — — 1 1 1 1

• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e PCC7 PCC� PCC5 PCC4 PCC� PCC� PCC1 PCC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~6 “—”:Unimplemented,readas“0” PACn/PBCn/PCCn:I/Otypeselection

0:output 1:input

Pin-remapping FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyof thesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremorethanonepinfunctionisselectedsimultaneously.Additionally there isaPRM0registertoestablishcertainpinfunctions.Thispin-remappingfunctionisonlyavailablefortheHT66F30-1andHT68F30-1devices.

Pin-remapping RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.ThedevicesincludeaPRM0registerwhichcanselectthefunctionsofcertainpins.TheHT66F30-1andHT68F30-1devicesincludeaPRM0registerwhichcanselectthefunctionsofcertainpins.

PRM0 Register – HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — — — — — PCPRM SIMPS0 PCKPSR/W — — — — — R/W R/W R/WPOR — — — — — 0 0 0

Bit7~3 Unimplemented,readas“0”Bit2 PCPRM:PC1~PC0pin-sharedfunctionPinRemappingControl

0:Nochange 1:TP1B_0onPC0changetoPA6,TP1B_1onPC1changetoPA7ifSIMPS0=1

Bit1 SIMPS0:SIMPinRemappingControl 0:SDOonPA5;SDI/SDAonPA6;SCK/SCLonPA7;SCSonPB5 1:SDOonPC1;SDI/SDAonPC0;SCK/SCLonPC7;SCSonPC6

Bit0 PCKPS:PCKandPINTPinRemappingControl 0:PCKonPC2;PINTonPC3 1:PCKonPC5;PINTonPC4

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I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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A/D Input/Output Structure

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Programming ConsiderationsWithintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PCC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PC,arefirstprogrammed.Selectingwhichpinsare inputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdevicesistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeing the functionalunit for thegenerationofPWMsignals.Eachof theTMshaseithermultipleinterrupts.TheadditionofinputandoutputpinsforeachTMensuresthatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualCompactandEnhancedTMsections.

IntroductionThedevicescontain twoTMshavingareferencenameofTM0andTM1.Each individualTMcanbecategorisedasacertaintype,namelyCompactTypeTM,StandardTypeTMorEnhancedTypeTM.Althoughsimilar innature, thedifferentTMtypesvary in their featurecomplexity.Thecommonfeatures toallof theCompact,StandardandEnhancedTMswillbedescribed inthissection.ThedetailedoperationregardingeachoftheTMtypeswillbedescribedinseparatesections.ThemainfeaturesanddifferencesbetweenthethreetypesofTMsaresummarisedintheaccompanyingtable.

TM Function CTM STM ETMTi�e�/Counte� √ √ √I/P Captu�e — √ √Co�pa�e Match Output √ √ √PWM Channels 1 1 �Single Pulse Output — 1 �PWM Align�ent Edge Edge Edge & Cent�ePWM Adjust�ent Pe�iod & Duty Duty o� Pe�iod Duty o� Pe�iod Duty o� Pe�iod

TM Function Summary

Rev. 1.40 7� �ove��e� �� 01� Rev. 1.40 77 �ove��e� �� 01�



EachdeviceintheseriescontainsaspecificnumberofCompactType,StandardTypeandEnhancedTypeTMwhichareshowninthetabletogetherwiththeirindividualreferencename,TM0,TM1.

Device TM0 TM1HT��F�0-1/HT�8F�0-1 10-�it CTM 10-�it STMHT��F�0-1/HT�8F�0-1 10-�it CTM 10-�it ETM

TM Name/Type Reference

TM OperationThedifferent typesofTMofferadiverserangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.Theselectionof therequiredclocksourceis implementedusingtheTnCK2~TnCK0bits intheTMncontrolregisters.TheclocksourcecanbearatioofeitherthesystemclockfSYSortheinternalhighclockfH,thefLclocksourceortheexternalTCKnpin.Notethatsettingthesebitstothevalue101willselectanundefinedclockinput, ineffectdisconnectingtheTMclocksource.TheTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheCompactandStandardtypeTMseachhastwointernalinterrupts,oneforeachoftheinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.AstheEnhancedtypeTMhasthreeinternalcomparatorsandcomparatorAorcomparatorBorcomparatorPcomparematchfunctions,itconsequentlyhasthreeinternalinterrupts.WhenaTMinterruptisgenerateditcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

Rev. 1.40 78 �ove��e� �� 01� Rev. 1.40 79 �ove��e� �� 01�



TM External PinsEachoftheTMs,irrespectiveofwhattype,hasoneTMinputpin,withthelabelTCKn.TheTMinputpin,isessentiallyaclocksourcefortheTMandisselectedusingtheTnCK2~TnCK0bitsintheTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThisexternalTMinputpinissharedwithotherfunctionsbutwillbeconnectedtotheinternalTMifselectedusingtheTnCK2~TnCK0bits.TheTMinputpincanbechosentohaveeitherarisingorfallingactiveedge.

TheTMseachhaveoneormoreoutputpinswiththelabelTPn.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalTPnoutputpinisalsothepinwheretheTMgenerates thePWMoutputwaveform.As theTMoutputpinsarepin-sharedwithotherfunction, theTMoutput functionmust firstbesetupusingregisters.Asinglebit inoneof theregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeanddevicesaredifferent,thedetailsareprovidedintheaccompanyingtable.

AllTMoutputpinnameshavea“_n”suffix.Pinnamesthatincludea“_0”or“_1”suffixindicatethattheyarefromaTMwithmultipleoutputpins.ThisallowstheTMtogenerateacomplimentaryoutputpair,selectedusingtheI/Oregisterdatabits.

Device CTM STM ETM RegistersHT��F�0-1 HT�8F�0-1

TCK0TP0_0

TCK1TP1_0� TP1_1 ― TMPC0

HT��F�0-1 HT�8F�0-1

TCK0TP0_0� TP0_1 ― TCK1

TP1A� TP1B_0� TP1B_1 TMPC0

TM Input/Output Pins

TM Input/Output Pin ControlSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunction,isimplementedusingoneortworegisters,withasinglebitineachregistercorrespondingtoaTMinput/outputpin.SettingthebithighwillsetupthecorrespondingpinasaTMinput/output, ifresettozerothepinwillretainitsoriginalotherfunction.

DeviceBit

7 6 5 4 3 2 1 0HT��F�0-1 HT�8F�0-1 — — T1CP1 T1CP0 — — — T0CP0

HT��F�0-1 HT�8F�0-1 T1ACP0 — T1BCP1 T1BCP1 — — T0CP1 T0CP0

TM Input/Output Pin Control Registers List

Rev. 1.40 78 �ove��e� �� 01� Rev. 1.40 79 �ove��e� �� 01�



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HT66F20-1/HT68F20-1 TM Function Pin Control Block Diagram

Note:1.TheI/OregisterdatabitsshownareusedforTMoutputinversioncontrol.

2.IntheCaptureInputMode,theTMpincontrolregistermustneverenablemorethanoneTMinput.

Rev. 1.40 80 �ove��e� �� 01� Rev. 1.40 81 �ove��e� �� 01�



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HT66F30-1/HT68F30-1 TM0 Function Pin Control Block DiagramNote:1.TheI/OregisterdatabitsshownareusedforTMoutputinversioncontrol.


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HT66F30-1/HT68F30-1 TM1 Function Pin Control Block DiagramNote:1.TheI/OregisterdatabitsshownareusedforTMoutputinversioncontrol.


Rev. 1.40 80 �ove��e� �� 01� Rev. 1.40 81 �ove��e� �� 01�



TMPC0 Register• HT66F20-1/HT68F20-1

Bit 7 6 5 4 3 2 1 0�a�e — — T1CP1 T1CP1 — — — T0CP0R/W — — R/W R/W — — — R/WPOR — — 0 1 — — — 1

Bit7~6 “—”Unimplemented,readas“0”Bit5 T1CP1:TP1_1PinControl

0:Disable1:Enable

Bit4 T1CP0:TP1_0PinControl0:Disable1:Enable

Bit3~1 “—”Unimplemented,readas“0”Bit0 T0CP0:TP0_0PinControl

0:Disable1:Enable

• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e T1ACP0 — T1BCP1 T1BCP0 — — T0CP1 T0CP0R/W R/W — R/W R/W — — R/W R/WPOR 1 — 0 1 — — 0 1

Bit7 T1ACP0:TP1ApinControl0:Disable1:Enable

Bit6 Unimplemented,readas"0"Bit5 T1BCP1:TP1B_1pinControl

0:Disable1:Enable

Bit4 T1BCP0:TP1B_0pinControl0:Disable1:Enable

Bit3~2 Unimplemented,readas"0"Bit1 T0CP1:TP0_1pinControl

0:Disable1:Enable

Bit0 T0CP0:TP0_0pinControl0:Disable1:Enable

Rev. 1.40 8� �ove��e� �� 01� Rev. 1.40 8� �ove��e� �� 01�



Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRBregisters,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

Data Bus

8-�it Buffe�

TMxDHTMxDL

TMxBHTMxBL

TMxAHTMxAL

TM Counte� Registe� (Read only)

TM CCRA Registe� (Read/W�ite)

TM CCRB Registe� (Read/W�ite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRBorCCRA♦ Step1.WritedatatoLowByteTMxALorTMxBL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteTMxAHorTMxBH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydataislatchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRBorCCRA♦ Step1.ReaddatafromtheHighByteTMxDH,TMxAHorTMxBH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowByteTMxDL,TMxALorTMxBL– Thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.40 8� �ove��e� �� 01� Rev. 1.40 8� �ove��e� �� 01�



Compact Type TM – CTMAlthoughthesimplestformofthetwoTMtypes,theCompactTMtypestillcontainsthreeoperatingmodes,whichareCompareMatchOutput,Timer/EventCounterandPWMOutputmodes.TheCompactTMcanalsobecontrolledwithanexternalinputpinandcandriveoneortwoexternaloutputpins.Thetwoexternaloutputpinscanbethesamesignalortheinversesignal.

Device TM Type TM Name TM Input Pin TM Output PinHT��F�0-1/HT�8F�0-1 10-�it CTM TM0 TCK0 TP0_0HT��F�0-1/HT�8F�0-1 10-�it CTM TM0 TCK0 TP0_0� TP0_1

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Compact Type TM Block Diagram (n=0)

Compact TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcompare thevalue in thecounterwithCCRPandCCRAregisters.TheCCRPisthreebitswidewhosevalueiscomparedwiththehighestthreebitsinthecounterwhiletheCCRAisthetenbitsandthereforecompareswithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theT0ONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheCompactTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 84 �ove��e� �� 01� Rev. 1.40 85 �ove��e� �� 01�



Compact Type TM Register DescriptionOveralloperationof theCompactTMiscontrolledusingsixregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.Theremaining tworegistersarecontrol registerswhichsetup thedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TM0C0 T0PAU T0CK� T0CK1 T0CK0 T0O� T0RP� T0RP1 T0RP0TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLRTM0DL D7 D� D5 D4 D� D� D1 D0TM0DH — — — — — — D9 D8TM0AL D7 D� D5 D4 D� D� D1 D0TM0AH — — — — — — D9 D8

Compact TM Register List

TM0DL Register

Bit 7 6 5 4 3 2 1 0�a�e D7 D� D5 D4 D� D� D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 TM0DL:TM0CounterLowByteRegisterbit7~bit0TM010-bitCounterbit7~bit0

TM0DH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM0DH:TM0CounterHighByteRegisterbit1~bit0

TM010-bitCounterbit9~bit8

TM0AL Register

Bit 7 6 5 4 3 2 1 0�a�e D7 D� D5 D4 D� D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 TM0AL:TM0CCRALowByteRegisterbit7~bit0TM010-bitCCRAbit7~bit0

TM0AH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM0AH:TM0CCRAHighByteRegisterbit1~bit0

TM010-bitCCRAbit9~bit8

Rev. 1.40 84 �ove��e� �� 01� Rev. 1.40 85 �ove��e� �� 01�



TM0C0 Register

Bit 7 6 5 4 3 2 1 0�a�e T0PAU T0CK� T0CK1 T0CK0 T0O� T0RP� T0RP1 T0RP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 T0PAU:TM0CounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 T0CK2~T0CK0:SelectTM0Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:Undefined110:TCK0risingedgeclock111:TCK0fallingedgeclock

These threebits areused to select theclock source for theTM0.Selecting theReservedclockinputwilleffectivelydisable the internalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 T0ON:TM0CounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheTM0.Settingthebithighenablesthecounter torun,clearingthebitdisables theTM0.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theTM0whichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwill retain its residualvalue. If theTM0is in theCompareMatchOutputModethentheTM0outputpinwillberesettoitsinitialcondition,asspecifiedbytheT0OCbit,whentheT0ONbitchangesfromlowtohigh.

Bit2~0 T0RP2~T0RP0:TM0CCRP3-bitregister,comparedwiththeTM0Counterbit9~bit7ComparatorPMatchPeriod000:1024TM0clocks001:128TM0clocks010:256TM0clocks011:384TM0clocks100:512TM0clocks101:640TM0clocks110:768TM0clocks111:896TM0clocks

ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT0CCLRbit isset tozero.SettingtheT0CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.40 8� �ove��e� �� 01� Rev. 1.40 87 �ove��e� �� 01�



TM0C1 Register

Bit 7 6 5 4 3 2 1 0�a�e T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T0M1~T0M0:SelectTM0OperatingMode00:CompareMatchOutputMode01:Undefined10:PWMMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheT0M1andT0M0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T0IO1~T0IO0:SelectTP0_0,TP0_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Undefined

Timer/counterModeunused

ThesetwobitsareusedtodeterminehowtheTM0outputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTM0isrunning.IntheCompareMatchOutputMode,theT0IO1andT0IO0bitsdeterminehowtheTM0outputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTM0outputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTM0outputpinshouldbesetupusingtheT0OCbit intheTM0C1register.NotethattheoutputlevelrequestedbytheT0IO1andT0IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT0OCbitotherwisenochangewilloccurontheTM0outputpinwhenacomparematchoccurs.AftertheTM0outputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT0ONbitfromlowtohigh.In thePWMMode, theT0IO1andT0IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunction ismodifiedbychanging these twobits. It isnecessary toonlychangethevaluesof theT0IO1andT0IO0bitsonlyafter theTM0hasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT0IO1andT0IO0bitsarechangedwhentheTMisrunning.

Rev. 1.40 8� �ove��e� �� 01� Rev. 1.40 87 �ove��e� �� 01�



Bit3 T0OC:TP0_0,TP0_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTM0outputpin. ItsoperationdependsuponwhetherTM0isbeingusedintheCompareMatchOutputModeorinthePWMMode.Ithasnoeffect if theTM0 is in theTimer/CounterMode. In theCompareMatchOutputModeitdetermines the logic levelofheTM0outputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesif thePWMsignal isactivehighoractivelow.

Bit2 T0POL:TP0_0,TP0_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP0_0orTP0_1outputpin.Whenthebit issethightheTM0outputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTM0isintheTimer/CounterMode.

Bit1 T0DPX:TM0PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 T0CCLR:SelectTM0Counterclearcondition0:TM0ComparatorPmatch1:TM0ComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theCompactTM0containstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT0CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT0CCLRbitisnotusedinthePWMMode.

Compact Type TM Operating ModesTheCompactTypeTMcanoperateinoneofthreeoperatingmodes,CompareMatchOutputMode,PWMModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheT0M1andT0M0bitsintheTM0C1register.

Compare Match Output ModeToselectthismode,bitsT0M1andT0M0intheTM0C1register,shouldbesetto“00”respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheT0CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothT0AFandT0PFinterruptrequestflagsfortheComparatorAandComparatorPrespectively,willbothbegenerated.

Rev. 1.40 88 �ove��e� �� 01� Rev. 1.40 89 �ove��e� �� 01�



IftheT0CCLRbitintheTM0C1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theT0AFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenT0CCLRishighnoT0PFinterruptrequestflagwillbegenerated.IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,value,howeverheretheT0AFinterruptrequestflagwillnotbegenerated.

As thenameof themodesuggests,afteracomparison ismade, theTMoutputpinwillchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaT0AFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheT0PFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theT0IO1andT0IO0bitsintheTM0C1register.TheTMoutputpincanbeselectedusingtheT0IO1andT0IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theT0ONbitchangesfromlowtohigh,issetupusingtheT0OCbit.NotethatiftheT0IO1andT0IO0bitsarezerothennopinchangewilltakeplace.

Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRP=0

CCRP > 0

Counte� ove�flowCCRP > 0Counte� clea�ed �y CCRP value

Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnM [1:0] = 00

Output pin set to initial Level Low if TnOC=0

Output Toggle with TnAF flag

�ote TnIO [1:0] = 10 Active High Output selectHe�e TnIO [1:0] = 11

Toggle Output select

Output not affected �y TnAF flag. Re�ains High until �eset �y TnO� �it

Output PinReset to Initial value

Output cont�olled �y othe� pin-sha�ed function

Output Inve�tswhen TnPOL is high

Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=0

Rev. 1.40 88 �ove��e� �� 01� Rev. 1.40 89 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRA=0

CCRA = 0Counte� ove�flowCCRA > 0 Counte� clea�ed �y CCRA value

Pause

Resu�e

Stop Counte� Resta�t

TnCCLR = 1; TnM [1:0] = 00









TnPF not gene�ated

�o TnAF flag gene�ated on CCRA ove�flow

Output does not change


Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.TheTnPFflagisnotgeneratedwhenTnCCLR=15.n=0

Rev. 1.40 90 �ove��e� �� 01� Rev. 1.40 91 �ove��e� �� 01�



Timer/Counter ModeToselectthismode,bitsT0M1andT0M0intheTM0C1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsT0M1andT0M0intheTM0C1registershouldbesetto10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, theT0CCLRbithasnoeffectonthePWMoperation.Bothof theCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycle isdeterminedusing theT0DPXbit in theTM0C1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheT0OCbitintheTM0C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoT0IO1andT0IO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheT0POLbitisusedtoreversethepolarityofthePWMoutputwaveform.

CTM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �5� �84 51� �40 7�8 89� 10�4Duty CCRA

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,

TheCTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

CTM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 1�8 �5� �84 51� �40 7�8 89� 10�4

ThePWMoutputperiod isdeterminedbytheCCRAregistervalue togetherwith theTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.40 90 �ove��e� �� 01� Rev. 1.40 91 �ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� clea�ed �y CCRP

Pause Resu�e Counte� Stop if TnO� �it low

Counte� Reset when TnO� �etu�ns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle set �y CCRA

PWM �esu�es ope�ation

Output cont�olled �y othe� pin-sha�ed function Output Inve�ts

when TnPOL = 1PWM Pe�iod set �y CCRP

TM O/P Pin(TnOC=0)

PWM Mode – TnDPX=0

Note:1.HereTnDPX=0–CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0

Rev. 1.40 9� �ove��e� �� 01� Rev. 1.40 9� �ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� clea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cycle set �y CCRP



when TnPOL = 1PWM Pe�iod set �y CCRA

TM O/P Pin(TnOC=0)


Note:1.HereTnDPX=1–CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=0

Rev. 1.40 9� �ove��e� �� 01� Rev. 1.40 9� �ove��e� �� 01�



Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithanexternalinputpinandcandrivetwoexternaloutputpins.TheStandardTypeTMisonlycontainedintheHT66F20-1andHT68F20-1devices.

Device TM Type TM Name TM Input Pin TM Output PinHT��F�0-1/HT�8F�0-1 10-�it STM TM1 TCK1 TP1_0� TP1_1HT��F�0-1/HT�8F�0-1 ― ― ― ―

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HT66F20-1/HT68F20-1 Standard Type TM Block Diagram (n=1)

Standard TM OperationAtthecoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealso twointernalcomparatorswith thenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris3-bitwidewhosevalueiscomparedthewithhighest3bitsinthecounterwhiletheCCRAisthetenorsixteenbitsandthereforecomparesallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theTnONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 94 �ove��e� �� 01� Rev. 1.40 95 �ove��e� �� 01�



Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitCCRAvalue.TheremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TM1C0 T1PAU T1CK� T1CK1 T1CK0 T1O� T1RP� T1RP1 T1RP0TM1C1 T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLRTM1DL D7 D� D5 D4 D� D� D1 D0TM1DH D15 D14 D1� D1� D11 D10 D9 D8TM1AL D7 D� D5 D4 D� D� D1 D0TM1AH D15 D14 D1� D1� D11 D10 D9 D8

10-bit Standard TM Register List – HT66F20-1/HT68F20-1

TM1C0 Register




Bit6~4 T1CK2,T1CK1, T1CK0:SelectTM1Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:Undefined110:TCKnrisingedgeclock111:TCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYS isthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.


Thisbitcontrolstheoverallon/offfunctionoftheTM.Settingthebithighenablesthecountertorun,clearingthebitdisablestheTM.ClearingthisbittozerowillstopthecounterfromcountingandturnofftheTMwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillberesettozero,howeverwhenthebitchangesfromhightolow,theinternalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT1OCbit,whentheT1ONbitchangesfromlowtohigh.

Rev. 1.40 94 �ove��e� �� 01� Rev. 1.40 95 �ove��e� �� 01�




ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter'shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT1CCLRbit isset tozero.SettingtheT1CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

TM1C1 Register

Bit 7 6 5 4 3 2 1 0�a�e T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1M1~T1M0:SelectTM1OperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremadetotheT1M1andT1M0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1IO1~T1IO0:SelectTP1_0,TP1_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMoutputinactivestate01:PWMoutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1_0,TP1_101:InputcaptureatfallingedgeofTP1_0,TP1_110:Inputcaptureatfalling/risingedgeofTP1_0,TP1_111:Inputcapturedisabled

Timer/counterMode:Unused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.

Rev. 1.40 9� �ove��e� �� 01� Rev. 1.40 97 �ove��e� �� 01�



IntheCompareMatchOutputMode,theT1IO1andT1IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1OCbit intheTM1C1register.NotethattheoutputlevelrequestedbytheT1IO1andT1IO0bitsmustbedifferentfromtheinitialvaluesetupusingtheT1OCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.In thePWMMode, theT1IO1andT1IO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.It isnecessarytochangethevaluesoftheT1IO1andT1IO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theT1IO1andT1IO0bitsarechangedwhentheTMisrunning.

Bit3 T1OC:TP1_0,TP1_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTMisbeingusedintheCompareMatchOutputModeorinthePWMMode/SinglePulseOutputMode.IthasnoeffectiftheTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheTMoutputpinbeforeacomparematchoccurs.InthePWMModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 TnPOL:TP1_0,TP1_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1_0orTP1_1outputpin.Whenthebit issethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T1DPX:TM1PWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 T1CCLR:SelectTM1Counterclearcondition0:TM1ComparatrorPmatch1:TM1ComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear the internalcounter.With theT1CCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.40 9� �ove��e� �� 01� Rev. 1.40 97 �ove��e� �� 01�



TMnDL Register



TMnDH Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 TM1DH:TM1CounterHighByteRegisterbit1~bit0


TMnAL Register



TMnAH Register


Bit7~2 Unimplemented,readas“0”Bit1~0 TM1AH:TM1CCRAHighByteRegisterbit1~bit0


Rev. 1.40 98 �ove��e� �� 01� Rev. 1.40 99 �ove��e� �� 01�



Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheT1M1andT1M0bitsintheTM1C1register.

Compare Match Output ModeToselectthismode,bitsT1M1andT1M0intheTM1C1register,shouldbesetto00respectively.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheT1CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP, theotheriswhentheCCRPbitsareallzerowhichallowsthecounter tooverflow.HerebothT1AFandT1PFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheT1CCLRbitintheTM1C1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theT1AFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenT1CCLRishighnoT1PFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto"0".

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenanT1AFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheT1PFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheTMoutputpin.Thewayinwhich theTMoutputpinchangesstatearedeterminedby theconditionof theT1IO1andT1IO0bitsintheTM1C1register.TheTMoutputpincanbeselectedusingtheT1IO1andT1IO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof theTMoutputpin,which issetupafter theT1ONbitchangesfromlowtohigh,issetupusingtheT1OCbit.NotethatiftheT1IO1andT1IO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.40 98 �ove��e� �� 01� Rev. 1.40 99 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRP=0

CCRP > 0


Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnM [1:0] = 00










Note:1.WithTnCCLR=0,aComparatorPmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.n=1

Rev. 1.40 100 �ove��e� �� 01� Rev. 1.40 101 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin

Ti�e

CCRA=0


Pause

Resu�e


TnCCLR = 1; TnM [1:0] = 00













Note:1.WithTnCCLR=1,aComparatorAmatchwillclearthecounter2.TheTMoutputpiniscontrolledonlybytheTnAFflag3.TheoutputpinisresettoitsinitialstatebyaTnONbitrisingedge4.ATnPFflagisnotgeneratedwhenTnCCLR=15.n=1

Rev. 1.40 100 �ove��e� �� 01� Rev. 1.40 101 �ove��e� �� 01�



Timer/Counter ModeToselectthismode,bitsT1M1andT1M0intheTM1C1registershouldbesetto11respectively.TheTimer/CounterModeoperates in an identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpin isnotused.Therefore theabovedescriptionandTimingDiagramsfor theCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsT1M1andT1M0intheTM1C1registershouldbesetto10respectivelyandalso theT1IO1andT1IO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible. In thePWMmode, theT1CCLRbithasnoeffectas thePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheT1DPXbitintheTM1C1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheT1OCbitintheTM1C1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoT1IO1andT1IO0bitsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheT1POLbitisusedtoreversethepolarityofthePWMoutputwaveform.

10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �5� �84 51� �40 7�8 89� 10�4Duty CCRA

IffSYS=12MHz,TMclocksourceselectfSYS/4,CCRP=100b,CCRA=128

TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=5.8594kHz,duty=128/512=25%.

IftheDutyvaluedefinedbyCCRAorCCRBregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

10-bit STM, PWM Mode, Edge-aligned Mode, T1DPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod CCRADuty 1�8 �5� �84 51� �40 7�8 89� 10�4

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.

Rev. 1.40 10� �ove��e� �� 01� Rev. 1.40 10� �ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e




TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle set �y CCRA



when TnPOL = 1PWM Pe�iod set �y CCRP

TM O/P Pin(TnOC=0)


Note:1.HereTnDPX=0,CounterclearedbyCCRP2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=1

Rev. 1.40 10� �ove��e� �� 01� Rev. 1.40 10� �ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Ti�e

Counte� clea�ed �y CCRA



TnDPX = 1; TnM [1:0] = 10

PWM Duty Cycle set �y CCRP



when TnPOL = 1PWM Pe�iod set �y CCRA

TM O/P Pin(TnOC=0)


Note:1.HereTnDPX=1--CounterclearedbyCCRA2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenTnIO[1:0]=00or014.TheTnCCLRbithasnoinfluenceonPWMoperation5.n=1

Rev. 1.40 104 �ove��e� �� 01� Rev. 1.40 105 �ove��e� �� 01�



Single Pulse ModeToselectthismode,bitsT1M1andT1M0intheTM1C1registershouldbesetto10respectivelyandalsotheT1IO1andT1IO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheT1ONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theT1ONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalTCK1pin,whichwillinturninitiatetheSinglePulseoutput.WhentheT1ONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheT1ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheT1ONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheT1ONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaTMinterrupt.Thecountercanonlyberesetback tozerowhentheT1ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheT1CCLRandT1nDPXbitsarenotusedinthisMode.

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� � � � � � � ��

� ��

� � � � � � � ��

� � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � � � � � �

Single Pulse Generation

Rev. 1.40 104 �ove��e� �� 01� Rev. 1.40 105 �ove��e� �� 01�



Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TM O/P Pin(TnOC=1)

Time

Counter stopped by CCRA

PauseResume Counter Stops

by software

Counter Reset when TnON returns high

TnM [1:0] = 10 ; TnIO [1:0] = 11

Pulse Width set by CCRA

Output Invertswhen TnPOL = 1

No CCRP Interrupts generated

TM O/P Pin(TnOC=0)

TCKn pin

Software Trigger

Cleared by CCRA match

TCKn pin Trigger

Auto. set by TCKn pin

Software Trigger

Software Clear

Software TriggerSoftware

Trigger

Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh5.IntheSinglePulseMode,TnIO[1:0]mustbesetto“11”andcannotbechanged6.n=1

Rev. 1.40 10� �ove��e� �� 01� Rev. 1.40 107 �ove��e� �� 01�



Capture Input ModeToselectthismodebitsT1M1andT1M0intheTM1C1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheTP1_0orTP1_1pin,whoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheT1IO1andT1IO0bitsintheTM1C1register.ThecounterisstartedwhentheT1ONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

When therequirededge transitionappearson theTP1_0orTP1_1pin thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTP1_0orTP1_1pinthecounterwillcontinuetofreerununtil theT1ONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;in thiswaytheCCRPvaluecanbeusedtocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheT1IO1andT1IO0bitscanselecttheactivetriggeredgeontheTP1_0orTP1_1pintobearisingedge,fallingedgeorbothedgetypes.If theT1IO1andT1IO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTP1_0orTP1_1pin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTP1_0orTP1_1pinispinsharedwithotherfunctions,caremustbetakeniftheTMisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheT1CCLRandT1DPXbitsarenotusedinthisMode.

CCRP

Counte�Value Counte�

ove�flow

CCRP Int.Flag TnPF

CCRA Int.Flag TnAF

TnO�

Pause

Counte�Reset

TnPAU

Resu�e

Stop

Ti�e

YY

XX

CCRAValue XX

TM Captu�ePin TPn_x

YY

TnIO [1:0]Value 00 - Rising edge 01 - Falling edge 11 - Disa�le Captu�e

Activeedge

Activeedge

XX

10 - Both edges

edge

YY

TnM [1:0] = 01

Active

Capture Input Mode

Note:1.TnM[1:0]=01andactiveedgesetbytheTnIO[1:0]bits2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction-TnOCandTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=1;x=0or1.

Rev. 1.40 10� �ove��e� �� 01� Rev. 1.40 107 �ove��e� �� 01�



Enhanced Type TM – ETMTheEnhancedTypeTMcontains fiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheEnhancedTMcanalsobecontrolledwithanexternalinputpinandcandrivethreeexternaloutputpins.

CTM Name TM No. TM Input Pin TM Output Pin

HT��F�0-1/HT�8F�0-1 ― ― ― ―

HT��F�0-1/HT�8F�0-1 10-�it ETM TM1 TCK1 TP1A; TP1B_0� TP1B_1

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��

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Enhanced Type TM Block Diagram (n=1)

Enhanced TM OperationAtitscoreisa10-bitcount-up/count-downcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Thereare three internalcomparatorswith thenames,ComparatorA,ComparatorBandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRA,CCRBandCCRPregisters.TheCCRPcomparatoris3-bitswidewhosevalueiscomparedwith thehighest3-bits in thecounterwhileCCRAandCCRBare10-bitswideand thereforecomparedwithallcounterbits.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychanging theT1ONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheEnhancedTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroloutputpins.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.40 108 �ove��e� �� 01� Rev. 1.40 109 �ove��e� �� 01�



Enhanced Type TM Register DescriptionOveralloperationoftheEnhancedTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRBvalue.TheremainingthreeregistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodesaswellasthethreeCCRPbits.

Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TM1C0 T1PAU T1CK� T1CK1 T1CK0 T1O� T1RP� T1RP1 T1RP0TM1C1 T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1PAOL T1CD� T1CCLRTM1C� T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1PBOL T1PWM1 T1PWM0TM1DL D7 D� D5 D4 D� D� D1 D0TM1DH — — — — — — D9 D8TM1AL D7 D� D5 D4 D� D� D1 D0TM1AH — — — — — — D9 D8TM1BL D7 D� D5 D4 D� D� D1 D0TM1BH — — — — — — D9 D8

10-bit Enhanced TM Register List – HT66F30-1/HT68F30-1

TM1C0 Register – 10-bit ETM




Bit6~4 T1CK2~T1CK0:SelectTM1Counterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fTBC101:Reserved110:TCK1risingedgeclock111:TCK1fallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheTM.SelectingtheReservedclockinputwilleffectivelydisabletheinternalcounter.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYS isthesystemclock,whilefHandfTBCareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Rev. 1.40 108 �ove��e� �� 01� Rev. 1.40 109 �ove��e� �� 01�




Thisbitcontrols theoverallon/offfunctionof theTM.SettingthebithighenablesthecountertorunandclearingthebitdisablestheTM.Clearingthisbittozerowillstop thecounter fromcountingand turnoff theTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTMisintheCompareMatchOutputModethentheTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheT1OCbit,whentheT1ONbitchangesfromlowtohigh.


ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtoclear theinternalcounterif theT1CCLRbit isset tozero.SettingtheT1CCLRbit tozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.40 110 �ove��e� �� 01� Rev. 1.40 111 �ove��e� �� 01�




Bit 7 6 5 4 3 2 1 0�a�e T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CD� T1CCLRR/W R/W R/W R/W R/W R/W R/W R R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1AM1~T1AM0:SelectTM1CCRAOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1AM1andT1AM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1AIO1~T1AIO0:SelectTP1AoutputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1A01:InputcaptureatfallingedgeofTP1A10:Inputcaptureatfalling/risingedgeofTP1A11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode,theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowor totoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1AOCbitintheTM1C1register.Notethattheoutputlevel requestedbytheT1AIO1andT1AIO0bitsmustbedifferent fromthe initialvaluesetupusingtheT1AOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1AIO1andT1AIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheT1AIO1andT1AIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1AIO1andT1AIO0bitsarechangedwhentheTMisrunning.

Rev. 1.40 110 �ove��e� �� 01� Rev. 1.40 111 �ove��e� �� 01�



Bit3 T1AOC:TP1AOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh


This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTM isbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.Ithasnoeffectif theTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theTMoutputpinbeforeacomparematchoccurs. In thePWMModeitdetermines if thePWMsignalisactivehighoractivelow.

Bit2 T1APOL:TP1AOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1Aoutputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1 T1CDN:TM1Countupordownflag0:Countup1:Countdown

Bit0 T1CCLR:SelectTM1Counterclearcondition0:TM1ComparatrorPmatch1:TM1ComparatrorAmatch

Thisbit isused to select themethodwhichclears the counter.Remember thattheEnhancedTMcontains threecomparators,ComparatorA,ComparatorBandComparatorP,butonlyComparatorAorComparatorPcanbeselectedtocleartheinternalcounter.WiththeT1CCLRbitsethigh, thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheT1CCLRbitisnotusedinthePWM,SinglePulseorInputCaptureMode.

Rev. 1.40 11� �ove��e� �� 01� Rev. 1.40 11� �ove��e� �� 01�




Bit 7 6 5 4 3 2 1 0�a�e T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 T1BM1~T1BM0:SelectTM1CCRBOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheTM.ToensurereliableoperationtheTMshouldbeswitchedoffbeforeanychangesaremade to theT1BM1andT1BM0bits.IntheTimer/CounterMode,theTMoutputpincontrolmustbedisabled.

Bit5~4 T1BIO1~T1BIO0:SelectTP1B_0,TP1B_1outputfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofTP1B_0,TP1B_101:InputcaptureatfallingedgeofTP1B_0,TP1B_110:Inputcaptureatfalling/risingedgeofTP1B_0,TP1B_111:inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.IntheCompareMatchOutputMode, theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorB.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorB.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheT1BOCbitintheTM1C2register.Notethattheoutputlevel requestedby theT1BIO1andT1BIO0bitsmustbedifferentfromthe initialvaluesetupusingtheT1BOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.AftertheTMoutputpinchangesstateitcanberesettoitsinitiallevelbychangingtheleveloftheT1ONbitfromlowtohigh.InthePWMMode,theT1BIO1andT1BIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheT1BIO1andT1BIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheT1BIO1andT1BIO0bitsarechangedwhentheTMisrunning.

Rev. 1.40 11� �ove��e� �� 01� Rev. 1.40 11� �ove��e� �� 01�



Bit3 T1BOC:TP1B_0,TP1B_1OutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh


This is theoutputcontrolbit for theTMoutputpin. ItsoperationdependsuponwhetherTM isbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.Ithasnoeffectif theTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theTMoutputpinbeforeacomparematchoccurs. In thePWMModeitdetermines if thePWMsignalisactivehighoractivelow.

Bit2 T1BPOL:TP1B_0,TP1B_1OutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheTP1B_0,TP1B_1outputpin.WhenthebitissethightheTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.

Bit1~0 T1PWM1~T1PWM0:SelectPWMMode00:Edgealigned01:Centrealigned,comparematchoncountup10:Centrealigned,comparematchoncountdown11:Centrealigned,comparematchoncountupordown

TM1DL Register – 10-bit ETM



TM1DH Register – 10-bit ETM

Bit 7 6 5 4 3 2 1 0�a�e — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 TM1DH:TM1CounterHighByteRegisterbit1~bit0


TM1AL Register – 10-bit ETM



Rev. 1.40 114 �ove��e� �� 01� Rev. 1.40 115 �ove��e� �� 01�



TM1AH Register – 10-bit ETM


Bit7~2 Unimplemented,readas"0"Bit1~0 TM1AH:TM1CCRAHighByteRegisterbit1~bit0


TM1BL Register – 10-bit ETM


Bit7~0 TM1BL:TM1CCRBLowByteRegisterbit7~bit0TM110-bitCCRBbit7~bit0

TM1BH Register – 10-bit ETM


Bit7~2 Unimplemented,readas"0"Bit1~0 TM1BH:TM1CCRBHighByteRegisterbit1~bit0

TM110-bitCCRBbit9~bit8

Enhanced Type TM Operating ModesTheEnhancedTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheT1AM1andT1AM0bitsintheTM1C1,andtheT1BM1andT1BM0bitsintheTM1C2register.

ETM Operation Mode

CCRA Compare

Match Output Mode

CCRA Timer/Counter

Mode

CCRA PWM Output Mode

CCRA Single Pulse Output

Mode

CCRA Input Capture Mode

CCRB Co�pa�e Match Output Mode √ — — — —CCRB Ti�e�/Counte� Mode — √ — — —CCRB PWM Output Mode — — √ — —CCRB Single Pulse Output Mode — — — √ —CCRB Input Captu�e Mode — — — — √

“√”: permitted; “—”: not permitted

Rev. 1.40 114 �ove��e� �� 01� Rev. 1.40 115 �ove��e� �� 01�



Compare Match Output ModeToselect thismode,bitsT1AM1,T1AM0andT1BM1,T1BM0intheTM1C1/TM1C2registersshouldbeallclearedtozero.Inthismodeoncethecounterisenabledandrunningitcanbeclearedbythreemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheT1CCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP, theother iswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththeT1AFandT1PFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheT1CCLRbitintheTM1C1registerishighthenthecounterwillbeclearedwhenacomparematchoccurs fromComparatorA.However,hereonly theT1AFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenT1CCLRishighnoT1PFinterruptrequestflagwillbegenerated.

Asthenameof themodesuggests,afteracomparisonismade, theTMoutputpin,willchangestate.TheTMoutputpinconditionhoweveronlychangesstatewhenaT1AForT1BFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorAorComparatorB.TheT1PFinterruptrequest flag,generatedfromacomparematchfromComparatorP,willhavenoeffectontheTMoutputpin.ThewayinwhichtheTMoutputpinchangesstateisdeterminedbytheconditionoftheT1AIO1andT1AIO0bitsintheTM1C1registerforETMCCRA,andtheT1BIO1andT1BIO0bitsintheTM1C2registerforETMCCRB.TheTMoutputpincanbeselectedusingtheT1AIO1,T1AIO0bits(fortheTP1Apin)andT1BIO1,T1BIO0bits(fortheTP1B_0,TP1B_1pins)togohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorAoracomparematchoccursfromComparatorB.TheinitialconditionoftheTMoutputpin,issetupaftertheT1AOCorT1BOCbitforTP1AorTP1B_0,TP1B_1outputpins.NotethatiftheT1AIO1,T1AIO0andT1BIO1,T1BIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.40 11� �ove��e� �� 01� Rev. 1.40 117 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnAPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TPnA O/P Pin

Ti�e

CCRP=0

CCRP > 0


Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnAM [1:0] = 00

Output pin set to initial Level Low if TnAOC=0


�ote TnAIO [1:0] = 10 Active High Output selectHe�e TnAIO [1:0] = 11





Output Inve�tswhen TnAPOL is high

ETM CCRA Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0theComparatorPmatchwillclearthecounter2.TPnAoutputpincontrolledonlybyTnAFflag3.OutputpinresettoinitialstatebyTnONbitrisingedge4.n=1

Rev. 1.40 11� �ove��e� �� 01� Rev. 1.40 117 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRB

TnO�

TnPAU

TnBPOL

CCRP Int. Flag TnPF

CCRB Int. Flag TnBF

TPnB O/P Pin

Ti�e

CCRP=0

CCRP > 0


Pause

Resu�e

Stop

Counte� Resta�t

TnCCLR = 0; TnBM [1:0] = 00

Output pin set to initial Level Low if TnBOC=0

Output Toggle with TnBF flag

�ote TnBIO [1:0] = 10 Active High Output selectHe�e TnBIO [1:0] = 11


Output not affected �y TnBF flag. Re�ains High until �eset �y TnO� �it



Output Inve�tswhen TnBPOL is high

ETM CCRB Compare Match Output Mode – TnCCLR=0

Note:1.WithTnCCLR=0theComparatorPmatchwillclearthecounter2.TPnBoutputpincontrolledonlybyTnBFflag3.OutputpinresettoinitialstatebyTnONbitrisingedge4.n=1

Rev. 1.40 118 �ove��e� �� 01� Rev. 1.40 119 �ove��e� �� 01�



Counte� Value

0x�FF

CCRP

CCRA

TnO�

TnPAU

TnAPOL

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

TPnA O/P Pin

Ti�e

CCRA=0


Pause

Resu�e


TnCCLR = 1; TnAM [1:0] = 00

Output pin set to initial Level Low if TnAOC=0


�ote TnAIO [1:0] = 10 Active High Output selectHe�e TnAIO [1:0] = 11









ETM CCRA Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1theComparatorAmatchwillclearthecounter2.TPnAoutputpincontrolledonlybyTnAFflag3.TPnAoutputpinresettoinitialstatebyTnONrisingedge4.TnPFflagsnotgeneratedwhenTnCCLR=15.n=1

Rev. 1.40 118 �ove��e� �� 01� Rev. 1.40 119 �ove��e� �� 01�



Counte� Value

0x�FF

CCRB

CCRA

TnO�

TnPAU

TnBPOL

CCRB Int. Flag TnBF

CCRA Int. Flag TnAF

TPnB O/P Pin

Ti�e

CCRA=0


Pause

Resu�e


TnCCLR = 1; TnBM [1:0] = 00

Output pin set to initial Level Low if TnBOC=0

Output Toggle with TnBF flag

�ote TnBIO [1:0] = 10 Active High Output selectHe�e TnBIO [1:0] = 11


Output not affected �y TnBF flag. Re�ains High until �eset �y TnO� �it





ETM CCRB Compare Match Output Mode – TnCCLR=1

Note:1.WithTnCCLR=1theComparatorAmatchwillclearthecounter2.TPnBoutputpincontrolledonlybyTnBFflag3.TPnBoutputpinresettoinitialstatebyTnONrisingedge4.TnPFflagsnotgeneratedwhenTnCCLR=15.n=1

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



Timer/Counter ModeToselectthismode,bitsT1AM1,T1AM0andT1BM1,T1BM0intheTM1C1andTM1C2registershouldallbesethigh.TheTimer/CounterModeoperates inan identicalway to theCompareMatchOutputModegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselect thismode, therequiredbitpairs,T1AM1,T1AM0andT1BM1,T1BM0shouldbesetto10respectivelyandalsotheT1AIO1,T1AIO0andT1BIO1,T1BIO0bitsshouldbeset to10respectively.ThePWMfunctionwithintheTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleontheTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,theT1CCLRbitisusedtodetermineinwhichwaythePWMperiodiscontrolled.WiththeT1CCLRbitsethigh,thePWMperiodcanbefinelycontrolledusingtheCCRAregisters.InthiscasetheCCRBregistersareusedtosetthePWMdutyvalue(forTP1B_0andTP1B_1outputpins).TheCCRPbitsarenotusedandTP1Aoutputpinisnotused.ThePWMoutputcanonlybegeneratedontheTP1B_0andTP1B_1outputpins.WiththeT1CCLRbitclearedtozero,thePWMperiodissetusingoneoftheeightvaluesofthethreeCCRPbits,inmultiplesof128.NowbothCCRAandCCRBregisterscanbeusedtosetupdifferentdutycyclevaluestoprovidedualPWMoutputsontheirrelativeTP1AandTP1B_0/TP1B_1pins.

TheT1PWM1andT1PWM0bitsdeterminethePWMalignment type,whichcanbeeitheredgeorcentre type. Inedgealignment, the leadingedgeof thePWMsignalswillallbegeneratedconcurrentlywhenthecounter isreset tozero.Withallpowercurrentsswitchingonat thesametime,thismaygiverisetoproblemsinhigherpowerapplications.IncentrealignmentthecentreofthePWMactivesignalswilloccursequentially, thusreducingthelevelofsimultaneouspowerswitchingcurrents.

Interruptflags,oneforeachoftheCCRA,CCRBandCCRP,willbegeneratedwhenacomparematchoccurs fromeither theComparatorA,ComparatorBorComparatorP.TheT1AOCandT1BOCbitsintheTM1C1andTM1C2registerareusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoT1AIO1,T1AIO0andT1BIO1,T1BIO0bitspairsareusedtoenablethePWMoutputortoforcetheTMoutputpintoafixedhighorlowlevel.TheT1APOLandT1BPOLbitareusedtoreversethepolarityofthePWMoutputwaveform.

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



ETM, PWM Mode, Edge – aligned Mode, T1CCLR=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod 1�8 �5� �84 51� �40 7�8 89� 10�4A Duty CCRAB Duty CCRB

IffSYS=16MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128andCCRB=256,

TheTP1APWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

TheTP1B_nPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=256/512=50%.

IftheDutyvaluedefinedbytheCCRAorCCRBregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

ETM, PWM Mode, Edge – aligned Mode, T1CCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Pe�iod 1 � � 511 51� 10�1 10�� 10��B Duty CCRB

ETM, PWM Mode, Center – aligned Mode, T1CCLR=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000bPe�iod �5� 51� 7�8 10�4 1�80 15�� 179� �04�A Duty (CCRA×�) - 1B Duty (CCRB×�) - 1

ETM, PWM Mode, Center – aligned Mode, T1CCLR=1

CCRA 1 2 3 511 512 1021 1022 1023Pe�iod � 4 � 10�� 10�4 �04� �044 �04�B Duty (CCRB×�) - 1

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnAPOL

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

TPnA Pin (TnAOC=1)

Ti�e

Counte� Clea�ed �y CCRP

PauseResu�e Stop Counte�

Resta�t

TnCCLR = 0;TnAM [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 00




CCRB

CCRP Int. Flag TnPF

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)

Duty Cycle set �y CCRA

Duty Cycle set �y CCRB

PWM Pe�iod set �y CCRP



ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearscounteranddeterminesPWMperiod2.InternalPWMfunctioncontinuesevenwhenTnAIO[1:0](orTnBIO[1:0])=00or013.CCRAcontrolsTPnAPWMdutyandCCRBcontrolsTPnBPWMduty4.n=1

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



Counte� Value

CCRA

TnO�

TnPAU

TnBPOL

CCRB Int. Flag TnBF

Ti�e

Counte� Clea�ed �y CCRA

PauseResu�e Stop Counte�

Resta�t

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 00




CCRB

CCRP Int. Flag TnPF

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)


PWM Pe�iod set �y CCRA

ETM PWM Mode – Edge Aligned

Note:1.HereTnCCLR=1thereforeCCRAclearscounteranddeterminesPWMperiod2.InternalPWMfunctioncontinuesevenwhenTnBIO[1:0]=00or013.CCRAcontrolsTPnBPWMperiodandCCRBcontrolsTPnBPWMduty4.HeretheTMpincontrolregistershouldnotenabletheTPnApinasaTMoutputpin5.n=1

Rev. 1.40 1�4 �ove��e� �� 01� Rev. 1.40 1�5 �ove��e� �� 01�



Counte� Value

CCRP

CCRA

TnO�

TnPAU

TnAPOL

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

TPnA Pin (TnAOC=1)

Ti�e

Pause

Resu�eStop

Counte� Resta�t

TnCCLR = 0;TnAM [1:0] = 10� TnBM [1:0] = 10;TnPWM [1:0] = 11


Output cont�olled �y Othe� pin-sha�ed function


CCRB

CCRP Int. Flag TnPF

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)



PWM Pe�iod set �y CCRP

ETM PWM Mode – Centre Aligned

Note:1.HereTnCCLR=0thereforeCCRPclearscounteranddeterminesPWMperiod2.TnPWM1/TnPWM0=11thereforePWMiscentrealigned3.InternalPWMfunctioncontinuesevenwhenTnAIO[1:0](orTnBIO[1:0])=00or014.CCRAcontrolsTPnAPWMdutyandCCRBcontrolsTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1

Rev. 1.40 1�4 �ove��e� �� 01� Rev. 1.40 1�5 �ove��e� �� 01�



Counte� Value

CCRA

TnO�

TnPAU

TnBPOL

CCRA Int. Flag TnAF

CCRB Int. Flag TnBF

Ti�e

Pause

Resu�eStop

Counte� Resta�t

TnCCLR = 1; TnBM [1:0] = 10;TnPWM [1:0] = 11


Output cont�olled�y othe� pin-sha�ed function

CCRB

TPnB Pin (TnBOC=1)

TPnB Pin (TnBOC=0)


PWM Pe�iod set �y CCRA


CCRP Int. Flag TnPF

ETM PWM Mode – Centre Aligned

Note:1.HereTnCCLR=1thereforeCCRAclearscounteranddeterminesPWMperiod2.TnPWM1/TnPWM0=11thereforePWMiscentrealigned3.InternalPWMfunctioncontinuesevenwhenTnBIO[1:0]=00or014.CCRAcontrolstheTPnBPWMperiodandCCRBcontrolstheTPnBPWMduty5.CCRPwillgenerateaninterruptrequestwhenthecounterdecrementstoitszerovalue6.n=1

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�7 �ove��e� �� 01�



Single Pulse Output ModeToselectthismode,therequiredbitpairs,T1AM1,T1AM0andT1BM1,T1BM0shouldbesetto10respectivelyandalsothecorrespondingT1AIO1,T1AIO0andT1BIO1,T1BIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheTMoutputpin.

ThetriggerforthepulseTP1AoutputleadingedgeisalowtohightransitionoftheT1ONbit,whichcanbeimplementedusingtheapplicationprogram.ThetriggerforthepulseTP1Boutputleadingedge isacomparematchfromComparatorB,whichcanbe implementedusing theapplicationprogram.However in theSinglePulseMode, theT1ONbitcanalsobemade toautomaticallychangefromlowtohighusingtheexternalTCK1pin,whichwillinturninitiatetheSinglePulseoutputofTP1A.WhentheT1ONbittransitionstoahighlevel, thecounterwillstartrunningandthepulseleadingedgeofTP1Awillbegenerated.TheT1ONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgeofTP1AandTP1BwillbegeneratedwhentheT1ONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheT1ONbitandthusgeneratetheSinglePulseoutputtrailingedgeofTP1AandTP1B.InthiswaytheCCRAvaluecanbeusedtocontrol thepulsewidthofTP1A.TheCCRA-CCRBvaluecanbeusedtocontrol thepulsewidthofTP1B.AcomparematchfromComparatorAandComparatorBwillalsogenerateTMinterrupts.ThecountercanonlyberesetbacktozerowhentheT1ONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheT1CCLRbitisalsonotused.

S/W Co��and SET“TnO�”

o�TCKn Pin T�ansition

CCRB Leading Edge

CCRA T�ailing Edge

S/W Co��and CLR“TnO�”

o�CCRA Co�pa�e Match

TPnA Output Pin

TPnB Output Pin

Pulse Width = (CCRA-CCRB) Value

Pulse Width = CCRA Value

Counte� Value

CCRB

CCRA

0 Ti�e

TnO� = 1CCRB Co�pa�e Match

S/W Co��and CLR“TnO�”

o�CCRA Co�pa�e MatchCCRB

T�ailing Edge

CCRA Leading Edge

TnO� �it1 → 0

TnO� �it1 → 0

TnO� �it0 → 1

Single Pulse Generation (n=1)

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�7 �ove��e� �� 01�



Counte� Value

CCRB

CCRA

TnO�

TnPAU

TnAPOL

CCRB Int. Flag TnBFCCRA Int. Flag TnAF

TPnA Pin(TnAOC=1)

Ti�e

Counte� stopped �y CCRA

PauseResu�e Counte� Stops

�y softwa�e


TnAM [1:0] = 10� TnBM [1:0] = 10;TnAIO [1:0] = 11� TnBIO [1:0] = 11

Pulse Width set �y (CCRA-CCRB) Output Inve�ts

when TnBPOL=1

TCKn pin

Softwa�e T�igge�

Clea�ed �y CCRA �atch

TCKn pin T�igge�

Auto. set �y TCKn pin

Softwa�e T�igge�

Softwa�e Clea�

Softwa�e T�igge�Softwa�e

T�igge�

TnBPOL

TPnA Pin(TnAOC=0)

TPnB Pin(TnBOC=1)

TPnB Pin(TnBOC=0)

Pulse Width set �y CCRA

Output Inve�tswhen TnAPOL=1

ETM – Single Pulse Mode

Note:1.CounterstoppedbyCCRA2.CCRPisnotused3.ThepulsetriggeredbytheTCKnpinorbysettingtheTnONbithigh4.ATCKnpinactiveedgewillautomaticallysettheTnONbithigh.5.IntheSinglePulseMode,TnAIO[1:0]andTnBIO[1:0]mustbesetto“11”andcannotbechanged.6.n=1

Rev. 1.40 1�8 �ove��e� �� 01� Rev. 1.40 1�9 �ove��e� �� 01�



Capture Input ModeToselectthismodebitsT1AM1,T1AM0andT1BM1,T1BM0intheTM1C1andTM1C2registersshouldbeset to01 respectively.Thismodeenablesexternal signals tocaptureandstore thepresentvalueoftheinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.Theexternalsignal issuppliedon theTP1AandTP1B_0,TP1B_1pins,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges; theactiveedgetransitiontypeisselectedusingtheT1AIO1,T1AIO0andT1BIO1,T1BIO0bitsintheTM1C1andTM1C2registers.ThecounterisstartedwhentheT1ONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheTP1AandTP1B_0,TP1B_1pinsthepresentvaluein thecounterwillbelatchedintotheCCRAandCCRBregistersandaTMinterruptgenerated.IrrespectiveofwhateventsoccurontheTP1AandTP1B_0,TP1B_1pinsthecounterwillcontinuetofreerununtiltheT1ONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheT1AIO1,T1AIO0andT1BIO1,T1BIO0bitscanselecttheactive triggeredgeontheTP1AandTP1B_0,TP1B_1pins tobearisingedge,fallingedgeorbothedgetypes.If theT1AIO1,T1AIO0andT1BIO1,T1BIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheTP1AandTP1B_0,TP1B_1pins,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheTP1AandTP1B_0,TP1B_1pinsarepinsharedwithotherfunctions,caremustbetakenif theTMisintheCaptureInputMode.Thisisbecauseif thepinissetupasanoutput, thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheT1CCLR,T1AOC,T1BOC,T1APOLandT1BPOLbitsarenotusedinthismode.

Rev. 1.40 1�8 �ove��e� �� 01� Rev. 1.40 1�9 �ove��e� �� 01�



Counte� Value

YY

CCRP

TnO�

TnPAU

CCRP Int. Flag TnPF

CCRA Int. Flag TnAF

CCRA Value

Ti�e


PauseResu�e

Counte� Reset

TnAM [1:0] = 01

TM captu�e pin TPnA

XX

Counte� Stop

TnAIO [1:0] Value

XX YY XX YY

Active edge Active

edgeActive edge

00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disa�le Captu�e

ETM CCRA Capture Input Mode

Note:1.T1AM[1:0]=01andactiveedgesetbytheT1AIO[1:0]bits2.TMCaptureinputpinactiveedgetransferscountervaluetoCCRA3.TnCCLRbitnotused4.Nooutputfunction–TnAOCandTnAPOLbitsnotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=1

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



CCRP

Counte� ove�flow

CCRP Int.Flag TnPF

CCRB Int.Flag TnBF

TnO� �it

Pause

Counte�Reset

TnPAU �it

Resu�e

Stop

YY

XX

CCRBValue XX

TM Captu�e Pin

YY

TnBIO1� TnBIO0Value 00 - Rising edge 01 - Falling edge 11 - Disa�le Captu�e

Activeedge

Activeedge

XX

10 - Both edges

Activeedges

YY

TnBM1� TnBM0 = 01

Ti�e

Counte�Value

ETM CCRB Capture Input Mode

Note:1.TnBM[1:0]=01andactiveedgesetbytheTnBIO[1:0]bits2.TheTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRB3.TheTnCCLRbitisnotused4.Nooutputfunction–TnBOCandTnBPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=1

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



Analog to Digital ConverterTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.TheA/DConverterisonlycontainedintheHT66F30-1andHT66F20-1devices.

A/D OverviewTheHT66F30-1containsamulti-channelanalogtodigitalconverterwhichcandirectlyinterfacetoexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoeithera12-bitdigitalvalue.

Part No. Input Channels A/D Channel Select Bits Input PinsHT��F�0-1/HT��F�0-1 8 ACS4� ACS�~ACS0 A�0~A�7

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

� � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � � �

� � � ��

� � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � �

� � �

� � � � � � � ��

� � �

� � � � � � � � �

� � � � � � � � � � � � � �

� � � � �

� � � � � � � �

� � �

� � � � ��

� � �

� � � � ��

� � � � ��

A/D Converter Structure

A/D Converter Register DescriptionOveralloperationoftheA/Dconverter iscontrolledusingfiveregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.TheremainingthreeregistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Register NameBit

7 6 5 4 3 2 1 0ADRL(ADRFS=0) D� D� D1 D0 — — — —ADRL(ADRFS=1) D7 D� D5 D4 D� D� D1 D0ADRH(ADRFS=0) D11 D10 D9 D8 D7 D� D5 D4ADRH(ADRFS=1) — — — — D11 D10 D9 D8ADCR0 START EOCB ADOFF ADRFS — ACS� ACS1 ACS0ADCR1 ACS4 V1�5E� — VREFS — ADCK� ADCK1 ADCK0ACERL ACE7 ACE� ACE5 ACE4 ACE� ACE� ACE1 ACE0

A/D Converter Register List – HT66F30-1/HT66F20-1

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



A/D Converter Data Registers – ADRL, ADRHAstheHT66F30-1orHT66F20-1devicecontainsaninternal12-bitA/Dconverter,itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasADRH,andalowbyteregister,knownasADRL.Aftertheconversionprocesstakesplace,theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised,theformatinwhichthedataisstorediscontrolledbytheADRFSbitintheADCR0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.

ADRFSADRH ADRL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D7 D� D5 D4 D� D� D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D7 D� D5 D4 D� D� D1 D0

A/D Data Registers

A/D Converter Control Registers – ADCR0, ADCR1, ACERLTocontrolthefunctionandoperationoftheA/Dconverter,threecontrolregistersknownasADCR0,ADCR1andACERLareprovided.These8-bitregistersdefinefunctionssuchastheselectionofwhichanalogchannel isconnected to the internalA/Dconverter, thedigitiseddata format, theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.TheACS2~ACS0bitsintheADCR0registerandACS4bitistheADCR1registerdefine theADCinputchannelnumber.As thedevicescontainonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheindividual8analoginputsmustberoutedtotheconverter.ItisthefunctionoftheACS4andACS2~ACS0bitstodeterminewhichanalogchannelinputpinsorinternal1.25VisactuallyconnectedtotheinternalA/Dconverter.

TheACERLcontrolregistercontainstheACE7~ACE0bitswhichdeterminewhichpinsonPortAisusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.SettingthecorrespondingbithighwillselecttheA/Dinputfunction,clearingthebittozerowillselecteithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



ADCR0 Register

Bit 7 6 5 4 3 2 1 0�a�e START EOCB ADOFF ADRFS — ACS� ACS1 ACS0R/W R/W R R/W R/W — R/W R/W R/WPOR 0 1 1 0 — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto“1”

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

ThisreadonlyflagisusedtoindicatewhenanA/Dconversionprocesshascompleted.Whentheconversionprocessisrunning,thebitwillbehigh.

Bit5 ADOFF:ADCmodulepoweron/offcontrolbit0:ADCmodulepoweron1:ADCmodulepoweroff

Thisbitcontrols thepowerto theA/Dinternalfunction.ThisbitshouldbeclearedtozerotoenabletheA/Dconverter.IfthebitissethighthentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.AstheA/Dconverterwillconsumealimitedamountofpower,evenwhennotexecutingaconversion,thismaybeanimportantconsiderationinpowersensitivebatterypoweredapplications.Note:1.itisrecommendedtosetADOFF=1beforeenteringIDLE/SLEEPModefor

savingpower.2.ADOFF=1willpowerdowntheADCmodule.

Bit4 ADRFS:ADCDataFormatControl0:ADCDataMSBisADRHbit7,LSBisADRLbit41:ADCDataMSBisADRHbit3,LSBisADRLbit0

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.

Bit3 Unimplemented,readas"0"Bit2~0 ACS2,ACS1, ACS0:SelectA/Dchannel(whenACS4is“0”)

000:AN0001:AN1010:AN2011:AN3100:AN4101:AN5110:AN6111:AN7

ThesearetheA/Dchannelselectcontrolbits.AsthereisonlyoneinternalhardwareA/DconvertereachoftheeightA/Dinputsmustberoutedtotheinternalconverterusingthesebits.IfbitACS4intheADCR1registerissethighthentheinternal1.25VwillberoutedtotheA/DConverter.

Rev. 1.40 1�4 �ove��e� �� 01� Rev. 1.40 1�5 �ove��e� �� 01�



ADCR1 Register

Bit 7 6 5 4 3 2 1 0�a�e ACS4 V1�5E� — VREFS — ADCK� ADCK1 ADCK0R/W R/W R/W — R/W — R/W R/W R/WPOR 0 0 — 0 — 0 0 0

Bit7 ACS4:SelectInternal1.25VbandgapvoltageasADCinput0:Disable1:Enable

Thisbitenablesthe1.25VbandgapvoltagetobeconnectedtotheA/Dconverter.TheV125ENbitmustfirsthavebeensettoenablethebandgapcircuit1.25VvoltagetobeusedbytheA/Dconverter.WhentheACS4bitissethigh,thebandgap1.25VvoltagewillberoutedtotheA/DconverterandtheotherA/Dinputchannelsdisconnected.

Bit6 V125EN:Internal1.25VControl0:Disable1:Enable

Thisbitcontrols the internalBandgapcircuiton/offfunctionto theA/Dconverter.Whenthebitissethighthebandgapvoltage1.25VcanbeusedasanA/Dconverterinput.Ifthebandgapvoltage1.25VisnotusedbytheA/DconverterandtheLVR/LVDfunctionisdisabledthenthebandgapreferencecircuitwillbeautomaticallyswitchedofftoconservepower.When1.25VisswitchedonforusebytheA/Dconverter,atimetBGshouldbeallowedforthebandgapcircuittostabilisebeforeimplementinganA/Dconversion.

Bit5 Unimplemented,readas"0"Bit4 VREFS:SelectADCreferencevoltage

0:InternalADCpower1:VREFpin

ThisbitisusedtoselectthereferencevoltagefortheA/Dconverter.Ifthebitishigh,thentheA/DconverterreferencevoltageissuppliedontheexternalVREFpin.Ifthepinislow,thentheinternalreferenceisusedwhichistakenfromthepowersupplypinVDD.

Bit3 Unimplemented,readas"0"Bit2~0 ADCK2,ADCK1, ADCK0:SelectADCclocksource

000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:Undefined

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

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ACERL Register

Bit 7 6 5 4 3 2 1 0�a�e ACE7 ACE� ACE5 ACE4 ACE� ACE� ACE1 ACE0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7 ACE7:DefinePA7isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN7








A/D OperationTheSTARTbit in theADCR0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theEOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.TheEOCBbit in theADCR0register isused to indicatewhentheanalogtodigitalconversionprocess is complete.Thisbitwillbeautomatically set to “0”by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theADCK2~ADCK0bitsintheADCR1register.

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Although theA/D clock source is determined by the system clocky, fSYS, and by bitsADCK2~ADCK0, therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstheminimumvalueofpermissibleA/Dclockperiod,tADCK,is0.5μs,caremustbetakenforsystemclockfrequenciesequaltoorgreaterthan4MHz.Forexample,ifthesystemclockoperatesatafrequencyof4MHz,theADCK2~ADCK0bitsshouldnotbesetto“000”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)ADCK2, ADCK1, ADCK0

=000 (fSYS)

ADCK2, ADCK1, ADCK0

=001 (fSYS/2)

ADCK2, ADCK1, ADCK0

=010 (fSYS/4)

ADCK2, ADCK1, ADCK0

=011 (fSYS/8)

ADCK2, ADCK1, ADCK0

=100 (fSYS/16)

ADCK2, ADCK1, ADCK0

=101 (fSYS/32)

ADCK2, ADCK1, ADCK0

=110 (fSYS/64)

ADCK2, ADCK1, ADCK0

=111

1MHz 1μs 2μs 4μs 8μs 16μs 32μs 64μs Undefined�MHz 500ns 1μs 2μs 4μs 8μs 16μs 32μs Undefined4MHz �50ns* 500ns 1μs 2μs 4μs 8μs 16μs Undefined8MHz 1�5ns* �50ns* 500ns 1μs 2μs 4μs 8μs Undefined1�MHz 8�ns* 1�7ns* ��ns* ��7ns 1.33μs 2.67μs 5.33μs Undefined

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADOFFbitintheADCR0register.ThisbitmustbezerotopowerontheA/Dconverter.EvenifnopinsareselectedforuseasA/DinputsbyclearingtheACE7~ACE0bitsintheACERLregisters,iftheADOFFbitiszerothensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADOFFissethightoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

ThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromeitherthepositivepowersupplypin,VDD,orfromanexternalreferencesourcessuppliedonpinVREF.ThedesiredselectionismadeusingtheVREFSbit.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFSbitissethigh,theVREFpinfunctionwillbeselectedandtheotherpinfunctionswillbedisabledautomatically.

A/D Input PinsAllof theA/Danalog inputpinsarepin-sharedwith the I/OpinsonPortAaswellasotherfunctions.TheACE7~ACE0bitsintheACERLregister,determinewhethertheinputpinsaresetupasA/Dconverteranaloginputsorwhethertheyhaveotherfunctions.IftheACE7~ACE0bitsforitscorrespondingpinissethighthenthepinwillbesetuptobeanA/Dconverterinputandtheoriginalpinfunctionsdisabled. In thisway,pinscanbechangedunderprogramcontrol tochange theirfunctionbetweenA/Dinputsandotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.Notethat it isnotnecessarytofirstsetuptheA/Dpinasaninput in thePACportcontrolregisters toenable theA/DinputaswhentheACE7~ACE0bitsenableanA/Dinput, thestatusof theportcontrolregisterwillbeoverridden.

TheA/Dconverterhas itsownreferencevoltagepin,VREF,however thereferencevoltagecanalsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheVREFSbitintheADCR1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.

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A/D Input Structure

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsADCK2~ADCK0intheADCR1register.

• Step2EnabletheA/DbyclearingtheADOFFbitintheADCR0registertozero.

• Step3SelectwhichchannelistobeconnectedtotheinternalA/DconverterbycorrectlyprogrammingtheACS4,ACS2~ACS0bitswhicharealsocontainedintheADCR1andADCR0register.

• Step4SelectwhichpinsaretobeusedasA/DinputsandconfigurethembycorrectlyprogrammingtheACE7~ACE0bitsintheACERLregister.

• Step5If theinterruptsare tobeused, theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dconverterinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbit,ADE,mustbothbesethightodothis.

• Step6Theanalog todigitalconversionprocesscannowbe initialisedbysetting theSTARTbit intheADCR0registerfromlowtohighandthenlowagain.Notethat thisbitshouldhavebeenoriginallyclearedtozero.

• Step7Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheADCR0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregisterADRLandADRHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheADCR0registerisused,theinterruptenablestepabovecanbeomitted.

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKwheretADCKisequaltotheA/Dclockperiod.

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A/D Conversion Timing

Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,bysettingbitADOFFhigh in theADCR0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAstheHT66F30-1containsa12-bitA/Dconverter,itsfull-scaleconverteddigitisedvalueisequaltoFFFH.Sincethefull-scaleanaloginputvalueisequal totheVDDorVREFvoltage, thisgivesasinglebitanaloginputvalueofVDDorVREFdividedby4096.

1LSB=(VDDorVREF)÷4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(VDDorVREF)÷4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDorVREFlevel.

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Ideal A/D Transfer Function

A/D Programming ExampleThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheADCR0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockandswitchoff1.25Vclr ADOFFmov a,0Fh ;setupACERLtoconfigurepinsAN0~AN3mov ACERL,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/Dconverter:start_conversion: clrSTART ;highpulseonstartbittoinitiateconversion setSTART ;resetA/D clrSTART ;startA/Dpolling_EOC: sz EOCB ;polltheADCR0registerEOCBbittodetectend ;ofA/Dconversion jmppolling_EOC ;continuepolling mova,ADRL ;readlowbyteconversionresultvalue movADRL_buffer,a ;saveresulttouserdefinedregister mova,ADRH ;readhighbyteconversionresultvalue movADRH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnexta/dconversion

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Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov ADCR1,a ;selectfSYS/8asA/Dclockandswitchoff1.25VClr ADOFFmov a,0Fh ;setupACERLtoconfigurepinsAN0~AN3mov ACERL,amov a,00hmov ADCR0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion: clrSTART ;highpulseonSTARTbittoinitiateconversion setSTART ;resetA/D clrSTART ;startA/D clrADF ;clearADCinterruptrequestflag set ADE ; enable ADC interrupt setEMI ;enableglobalinterrupt:: ; ADC interrupt service routineADC_ISR: movacc_stack,a ;saveACCtouserdefinedmemory mova,STATUS movstatus_stack,a ;saveSTATUStouserdefinedmemory:: mova,ADRL ;readlowbyteconversionresultvalue movadrl_buffer,a ;saveresulttouserdefinedregister mova,ADRH ;readhighbyteconversionresultvalue movadrh_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR: mova,status_stack movSTATUS,a ;restoreSTATUSfromuserdefinedmemory mova,acc_stack ;restoreACCfromuserdefinedmemory reti

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ComparatorsTwoindependentanalogcomparatorsarecontainedwithin thesedevices.Thesefunctionsofferflexibilityviatheirregistercontrolledfeaturessuchaspower-down,polarityselect,hysteresisetc.InsharingtheirpinswithnormalI/OpinsthecomparatorsdonotwastepreciousI/Opinsiftherefunctionsareotherwiseunused.

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Comparator OperationThedevicescontain twocomparator functionswhichareused tocompare twoanalogvoltagesandprovideanoutputbasedon theirdifference.Fullcontrolover the twointernalcomparatorsisprovidedvia twocontrol registers,CP0CandCP1C,oneassigned toeachcomparator.Thecomparatoroutputisrecordedviaabitintheirrespectivecontrolregister,butcanalsobetransferredoutontoasharedI/Opin.Additionalcomparator functions include,outputpolarity,hysteresisfunctionsandpowerdowncontrol.

Anypull-high resistorsconnected to the sharedcomparator inputpinswillbeautomaticallydisconnectedwhenthecomparatorisenabled.Asthecomparatorinputsapproachtheirswitchinglevel,somespuriousoutputsignalsmaybegeneratedonthecomparatoroutputdueto theslowrisingor fallingnatureof the inputsignals.Thiscanbeminimisedbyselecting thehysteresisfunctionwillapplyasmallamountofpositivefeedbacktothecomparator.Ideallythecomparatorshouldswitchat thepointwherethepositiveandnegativeinputssignalsareat thesamevoltagelevel,however,unavoidableinputoffsetsintroducesomeuncertaintieshere.Thehysteresisfunction,ifenabled,alsoincreasestheswitchingoffsetvalue.

Comparator RegistersTherearetworegistersforoverallcomparatoroperation,oneforeachcomparator.Ascorrespondingbits in the tworegistershave identical functions, they following register tableapplies tobothregisters.

RegisterName

Bit

7 6 5 4 3 2 1 0CP0C C0SEL C0E� C0POL C0OUT C0OS — — C0HYE�CP1C C1SEL C1E� C1POL C1OUT C1OS — — C1HYE�

Comparator Registers List

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CP0C Register

Bit 7 6 5 4 3 2 1 0�a�e C0SEL C0E� C0POL C0OUT C0OS — — C0HYE�R/W R/W R/W R/W R R/W — — R/WPOR 1 0 0 0 0 — — 1

Bit7 C0SEL:SelectComparatorpinsorI/Opins0:I/Opinselect1:Comparatorpinselect

ThisistheComparatorpinorI/Opinselectbit.Ifthebitishighthecomparatorwillbeselectedandthetwocomparatorinputpinswillbeenabled.Asaresult,thesetwopinswill losetheirI/Opinfunctions.Anypull-highconfigurationoptionsassociatedwiththecomparatorsharedpinswillalsobeautomaticallydisconnected.

Bit6 C0EN:ComparatorOn/Offcontrol0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedevicesentertheSLEEPorIDLEmode.

Bit5 C0POL:Comparatoroutputpolarity0:outputnotinverted1:outputinverted

Thisisthecomparatorpolaritybit.If thebit iszerothentheC0OUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorC0OUTbitwillbeinverted.

Bit4 C0OUT:ComparatoroutputbitC0POL=00:C0+<C0-1:C0+>C0-

C0POL=10:C0+>C0-1:C0+<C0-

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheC0POLbit.

Bit3 C0OS:Outputpathselect0:C0Xpin1:Internaluse

This is thecomparatoroutputpathselectcontrolbit. If thebit isset to"0"andtheC0SELbit is"1"thecomparatoroutput isconnectedtoanexternalC0Xpin.If thebit isset to"1"or theC0SELbit is"0" thecomparatoroutputsignal isonlyusedinternallybythedevicesallowingthesharedcomparatoroutputpintoretainitsnormalI/Ooperation.

Bit2~1 Unimplemented,readas"0"Bit0 C0HYEN:HysteresisControl

0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

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CP1C RegisterBit 7 6 5 4 3 2 1 0

�a�e C1SEL C1E� C1POL C1OUT C1OS — — C1HYE�R/W R/W R/W R/W R R/W — — R/WPOR 1 0 0 0 0 — — 1

Bit7 C1SEL:SelectComparatorpinsorI/Opins0:I/Opinselect1:Comparatorpinselect

ThisistheComparatorpinorI/Opinselectbit.Ifthebitishighthecomparatorwillbeselectedandthetwocomparatorinputpinswillbeenabled.Asaresult,thesetwopinswill losetheirI/Opinfunctions.Anypull-highconfigurationoptionsassociatedwiththecomparatorsharedpinswillalsobeautomaticallydisconnected.

Bit6 C1EN:ComparatorOn/Offcontrol0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedevicesentertheSLEEPorIDLEmode.

Bit5 C1POL:Comparatoroutputpolarity0:outputnotinverted1:outputinverted

Thisisthecomparatorpolaritybit.If thebit iszerothentheC1OUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorC1OUTbitwillbeinverted.

Bit4 C1OUT:ComparatoroutputbitC1POL=00:C1+<C1-1:C1+>C1-

C1POL=10:C1+>C1-1:C1+<C1-

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheC1POLbit.

Bit3 C1OS:Outputpathselect0:C1Xpin1:Internaluse

This is thecomparatoroutputpathselectcontrolbit. If thebit isset to"0"andtheC1SELbit is"1"thecomparatoroutput isconnectedtoanexternalC1Xpin.If thebit isset to"1"or theC1SELbit is"0" thecomparatoroutputsignal isonlyusedinternallybythedevicesallowingthesharedcomparatoroutputpintoretainitsnormalI/Ooperation.

Bit2~1 Unimplemented,readas"0"Bit0 C1HYEN:HysteresisControl

0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

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Comparator InterruptEachalsopossesses itsowninterrupt function.Whenanyoneof thechangesstate, its relevantinterruptflagwillbeset,andif thecorrespondinginterruptenablebit isset, thena jumpto itsrelevantinterruptvectorwillbeexecuted.NotethatitisthechangingstateoftheC0OUTorC1OUTbitandnottheoutputpinwhichgeneratesaninterrupt.If themicrocontroller is intheSLEEPorIDLEModeandtheComparatorisenabled,thenif theexternalinputlinescausetheComparatoroutputtochangestate, theresultinggeneratedinterruptflagwillalsogenerateawake-up.If it isrequiredtodisableawake-upfromoccurring,thentheinterruptflagshouldbefirstsethighbeforeenteringtheSLEEPorIDLEMode.

Programming ConsiderationsIf thecomparator isenabled, itwillremainactivewhenthemicrocontrollerenters theSLEEPorIDLEMode,howeverasitwillconsumeacertainamountofpower,theusermaywishtoconsiderdisablingitbeforetheSLEEPorIDLEModeisentered.AscomparatorpinsaresharedwithnormalI/OpinstheI/Oregistersforthesepinswillbereadaszero(portcontrolregisteris"1")orreadasportdataregistervalue(portcontrolregisteris"0")ifthecomparatorfunctionisenabled.

Serial Interface Module – SIMThesedevicescontainaSerialInterfaceModule,whichincludesboththefourlineSPIinterfaceorthetwolineI2Cinterfacetypes,toallowaneasymethodofcommunicationwithexternalperipheralhardware.Havingrelativelysimplecommunicationprotocols, theseserial interface typesallowthemicrocontroller to interface toexternalSPIorI2Cbasedhardwaresuchassensors,FlashorEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/OpinsthereforetheSIMinterfacefunctionmustfirstbeselectedusingaconfigurationoption.Asbothinterfacetypessharethesamepinsandregisters,thechoiceofwhethertheSPIorI2CtypeisusedismadeusingtheSIMoperatingmodecontrolbits,namedSIM2~SIM0,intheSIMC0register.Thesepull-highresistorsoftheSIMpin-sharedI/Oareselectedusingpull-highcontrolregisters,andalsoiftheSIMfunctionisenabled.

SPI InterfaceTheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashorEEPROMmemorydevicesetc.OriginallydevelopedbyMotorola, the four lineSPIinterfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunicationisfullduplexandoperatesasaslave/mastertype,wherethedevicescanbeeithermasterorslave.AlthoughtheSPIinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster,butthesedevicesprovidedonlyoneSCSpin.If themasterneedstocontrolmultipleslavedevicesfromasinglemaster,themastercanuseI/Opintoselecttheslavedevices.

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SPI Interface OperationTheSPIinterfaceisafullduplexsynchronousserialdatalink.It isafourlineinterfacewithpinnamesSDI,SDO,SCKandSCS.PinsSDIandSDOare theSerialData InputandSerialDataOutput lines,SCKis theSerialClocklineandSCSis theSlaveSelect line.AstheSPIinterfacepinsarepin-sharedwithotherfunctionsandwiththeI2Cfunctionpins,theSPIinterfacemustfirstbeselectedbythecorrectbits intheSIMC0andSIMC2registers.After theSPIoptionhasbeenselected,itcanalsobeadditionallydisabledorenabledusingtheSIMENbitintheSIMC0register.Communicationbetweendevicesconnected to theSPI interface iscarriedout inaslave/mastermodewithalldatatransferinitiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.AsthedeviceonlycontainsasingleSCSpinonlyoneslavedevicecanbeutilized.TheSCSpiniscontrolledbysoftware,setCSENbitto"1"toenableSCSpinfunction,setCSENbitto"0"theSCSpinwillbefloatingstate.

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SPI Bolck Diagram

Rev. 1.40 14� �ove��e� �� 01� Rev. 1.40 147 �ove��e� �� 01�



TheSPIfunctioninthesedevicesoffersthefollowingfeatures:

• Fullduplexsynchronousdatatransfer

• BothMasterandSlavemodes

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

• WCOLbitenabledordisableselect

ThestatusoftheSPIinterfacepinsisdeterminedbyanumberoffactorssuchaswhetherthedevicesareinthemasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENandSIMEN.

Thereare several configurationoptionsassociatedwith theSPI interface.Oneof these is toenabletheSIMfunctionwhichselects theSIMpinsratherthannormalI/Opins.Notethat if theconfigurationoptiondoesnotselecttheSIMfunctionthentheSIMENbitintheSIMC0registerwillhavenoeffect.AnothertwoSPIconfigurationoptionsdetermineiftheCSENandWCOLbitsaretobeused.

SPI RegistersTherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterface.ThesearetheSIMDdataregisterandtworegistersSIMC0andSIMC2.NotethattheSIMC1registerisonlyusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM� SIM1 SIM0 PCKE� PCKP1 PCKP0 SIME� —SIMD D7 D� D5 D4 D� D� D1 D0

SIMC� D7 D� CKPOLB CKEG MLS CSE� WCOL TRF

SIM Registers List

TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedeviceswritedatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicescanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

• SIMDRegister

Bit 7 6 5 4 3 2 1 0�a�e D7 D� D5 D4 D� D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

"x" unknownTherearealsotwocontrolregistersfortheSPIinterface,SIMC0andSIMC2.NotethattheSIMC2registeralsohasthenameSIMAwhichisusedbytheI2Cfunction.TheSIMC1registerisnotusedbytheSPIfunction,onlybytheI2Cfunction.RegisterSIMC0isusedtocontroltheenable/disablefunctionandtoset thedata transmissionclockfrequency.Althoughnotconnectedwith theSPIfunction,theSIMC0registerisalsousedtocontrolthePeripheralClockPrescaler.RegisterSIMC2isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflagetc.

Rev. 1.40 14� �ove��e� �� 01� Rev. 1.40 147 �ove��e� �� 01�



• SIMC0Register

Bit 7 6 5 4 3 2 1 0�a�e SIM� SIM1 SIM0 PCKE� PCKP1 PCKP0 SIME� —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —

Bit7~5 SIM2, SIM1, SIM0: SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfTBC100:SPImastermode;SPIclockisTM0CCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:NonSIMfunction

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromTM0.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevices.

Bit4 PCKEN:PCKOutputPinControl0:Disable1:Enable

Bit3~2 PCKP1, PCKP0: SelectPCKoutputpinfrequency00:fSYS

01:fSYS/410:fSYS/811:TM0CCRPmatchfrequency/2

Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 Unimplemented,readas"0"

Rev. 1.40 148 �ove��e� �� 01� Rev. 1.40 149 �ove��e� �� 01�



• SIMC2Register

Bit 7 6 5 4 3 2 1 0�a�e D7 D� CKPOLB CKEG MLS CSE� WCOL TRFR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 UndefinedbitThisbitcanbereadorwrittenbytheapplicationprogram.

Bit5 CKPOLB:Determinesthebaseconditionoftheclockline0:theSCKlinewillbehighwhentheclockisinactive1:theSCKlinewillbelowwhentheclockisinactive

TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockisinactive.

Bit4 CKEG:DeterminesSPISCKactiveclockedgetypeCKPOLB=00:SCKishighbaselevelanddatacaptureatSCKrisingedge1:SCKishighbaselevelanddatacaptureatSCKfallingedge

CKPOLB=10:SCKislowbaselevelanddatacaptureatSCKfallingedge1:SCKislowbaselevelanddatacaptureatSCKrisingedge

TheCKEGandCKPOLBbitsareusedtosetupthewaythattheclocksignaloutputsandinputsdataontheSPIbus.Thesetwobitsmustbeconfiguredbeforedatatransferisexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockis inactive.TheCKEGbitdeterminesactiveclockedgetypewhichdependsupontheconditionofCKPOLBbit.

Bit3 MLS:SPIDatashiftorder0:LSB1:MSB

Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,eitherMSBorLSBfirst.SettingthebithighwillselectMSBfirstandlowforLSBfirst.

Bit2 CSEN:SPISCSpinControl0:Disable1:Enable

TheCSENbitisusedasanenable/disablefortheSCSpin.Ifthisbitislow,thentheSCSpinwillbedisabledandplacedintoI/Opinortheotherfunctions.If thebit ishightheSCSpinwillbeenabledandusedasaselectpin.NotethatusingtheCSENbitcanbedisabledorenabledviaconfigurationoption.

Bit1 WCOL:SPIWriteCollisionflag0:Nocollision1:Collision

TheWCOLflagisusedtodetectifadatacollisionhasoccurred.IfthisbitishighitmeansthatdatahasbeenattemptedtobewrittentotheSIMDregisterduringadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thebitcanbeclearedbytheapplicationprogram.NotethatusingtheWCOLbitcanbedisabledorenabledviaconfigurationoption.

Bit0 TRF:SPITransmit/ReceiveCompleteflag0:Dataisbeingtransferred1:SPIdatatransmissioniscompleted

TheTRFbitistheTransmit/ReceiveCompleteflagandisset“1”automaticallywhenanSPIdatatransmissioniscompleted,butmustsetto“0”bytheapplicationprogram.Itcanbeusedtogenerateaninterrupt.

Rev. 1.40 148 �ove��e� �� 01� Rev. 1.40 149 �ove��e� �� 01�



SPI CommunicationAftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,whendataiswrittentotheSIMDregister, transmission/receptionwillbeginsimultaneously.Whenthedata transfer iscomplete, theTRFflagwillbesetautomatically,butmustbeclearedusing theapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedintotheSIMDregister.ThemastershouldoutputanSCSsignal toenable theslavedevicesbeforeaclocksignalisprovided.TheslavedatatobetransferredshouldbewellpreparedattheappropriatemomentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEGbit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignalforvariousconfigurationsoftheCKPOLBandCKEGbits.

TheSPIwillcontinuetofunctionevenintheIDLEMode.

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SPI Master Mode Timing

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SPI Slave Mode Timing – CKEG=0

Rev. 1.40 150 �ove��e� �� 01� Rev. 1.40 151 �ove��e� �� 01�



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SPI Slave Mode Timing – CKEG=1

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SPI Transfer Control Flowchart

Rev. 1.40 150 �ove��e� �� 01� Rev. 1.40 151 �ove��e� �� 01�



I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

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I2C Master Slave Bus Connection

I2C Interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it isthemasterdevicethathasoverallcontrolofthebus.Forthesedevices,whichonlyoperateinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

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I2C Block Diagram

ThereareseveralconfigurationoptionsassociatedwiththeI2Cinterface.OneoftheseistoenablethefunctionwhichselectstheSIMpinsratherthannormalI/Opins.Notethatiftheconfigurationoptiondoesnotselect theSIMfunctionthentheSIMENbit in theSIMC0registerwillhavenoeffect.AconfigurationoptionexiststoallowaclockotherthanthesystemclocktodrivetheI2Cinterface.AnotherconfigurationoptiondeterminesthedebouncetimeoftheI2Cinterface.Thisusestheinternalclocktoineffectaddadebouncetimetotheexternalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.Thedebouncetime, ifselected,canbechosen tobeeither2or4systemclocks.Toachieve therequiredI2Cdata transferspeed, there

Rev. 1.40 15� �ove��e� �� 01� Rev. 1.40 15� �ove��e� �� 01�



existsarelationshipbetweenthesystemclock,fSYS,andtheI2Cdebouncetime.ForeithertheI2CStandardorFastmodeoperation,usersmusttakecareoftheselectedsystemclockfrequencyandtheconfigureddebouncetimetomatchthecriterionshowninthefollowingtable.

I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz)�o de�ounce fSYS > �MHz fSYS > 5MHz� syste� clock de�ounce fSYS > 4MHz fSYS > 10MHz4 syste� clock de�ounce fSYS > 8MHz fSYS > �0MHz

I2C Minimum fSYS Frequency

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I2C RegistersTherearethreecontrolregistersassociatedwiththeI2Cbus,SIMC0,SIMC1andSIMA,andonedataregister,SIMD.TheSIMDregister,whichisshownintheaboveSPIsection,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

NotethattheSIMAregisteralsohasthenameSIMC2whichisusedbytheSPIfunction.BitSIMENandbitsSIM2~SIM0inregisterSIMC0areusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM� SIM1 SIM0 PCKE� PCKP1 PCKP0 SIME� —SIMC1 HCF HA�S HBB HTX TXAK SRW IAMWU RXAKSIMD D7 D� D5 D4 D� D� D1 D0SIMA IICA� IICA5 IICA4 IICA� IICA� IICA1 IICA0 D0

I2C Registers List

Rev. 1.40 15� �ove��e� �� 01� Rev. 1.40 15� �ove��e� �� 01�



• SIMC0Register

Bit 7 6 5 4 3 2 1 0�a�e SIM� SIM1 SIM0 PCKE� PCKP1 PCKP0 SIME� —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —

Bit7~5 SIM2, SIM1, SIM0: SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfTBC100:SPImastermode;SPIclockisTM0CCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:NonSIMfunction

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromtheTM0.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 PCKEN:PCKOutputPinControl0:Disable1:Enable

Bit3~2 PCKP1, PCKP0: SelectPCKoutputpinfrequency00:fSYS


Bit1 SIMEN:SIMControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface, theSDI,SDO,SCKandSCS,orSDAandSCLlineswillbeinafloatingconditionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviaSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.If theSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 Unimplemented,readas"0"

Rev. 1.40 154 �ove��e� �� 01� Rev. 1.40 155 �ove��e� �� 01�



• SIMC1Register

Bit 7 6 5 4 3 2 1 0�a�e HCF HAAS HBB HTX TXAK SRW IAMWU RXAKR/W R R R R/W R/W R R/W RPOR 1 0 0 0 0 0 0 1

Bit7 HCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAAS:I2CBusaddressmatchflag0:Notaddressmatch1:Addressmatch

TheHAASflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 HBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBflagis theI2Cbusyflag.Thisflagwillbe“1”whentheI2Cbus isbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto“0”whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTX:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 TXAK:I2CBustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedonotsendacknowledgeflag

TheTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKbitto“0”beforefurtherdataisreceived.

Bit2 SRW:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheHAASflagissethigh,theslavedevicewillchecktheSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheSRWflagishigh,themasterisrequestingtoreaddatafromthebus,so theslavedeviceshouldbe in transmitmode.WhentheSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 IAMWU:I2CAddressMatchWake-upControl0:Disable1:Enable-mustbeclearedbytheapplicationprogramafterwake-up

Thisbitshouldbesetto1toenabletheI2CaddressmatchwakeupfromtheSLEEPorIDLEMode.IftheIAMWUbithasbeensetbeforeenteringeithertheSLEEPorIDLEmodetoenabletheI2Caddressmatchwakeup,thenthisbitmustbeclearedbytheapplicationprogramafterwake-uptoensurecorrectiondeviceoperation.

Rev. 1.40 154 �ove��e� �� 01� Rev. 1.40 155 �ove��e� �� 01�



Bit0 RXAK:I2CBusReceiveacknowledgeflag0:Slavereceiveacknowledgeflag1:Slavedoesnotreceiveacknowledgeflag

TheRXAKflag is thereceiveracknowledgeflag.WhentheRXAKflag is“0”, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.Theslavetransmitterwill thereforecontinuesendingoutdatauntil theRXAKflagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedeviceswritedatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicescanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

• SIMDRegister

Bit 7 6 5 4 3 2 1 0�a�e D7 D� D5 D4 D� D� D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x X x x x x x x

"x" unknown• SIMARegister

Bit 7 6 5 4 3 2 1 0�a�e IICA� IICA5 IICA4 IICA� IICA� IICA1 IICA0 —R/W R/W R/W R/W R/W R/W R/W R/W —POR x X x x x x x —

"x" unknownBit7~1 IICA6~IICA0:I2Cslaveaddress

IICA6~IICA0istheI2Cslaveaddressbit6~bit0.TheSIMAregister isalsousedbytheSPI interfacebuthas thenameSIMC2.TheSIMAregister is the locationwhere the7-bitslaveaddressof theslavedevice isstored.Bits7~1of theSIMAregisterdefine thedeviceslaveaddress.Bit0 isnotdefined.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheSIMAregister,theslavedevicewillbeselected.NotethattheSIMAregisteristhesameregisteraddressasSIMC2whichisusedbytheSPIinterface.

Bit0 UndefinedbitThisbitcanbereadorwrittenbyusersoftwareprogram.

Rev. 1.40 15� �ove��e� �� 01� Rev. 1.40 157 �ove��e� �� 01�



I2C Bus CommunicationCommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignal isplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theHAASbitintheSIMC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheHAASbittodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfer.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingarestepstoachievethis:

• Step1SettheSIM2~SIM0andSIMENbitsintheSIMC0registerto“1”toenabletheI2Cbus.

• Step2WritetheslaveaddressofthedevicetotheI2CbusaddressregisterSIMA.

• Step3Set theSIMEandSIMMuti-Function interruptenablebitof the interruptcontrol register toenabletheSIMinterruptandMulti-functioninterrupt.

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I2C Bus Initialisation Flow Chart

Rev. 1.40 15� �ove��e� �� 01� Rev. 1.40 157 �ove��e� �� 01�



I2C Bus Start SignalTheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected, this indicates that theI2Cbus isbusyandtherefore theHBBbitwillbeset.ASTARTconditionoccurswhenahigh to lowtransitionon theSDAline takesplacewhentheSCLlineremainshigh.

Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagHAASwhentheaddressesmatch.

Asan I2Cbus interrupt cancome from two sources,when theprogramenters the interruptsubroutine,theHAASbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Bus Read/Write SignalTheSRWbitintheSIMC1registerdefineswhethertheslavedevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheSRWflagis“1”thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheSRWflagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

I2C Bus Slave Address Acknowledge SignalAfter themasterhas transmitted a calling address, any slavedeviceon the I2Cbus,whoseown internaladdressmatches thecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheSRWflagtodetermineifitistobeatransmitterorareceiver.IftheSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1registershouldbesetto“1”.IftheSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.

Rev. 1.40 158 �ove��e� �� 01� Rev. 1.40 159 �ove��e� �� 01�



I2C Bus Data and Acknowledge SignalThe transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver, thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMDregister.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintotheSIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasTXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbitintheSIMC1registertodetermineifit istosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

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Note:*Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Communication Timing Diagram

Rev. 1.40 158 �ove��e� �� 01� Rev. 1.40 159 �ove��e� �� 01�



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I2C Bus ISR flow Chart

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



Peripheral Clock OutputThePeripheralClockOutputallowsthedevice tosupplyexternalhardwarewithaclocksignalsynchronisedtothemicrocontrollerclock.

Peripheral Clock OperationAstheperipheralclockoutputpin,PCK,issharedwithI/Oline,therequiredpinfunctionischosenviaPCKENintheSIMC0register.ThePeripheralClockfunctioniscontrolledusingtheSIMC0register.Theclocksourcefor thePeripheralClockOutputcanoriginatefromeither theTM0CCRPmatchfrequency/2oradividedratiooftheinternalfSYSclock.ThePCKENbitintheSIMC0registeristheoverallon/offcontrol,settingPCKENbitto"1"enablesthePeripheralClock,settingPCKENbitto"0"disablesit.TherequireddivisionratioofthesystemclockisselectedusingthePCKP1andPCKP0bitsinthesameregister.IfthedeviceenterstheSLEEPModethiswilldisablethePeripheralClockoutput.

SIMC0 RegisterBit 7 6 5 4 3 2 1 0

�a�e SIM� SIM1 SIM0 PCKE� PCKP1 PCKP0 SIME� —R/W R/W R/W R/W R/W R/W R/W R/W —POR 1 1 1 0 0 0 0 —

Bit7~5 SIM2,SIM1, SIM0:SIMoperatingmodecontrol000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfTBC100:SPImastermode;SPIclockisTM0CCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:Unusedmode

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbutcanalsobechosentobesourcedfromtheTM0.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 PCKEN:PCKoutputpincontrol0:Disable1:Enable

Bit3~2 PCKP1, PCKP0:selectPCKoutputpinfrequency00:fSYS


Bit1 SIMEN:SIMcontrol0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface, theSDI,SDO,SCKandSCS,orSDAandSCLlineswillbeinafloatingconditionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.NotethatwhentheSIMENbitchangesfromlowtohighthecontentsoftheSPIcontrolregisterswillbe inanunknownconditionandshouldthereforebefirstinitialisedbytheapplicationprogram.

Bit0 unimplemented,readas"0"

Rev. 1.40 1�0 �ove��e� �� 01� Rev. 1.40 1�1 �ove��e� �� 01�



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thesedevicescontainseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptsaregeneratedbytheactionoftheexternalINT0~INT1andPINTpins,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,Comparators,TimeBase,LVD,EEPROM,SIMandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfall intothreecategories.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI2registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlo�al EMI — —Co�pa�ato� CPnE CPnF n=0 o� 1I�Tn Pin I�TnE I�TnF n=0~1A/D Conve�te� ADE ADF HT��F�0-1/HT��F�0-1 onlyMulti-function MFnE MFnF n=0~�Ti�e Base TBnE TBnF n=0 o� 1SIM SIME SIMF —LVD LVE LVF —EEPROM DEE DEF —PI�T Pin XPE XPF —

TMTnPE TnPF

n=0~1TnAE TnAFTnBE TnBF n=1

Interrupt Register Bit Naming Conventions

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



Interrupt Register Contents• HT66F20-1

NameBit

7 6 5 4 3 2 1 0I�TEG — — — — I�T1S1 I�T1S0 I�T0S1 I�T0S0I�TC0 — CP0F I�T1F I�T0F CP0E I�T1E I�T0E EMII�TC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1EI�TC� MF�F TB1F TB0F MF�F MF�E TB1E TB0E MF�EMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — — T1AF T1PF — — T1AE T1PEMFI� DEF LVF XPF SIMF DEE LVE XPE SIME

• HT66F30-1

NameBit

7 6 5 4 3 2 1 0I�TEG — — — — I�T1S1 I�T1S0 I�T0S1 I�T0S0I�TC0 — CP0F I�T1F I�T0F CP0E I�T1E I�T0E EMII�TC1 ADF MF1F MF0F CP1F ADE MF1E MF0E CP1EI�TC� MF�F TB1F TB0F MF�F MF�E TB1E TB0E MF�EMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — T1BF T1AF T1PF — T1BE T1AE T1PEMFI� DEF LVF XPF SIMF DEE LVE XPE SIME

• HT68F20-1

NameBit

7 6 5 4 3 2 1 0I�TEG — — — — I�T1S1 I�T1S0 I�T0S1 I�T0S0I�TC0 — CP0F I�T1F I�T0F CP0E I�T1E I�T0E EMII�TC1 — MF1F MF0F CP1F — MF1E MF0E CP1EI�TC� MF�F TB1F TB0F MF�F MF�E TB1E TB0E MF�EMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — — T1AF T1PF — — T1AE T1PEMFI� DEF LVF XPF SIMF DEE LVE XPE SIME

• HT68F30-1

NameBit

7 6 5 4 3 2 1 0I�TEG — — — — I�T1S1 I�T1S0 I�T0S1 I�T0S0I�TC0 — CP0F I�T1F I�T0F CP0E I�T1E I�T0E EMII�TC1 — MF1F MF0F CP1F — MF1E MF0E CP1EI�TC� MF�F TB1F TB0F MF�F MF�E TB1E TB0E MF�EMFI0 — — T0AF T0PF — — T0AE T0PEMFI1 — T1BF T1AF T1PF — T1BE T1AE T1PEMFI� DEF LVF XPF SIMF DEE LVE XPE SIME

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�� ove��e� �� 01�



INTEG Register

Bit 7 6 5 4 3 2 1 0�a�e — — — — I�T1S1 I�T1S0 I�T0S1 I�T0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0”Bit3~2 INT1S1,INT1S0:interruptedgecontrolforINT1pin

00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

Bit1~0 INT0S1,INT0S0:interruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

INTC0 Register

Bit 7 6 5 4 3 2 1 0�a�e — CP0F I�T1F I�T0F CP0E I�T1E I�T0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 CP0F:Comparator0InterruptRequestFlag

0:Norequest1:Interruptrequest

Bit5 INT1F:INT1interruptrequestflag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0interruptrequestflag0:Norequest1:Interruptrequest

Bit3 CP0E:Comparator0InterruptControl0:Disable1:Enable

Bit2 INT1E:INT1interruptcontrol0:Disable1:Enable

Bit1 INT0E:INT0interruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

Rev. 1.40 1�4 �ove��e� �� 01� Rev. 1.40 1�5 �ove��e� �� 01�



INTC1 Register• HT66F20-1/HT66F30-1

Bit 7 6 5 4 3 2 1 0�a�e ADF MF1F MF0F CP1F ADE MF1E MF0E CP1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 MF1F:Multi-functionInterrupt1RequestFlag0:Norequest1:Interruptrequest


Bit4 CP1F:Comparator1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 ADE:A/DConverterInterruptInterruptControl0:Disable1:Enable

Bit2 MF1E:Multi-functionInterrupt1Control0:Disable1:Enable



Rev. 1.40 1�4 �ove��e� �� 01� Rev. 1.40 1�5 �ove��e� �� 01�



• HT68F20-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — MF1F MF0F CP1F — MF1E MF0E CP1ER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplenented,readas"0"Bit6 MF1F:Multi-functionInterrupt1RequestFlag

0:Norequest1:Interruptrequest


Bit4 CP1F:Comparator1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 Unimplenented,readas"0"Bit2 MF1E:Multi-functionInterrupt1Control

0:Disable1:Enable



Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�7 �ove��e� �� 01�



INTC2 Register

Bit 7 6 5 4 3 2 1 0�a�e MF�F TB1F TB0F MF�F MF�E TB1E TB0E MF�ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0


Bit6 TB1F:TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest



Bit2 TB1E:TimeBase1InterruptControl0:Disable1:Enable

Bit1 TB0E:TimeBase0InterruptControl0:Disable1:Enable


MFI0 Register

Bit 7 6 5 4 3 2 1 0�a�e — — T0AF T0PF — — T0AE T0PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 T0AF:TM0ComparatorAmatchinterruptrequestflag

0:norequest1:interruptrequest

Bit4 T0PF:TM0ComparatorPmatchinterruptrequestflag0:norequest1:interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 T0AE:TM0ComparatorAmatchinterruptcontrol

0:disable1:enable

Bit0 T0PE:TM0ComparatorPmatchinterruptcontrol0:disable1:enable

Rev. 1.40 1�� ove��e� �� 01� Rev. 1.40 1�7 �ove��e� �� 01�



MFI1 Register• HT66F20-1/HT68F20-1

Bit 7 6 5 4 3 2 1 0�a�e — — T1AF T1PF — — T1AE T1PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 T1AF:TM1ComparatorAmatchinterruptrequestflag



Bit3~2 Unimplemented,readas"0"Bit1 T1AE:TM1ComparatorAmatchinterruptcontrol

0:disable1:enable


• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e — T1BF T1AF T1PF — T1BE T1AE T1PER/W — R/W R/W R/W — R/W R/W R/WPOR — 0 0 0 — 0 0 0

Bit7 Unimplemented,readas"0"Bit6 T1BF:TM1ComparatorBmatchinterruptrequestflag


Bit5 T1AF:TM1ComparatorAmatchinterruptrequestflag0:norequest1:interruptrequest


Bit3 Unimplemented,readas"0"Bit2 T1BE:TM1ComparatorBmatchinterruptcontrol

0:disable1:enable

Bit1 T1AE:TM1ComparatorAmatchinterruptcontrol0:disable1:enable


Rev. 1.40 1�8 �ove��e� �� 01� Rev. 1.40 1�9 �ove��e� �� 01�



MFI2 Register

Bit 7 6 5 4 3 2 1 0�a�e DEF LVF XPF SIMF DEE LVE XPE SIMER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 DEF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 XPF:Externalperipheralinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 SIMF:SIMinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 DEE:DataEEPROMInterruptControl0:Disable1:Enable

Bit2 LVE:LVDInterruptControl0:Disable1:Enable

Bit1 XPE:ExternalPeripheralInterruptControl0:Disable1:Enable

Bit0 SIME:SIMInterruptControl0:Disable1:Enable

Rev. 1.40 1�8 �ove��e� �� 01� Rev. 1.40 1�9 �ove��e� �� 01�



Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMCompareP,CompareAorCompareBmatchorA/Dconversioncompletionetc,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.40 170 �ove��e� �� 01� Rev. 1.40 171 �ove��e� �� 01�



04H

08H

0CH

10H

14H

18H

1CH

�0H

�4H

�8H

Vector

Low

P�io�ityHigh

RequestFlags

Ena�leBits

Maste�Ena�le

RequestFlags

Ena�leBits

EMI auto disa�led in ISR

Inte��upts contained withinMulti-Function Inte��upts

Inte��upt�a�e


MF�FM. Funct. � MF�E

XPFPI�T Pin XPE

EMI �CH

LVFLVD LVE

DEFEEPROM DEE

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

SIMFSIM SIME

T1BFTM1 B T1BE

T1AFTM1 A T1AE

T1PFTM1 P T1PE

T0AFTM0 A T0AE

T0PFTM0 P T0PE

I�T0FI�T0 Pin I�T0E


CP0FCo�p. 0 CP0E

CP1FCo�p. 1 CP1E

MF0FM. Funct. 0 MF0E


ADFA/D ADE EMI


TB0FTi�e Base 0 TB0E


xxF

Legend

Request Flag – no auto �eset in ISR

xxF Request Flag – auto �eset in ISR

xxE Ena�le Bit

Interrupt Structure – HT66F20-1/HT66F30-1

Rev. 1.40 170 �ove��e� �� 01� Rev. 1.40 171 �ove��e� �� 01�



04H

08H

0CH

10H

14H

18H

�0H

�4H

�8H

Vector

Low

P�io�ityHigh

RequestFlags

Ena�leBits

Maste�Ena�le

RequestFlags

Ena�leBits

EMI auto disa�led in ISR

Inte��upts contained withinMulti-Function Inte��upts




XPFPI�T Pin XPE

EMI �CH

LVFLVD LVE

DEFEEPROM DEE

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

EMI

SIMFSIM SIME

T1BFTM1 B T1BE

T1AFTM1 A T1AE

T1PFTM1 P T1PE

T0AFTM0 A T0AE

T0PFTM0 P T0PE



CP0FCo�p. 0 CP0E

CP1FCo�p. 1 CP1E






xxF

Legend

Request Flag – no auto �eset in ISR

xxF Request Flag – auto �eset in ISR

xxE Ena�le Bit

Interrupt Structure – HT68F20-1/HT68F30-1

Rev. 1.40 17� �ove��e� �� 01� Rev. 1.40 17� �ove��e� �� 01�



External InterruptTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT1.Anexternalinterruptrequestwill takeplacewhentheexternal interruptrequestflags,INT0F~INT1Fareset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INT0E~INT1E,mustfirstbeset.AdditionallythecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins, theycanonlybeconfiguredasexternal interruptpins if theirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Comparator InterruptThecomparator interruptsarecontrolledbythetwointernalcomparators.Acomparator interruptrequestwill takeplacewhen thecomparator interrupt request flags,CP0ForCP1F,areset,asituationthatwilloccurwhenthecomparatoroutputchangesstate.Toallowtheprogramtobranchto its respective interruptvectoraddress, theglobal interruptenablebit,EMI,andcomparatorinterruptenablebits,CP0EandCP1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutputtransition,asubroutinecalltothecomparatorinterruptvector,willtakeplace.Whentheinterruptisserviced,thecomparatorinterruptrequestflags,CP0FandCP1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Multi-function InterruptWithinthesedevicesarefourMulti-functioninterrupts.Unlike theother independent interrupts,these interruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts,SIMInterrupt,ExternalPeripheralInterrupt,LVDinterruptandEEPROMInterrupt.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MF0F~MF3Fareset.TheMulti-functioninterruptflagswillbesetwhenanyoftheirincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflag,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMInterrupts,SIMInterrupt,ExternalPeripheralInterrupt,LVDinterruptandEEPROMInterruptwillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

Rev. 1.40 17� �ove��e� �� 01� Rev. 1.40 17� �ove��e� �� 01�



A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

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TBC Register

Bit 7 6 5 4 3 2 1 0�a�e TBO� TBCK TB11 TB10 LXTLP TB0� TB01 TB00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 1 0 1 1 1

Bit7 TBON:TB0andTB1Control0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11~TB10:SelectTimeBase1Time-outPeriod00:4096/fTB01:8192/fTB10:16384/fTB11:32768/fTB

Bit3 LXTLP:LXTLowPowerControl0:Disable1:Enable

Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod000:256/fTB001:512/fTB010:1024/fTB011:2048/fTB100:4096/fTB101:8192/fTB110:16384/fTB111:32768/fTB

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Time Base Interrupts

Rev. 1.40 174 �ove��e� �� 01� Rev. 1.40 175 �ove��e� �� 01�



Serial Interface Module InterruptsTheSerial InterfaceModuleInterrupt,alsoknownas theSIMinterrupt, iscontainedwithin theMulti-functionInterrupt.ASIMInterruptrequestwill takeplacewhentheSIMInterruptrequestflag,SIMF,isset,whichoccurswhenabyteofdatahasbeenreceivedortransmittedbytheSIMinterface.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobalinterruptenablebit,EMI,andtheSerialInterfaceInterruptenablebit,SIME,andMuti-functioninterruptenablebits,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheSIMinterface,asubroutinecall totherespectiveMulti-functionInterruptvector,willtakeplace.WhentheSerialInterfaceInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheSIMFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

External Peripheral InterruptTheExternalPeripheralInterruptoperatesinasimilarwaytotheexternalinterruptandiscontainedwithintheMulti-functionInterrupt.APeripheralInterruptrequestwilltakeplacewhentheExternalPeripheralInterruptrequestflag,XPF,isset,whichoccurswhenanegativeedgetransitionappearson thePINTpin.Toallowtheprogramtobranch to its respective interruptvectoraddress, theglobal interruptenablebit,EMI,externalperipheral interruptenablebit,XPE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanegativetransitionappearsontheExternalPeripheralInterruptpin,asubroutinecall totherespectiveMulti-functionInterrupt,will takeplace.WhentheExternalPeripheralInterruptisserviced, theEMIbitwillbeautomaticallyclearedtodisableother interrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.

AstheXPFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.Theexternalperipheralinterruptpinispin-sharedwithseveralotherpinswithdifferentfunctions.ItmustthereforebeproperlyconfiguredtoenableittooperateasanExternalPeripheralInterruptpin.

EEPROM InterruptTheEEPROMInterrupt, iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMwriteorreadcycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobalinterruptenablebit,EMI,EEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMwriteorreadcycleends,asubroutinecall totherespectiveMulti-functionInterruptvector,will takeplace.When theEEPROMInterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

Rev. 1.40 17� �ove��e� �� 01� Rev. 1.40 177 �ove��e� �� 01�



LVD InterruptTheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.AnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequest flag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM InterruptsTheCompactandStandardTMeachhas twointerrupts,while theEnhancedTypeTMhasthreeinterrupts.Allof theTMinterruptsarecontainedwithin theMulti-functionInterrupts.For theCompactandStandardTypeTMthereare twointerrupt request flagsTnPFandTnAFandtwoenablebitsTnPEandTnAE.FortheEnhancedTypeTMtherearethreeinterruptrequestflagsTnPF,TnAFandTnBFandthreeenablebitsTnPE,TnAEandTnBE.ATMinterruptrequestwill takeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorP,AorBmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthesedevicesare in theSLEEPor IDLEModeand its systemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycause theirrespectiveinterruptflag tobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Rev. 1.40 17� �ove��e� �� 01� Rev. 1.40 177 �ove��e� �� 01�



Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptserviceroutineisexecuted,asonlytheMulti-functioninterruptrequestflags,MF0F~MF3F,willbeautomaticallycleared, the individualrequestflagfor thefunctionneeds tobeclearedbytheapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

EveryinterrupthasthecapabilityofwakingupthemicrocontrollerwhenitisintheSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.40 178 �ove��e� �� 01� Rev. 1.40 179 �ove��e� �� 01�



Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0�a�e — — LVDO LVDE� — VLVD� VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Bit3 Unimplemented,readas"0"Bit2~0 VLVD2~VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.4V

Rev. 1.40 178 �ove��e� �� 01� Rev. 1.40 179 �ove��e� �� 01�



LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.4V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceispowereddownthelowvoltagedetectorwillremainactiveiftheLVDENbitishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

LVD Operation

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TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveiftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

Rev. 1.40 180 �ove��e� �� 01� Rev. 1.40 181 �ove��e� �� 01�



SCOM Function for LCDThedeviceshavethecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM3,arepinsharedwithcertainpinon thePC0~PC1,PC6~PC7port.TheLCDsignals(COMandSEG)aregeneratedusingtheapplicationprogram.

LCD OperationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguringthePC0~PC1,PC6~PC7pinsascommonpinsandusingotheroutputportslinesassegmentpins.TheLCDdriverfunctioniscontrolledusingtheSCOMCregisterwhichinadditiontocontrollingtheoverallon/offfunctionalsocontrols thebiasvoltagesetupfunction.Thisenables theLCDCOMdriver togenerate thenecessaryVDD/2voltagelevelsforLCD1/2biasoperation.

TheSCOMENbitintheSCOMCregisteristheoverallmastercontrolfortheLCDdriver,howeverthisbitisusedinconjunctionwiththeCOMnENbitstoselectwhichPortCpinsareusedforLCDdriving.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.

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LCD COM Bias

SCOMEN COMnEN Pin Function O/P Level0 X I/O 0 o� 11 0 I/O 0 o� 11 1 SCOMn VDD/�

Output Control

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LCD Bias ControlTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhichisbeingused.ThebiasresistorchoiceisimplementedusingtheISEL1andISEL0bitsintheSCOMCregister.

SCOMC Register• HT66F30-1/HT68F30-1

Bit 7 6 5 4 3 2 1 0�a�e D7 ISEL1 ISEL0 SCOME� COM�E� COM�E� COM1E� COM0E�R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 ReservedBit0:Correctlevel-bitmustberesettozeroforcorrectoperation1:Unpredictableoperation-bitmustnotbesethigh

Bit6~5 ISEL1, ISEL0:SelectSCOMtypicalbiascurrent(VDD=5V)00:25μA01:50μA10:100μA11:200μA

Bit4 SCOMEN:SCOMmoduleControl0:Disable1:Enable

Bit3 COM3EN:PC7orSCOM3selection0:GPIO1:SCOM3




Rev. 1.40 18� �ove��e� �� 01� Rev. 1.40 18� �ove��e� �� 01�



Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedevicesduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopmenttools.Astheseoptionsareprogrammedintothedevicesusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Options

1High Speed Syste� Oscillato� Selection - fH: 1. HXT �. ERC �. HIRC

�Low Speed Syste� Oscillato� Selection - fSUB: 1. LXT �. LIRC

�WDT Clock Selection - fS: 1. fSUB �. fSYS/4

4HIRC F�equency Selection: 1. 4MHz �. 8MHz �. 1�MHz

�ote: The fSUB and the fTBC clock sou�ce a�e LXT o� LIRC selection �y the fL configuration option.Reset Pin Options

5PB0/RES Pin Options: 1. RES pin �. I/O pin

Watchdog Options

�Watchdog Ti�e� Function: 1. Ena�le �. Disa�le

7CLR WDT Inst�uctions Selection: 1. 1 inst�uctions �. � inst�uctions

LVR Options

8LVR Function: 1. Ena�le �. Disa�le

9

LVR Voltage Selection: 1. �.10V �. �.55V �. �.15V 4. 4.�0V

SIM Options

10SIM Function: 1. Ena�le �. Disa�le

11SPI - WCOL �it: 1. Ena�le �. Disa�le

1�SPI - CSE� �it: 1. Ena�le �. Disa�le

1�I�C De�ounce Ti�e Selection: 1. �o de�ounce �. � syste� clock de�ounce �. 4 syste� clock de�ounce

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Application Circuits

HT66F20-1/HT66F30-1

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Note:"*":ItisrecommendedthatthiscomponentisaddedforaddedESDprotection."**":Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

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HT68F20-1/HT68F30-1

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Rev. 1.40 184 �ove��e� �� 01� Rev. 1.40 185 �ove��e� �� 01�



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

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Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[�] Add Data Me�o�y to ACC 1 Z� C� AC� OVADDM A�[�] Add ACC to Data Me�o�y 1�ote Z� C� AC� OVADD A�x Add i��ediate data to ACC 1 Z� C� AC� OVADC A�[�] Add Data Me�o�y to ACC with Ca��y 1 Z� C� AC� OVADCM A�[�] Add ACC to Data �e�o�y with Ca��y 1�ote Z� C� AC� OVSUB A�x Su�t�act i��ediate data f�o� the ACC 1 Z� C� AC� OVSUB A�[�] Su�t�act Data Me�o�y f�o� ACC 1 Z� C� AC� OVSUBM A�[�] Su�t�act Data Me�o�y f�o� ACC with �esult in Data Me�o�y 1�ote Z� C� AC� OVSBC A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y 1 Z� C� AC� OVSBCM A�[�] Su�t�act Data Me�o�y f�o� ACC with Ca��y� �esult in Data Me�o�y 1�ote Z� C� AC� OVDAA [�] Deci�al adjust ACC fo� Addition with �esult in Data Me�o�y 1�ote CLogic OperationA�D A�[�] Logical A�D Data Me�o�y to ACC 1 ZOR A�[�] Logical OR Data Me�o�y to ACC 1 ZXOR A�[�] Logical XOR Data Me�o�y to ACC 1 ZA�DM A�[�] Logical A�D ACC to Data Me�o�y 1�ote ZORM A�[�] Logical OR ACC to Data Me�o�y 1�ote ZXORM A�[�] Logical XOR ACC to Data Me�o�y 1�ote ZA�D A�x Logical A�D i��ediate Data to ACC 1 ZOR A�x Logical OR i��ediate Data to ACC 1 ZXOR A�x Logical XOR i��ediate Data to ACC 1 ZCPL [�] Co�ple�ent Data Me�o�y 1�ote ZCPLA [�] Co�ple�ent Data Me�o�y with �esult in ACC 1 ZIncrement & DecrementI�CA [�] Inc�e�ent Data Me�o�y with �esult in ACC 1 ZI�C [�] Inc�e�ent Data Me�o�y 1�ote ZDECA [�] Dec�e�ent Data Me�o�y with �esult in ACC 1 ZDEC [�] Dec�e�ent Data Me�o�y 1�ote ZRotateRRA [�] Rotate Data Me�o�y �ight with �esult in ACC 1 �oneRR [�] Rotate Data Me�o�y �ight 1�ote �oneRRCA [�] Rotate Data Me�o�y �ight th�ough Ca��y with �esult in ACC 1 CRRC [�] Rotate Data Me�o�y �ight th�ough Ca��y 1�ote CRLA [�] Rotate Data Me�o�y left with �esult in ACC 1 �oneRL [�] Rotate Data Me�o�y left 1�ote �oneRLCA [�] Rotate Data Me�o�y left th�ough Ca��y with �esult in ACC 1 CRLC [�] Rotate Data Me�o�y left th�ough Ca��y 1�ote C

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Mnemonic Description Cycles Flag AffectedData MoveMOV A�[�] Move Data Me�o�y to ACC 1 �oneMOV [�]�A Move ACC to Data Me�o�y 1�ote �oneMOV A�x Move i��ediate data to ACC 1 �oneBit OperationCLR [�].i Clea� �it of Data Me�o�y 1�ote �oneSET [�].i Set �it of Data Me�o�y 1�ote �oneBranchJMP add� Ju�p unconditionally � �oneSZ [�] Skip if Data Me�o�y is ze�o 1�ote �oneSZA [�] Skip if Data Me�o�y is ze�o with data �ove�ent to ACC 1�ote �oneSZ [�].i Skip if �it i of Data Me�o�y is ze�o 1�ote �oneS�Z [�].i Skip if �it i of Data Me�o�y is not ze�o 1�ote �oneSIZ [�] Skip if inc�e�ent Data Me�o�y is ze�o 1�ote �oneSDZ [�] Skip if dec�e�ent Data Me�o�y is ze�o 1�ote �oneSIZA [�] Skip if inc�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneSDZA [�] Skip if dec�e�ent Data Me�o�y is ze�o with �esult in ACC 1�ote �oneCALL add� Su��outine call � �oneRET Retu�n f�o� su��outine � �oneRET A�x Retu�n f�o� su��outine and load i��ediate data to ACC � �oneRETI Retu�n f�o� inte��upt � �oneTable ReadTABRDC [�] Read ta�le to TBLH and Data Me�o�y ��ote �oneTABRDL [�] Read ta�le (last page) to TBLH and Data Me�o�y ��ote �oneMiscellaneous�OP �o ope�ation 1 �oneCLR [�] Clea� Data Me�o�y 1�ote �oneSET [�] Set Data Me�o�y 1�ote �oneCLR WDT Clea� Watchdog Ti�e� 1 TO� PDFCLR WDT1 P�e-clea� Watchdog Ti�e� 1 TO� PDFCLR WDT� P�e-clea� Watchdog Ti�e� 1 TO� PDFSWAP [�] Swap ni��les of Data Me�o�y 1�ote �oneSWAPA [�] Swap ni��les of Data Me�o�y with �esult in ACC 1 �oneHALT Ente� powe� down �ode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.40 198 �ove��e� �� 01� Rev. 1.40 199 �ove��e� �� 01�



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• PackingMeterialsInformation

• Cartoninformation

http://www.holtek.com

http://www.holtek.com.tw/english/literature/package.pdf

http://www.holtek.com.tw/english/literature/packing-e.pdf

http://www.holtek.com.tw/english/literature/carton.pdf

Rev. 1.40 198 �ove��e� �� 01� Rev. 1.40 199 �ove��e� �� 01�



16-pin DIP (300mil) Outline Dimensions

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Fig1. Full Lead Packages Fig1. 1/2 Lead Packages

Fig 1

SymbolDimensions in inch

Min. Nom. Max.A 0.780 0.790 0.800 B 0.�40 0.�50 0.�80 C 0.115 0.1�0 0.195 D 0.115 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.0�0 0.070 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0

SymbolDimensions in mm

Min. Nom. Max.A 19.81 �0.07 �0.�� B �.10 �.�5 7.11C �.9� �.�0 4.95D �.9� �.�0 �.81E 0.�� 0.4� 0.5�F 1.14 1.5� 1.78G — �.54 BSC —H 7.�� 7.87 8.��I — — 10.9�

Rev. 1.40 �00 �ove��e� �� 01� Rev. 1.40 �01 �ove��e� �� 01�



Fig 2


Min. Nom. Max.A 0.745 0.7�5 0.785 B 0.�75 0.�85 0.�95 C 0.1�0 0.1�5 0.150 D 0.110 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.050 0.0�0 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0


Min. Nom. Max.A 18.9� 19.4� 19.94 B �.99 7.�4 7.49 C �.05 �.4� �.81 D �.79 �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.�7 1.5� G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

Fig 2


Min. Nom. Max.A 0.7�5 0.755 0.775 B 0.�40 0.�50 0.�80 C 0.115 0.1�0 0.195 D 0.115 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.0�0 0.070 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0


Min. Nom. Max.A 18.�7 19.18 19.�9 B �.10 �.�5 7.11 C �.9� �.�0 4.95 D �.9� �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.5� 1.78 G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

Rev. 1.40 �00 �ove��e� �� 01� Rev. 1.40 �01 �ove��e� �� 01�



16-pin NSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�� BSC —B — 0.154 BSC —C 0.01� — 0.0�0 C' — 0.�90 BSC —D — — 0.0�9 E — 0.050 BSC —F 0.004 — 0.010 G 0.01� — 0.050 H 0.004 — 0.010 α 0° ― 8°


Min. Nom. Max.A — �.000 BSC —B — �.900 BSC —C 0.�1 — 0.51 C' — 9.900 BSC —D — — 1.75 E — 1.�70 BSC —F 0.10 — 0.�5 G 0.40 — 1.�7 H 0.10 — 0.�5 α 0° ― 8°

Rev. 1.40 �0� �ove��e� �� 01� Rev. 1.40 �0� �ove��e� �� 01�



16-pin SSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�� BSC —B — 0.154 BSC —C 0.008 — 0.01� C’ — 0.19� BSC —D — — 0.0�9 E — 0.0�5 BSC —F 0.004 — 0.010 G 0.01� — 0.050 H 0.004 — 0.010α 0° — 8°


Min. Nom. Max.A — �.000 BSC —B — �.900 BSC —C 0.�0 — 0.�0 C’ — 4.900 BSC —D — — 1.75 E — 0.��5 BSC —F 0.10 — 0.�5 G 0.41 — 1.�7 H 0.10 — 0.�5 α 0° — 8°

Rev. 1.40 �0� �ove��e� �� 01� Rev. 1.40 �0� �ove��e� �� 01�



20-pin DIP (300mil) Outline Dimensions

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See Fig1


Min. Nom. Max.A 0.980 1.0�0 1.0�0 B 0.�40 0.�50 0.�80 C 0.115 0.1�0 0.195 D 0.115 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.0�0 0.070 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0


Min. Nom. Max.A �4.89 ��.1� ��.9� B �.10 �.�5 7.11C �.9� �.�0 4.95D �.9� �.�0 �.81E 0.�� 0.4� 0.5�F 1.14 1.5� 1.78G — �.54 BSC —H 7.�� 7.87 8.��I — — 10.9�

Rev. 1.40 �04 �ove��e� �� 01� Rev. 1.40 �05 �ove��e� �� 01�



See Fig 2


Min. Nom. Max.A 0.945 0.9�5 0.985 B 0.�75 0.�85 0.�95 C 0.1�0 0.1�5 0.150 D 0.110 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.050 0.0�0 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0


Min. Nom. Max.A �4.00 �4.51 �5.0� B �.99 7.�4 7.49C �.05 �.4� �.81D �.79 �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.�7 1.5� G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

Rev. 1.40 �04 �ove��e� �� 01� Rev. 1.40 �05 �ove��e� �� 01�



20-pin SOP (300mil) Outline Dimensions

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Min. Nom. Max.A — 0.40� BSC —B — 0.�95 BSC —C 0.01� — 0.0�0 C’ — 0.504 BSC —D — — 0.104 E — 0.050 BSC —F 0.004 — 0.01� G 0.01� — 0.050 H 0.008 — 0.01� α 0° — 8°


Min. Nom. Max.A — 10.�0 BSC —B — 7.50 BSC —C 0.�1 — 0.51 C’ — 1�.80 BSC —D — — �.�5 E — 1.�7 BSC —F 0.10 — 0.�0 G 0.40 — 1.�7 H 0.�0 — 0.�� α 0° — 8°

Rev. 1.40 �0� �ove��e� �� 01� Rev. 1.40 �07 �ove��e� �� 01�



20-pin SSOP (150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�� BSC —B — 0.155 BSC —C 0.008 — 0.01� C’ — 0.�41 BSC —D — — 0.0�9 E — 0.0�5 BSC —F 0.004 — 0.0098 G 0.01� — 0.05 H 0.004 — 0.01 α 0° — 8°


Min. Nom. Max.A — �.000 BSC —B — �.900 BSC —C 0.�0 — 0.�0 C’ — 8.��0 BSC —D — — 1.75 E — 0.��5 BSC —F 0.10 — 0.�5 G 0.41 — 1.�7 H 0.10 — 0.�5 α 0° — 8°

Rev. 1.40 �0� �ove��e� �� 01� Rev. 1.40 �07 �ove��e� �� 01�



24-pin SKDIP (300mil) Outline Dimensions

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See Fig1

Symbol Dimensions in inchMin. Nom. Max.

A 1.��0 1.�50 1.�80 B 0.�40 0.�50 0.�80 C 0.115 0.1�0 0.195 D 0.115 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.0�0 0.070 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0

Symbol Dimensions in mmMin. Nom. Max.

A �1.�4 �1.75 ��.51 B �.10 �.�5 7.11 C �.9� �.�0 4.95 D �.9� �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.5� 1.78 G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

Rev. 1.40 �08 �ove��e� �� 01� Rev. 1.40 �09 �ove��e� �� 01�



See Fig2


A 1.1�0 1.185 1.195 B 0.�40 0.�50 0.�80 C 0.115 0.1�0 0.195 D 0.115 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.0�0 0.070 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0


Min. Nom. Max.A �9.4� �0.10 �0.�5 B �.10 �.�5 7.11 C �.9� �.�0 4.95 D �.9� �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.5� 1.78 G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

See fig20


A 1.145 1.1�5 1.185 B 0.�75 0.�85 0.�95 C 0.1�0 0.1�5 0.150 D 0.110 0.1�0 0.150 E 0.014 0.018 0.0�� F 0.045 0.050 0.0�0 G — 0.100 BSC —H 0.�00 0.�10 0.��5 I — — 0.4�0

Symbol Dimensions in mmMin. Nom. Max.

A �9.08 �9.59 �0.10 B �.99 7.�4 7.49 C �.05 �.4� �.81 D �.79 �.�0 �.81 E 0.�� 0.4� 0.5� F 1.14 1.�7 1.5� G — �.54 BSC —H 7.�� 7.87 8.�� I — — 10.9�

Rev. 1.40 �08 �ove��e� �� 01� Rev. 1.40 �09 �ove��e� �� 01�



24-pin SOP (300mil) Outline Dimensions

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Min. Nom. Max.A — 0.40� BSC —B — 0.�95 BSC —C 0.01� — 0.0�0 C’ — 0.�0� BSC —D — — 0.104 E — 0.050 BSC —F 0.004 — 0.01� G 0.01� — 0.050 H 0.008 — 0.01� α 0° — 8°


Min. Nom. Max.A — 10.�0 BSC —B — 7.50 BSC —C 0.�1 — 0.51 C’ — 15.40 BSC —D — — �.�5 E — 1.�7 BSC —F 0.10 — 0.�0 G 0.40 — 1.�7 H 0.�0 — 0.�� α 0° ― 8°

Rev. 1.40 �10 �ove��e� �� 01� Rev. 1.40 �11 �ove��e� �� 01�



24-pin SSOP(150mil) Outline Dimensions

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Min. Nom. Max.A — 0.�� BSC —B — 0.154 BSC —C 0.008 — 0.01� C’ — 0.�41 BSC —D — — 0.0�9 E — 0.0�5 BSC —F 0.004 — 0.010 G 0.01� — 0.050 H 0.004 — 0.010α 0° — 8°


Min. Nom. Max.A — �.000 BSC —B — �.900 BSC —C 0.�0 — 0.�0 C’ — 8.��0 BSC —D — — 1.75 E — 0.��5 BSC —F 0.10 — 0.�5 G 0.41 — 1.�7 H 0.10 — 0.�5 α 0° — 8°

Rev. 1.40 �10 �ove��e� �� 01� Rev. 1.40 �11 �ove��e� �� 01�



Copy�ight© �01� �y HOLTEK SEMICO�DUCTOR I�C.The info��ation appea�ing in this Data Sheet is �elieved to �e accu�ate at the ti�e of pu�lication. Howeve�� Holtek assu�es no �esponsi�ility a�ising f�o� the use of the specifications described. The applications mentioned herein are used solely fo� the pu�pose of illust�ation and Holtek �akes no wa��anty o� �ep�esentation that such applications will �e suita�le without fu�the� �odification� no� �eco��ends the use of its p�oducts fo� application that �ay p�esent a �isk to hu�an life due to �alfunction o� othe�wise. Holtek's p�oducts a�e not autho�ized fo� use as c�itical co�ponents in life suppo�t devices o� syste�s. Holtek �ese�ves the �ight to alte� its products without prior notification. For the most up-to-date information, please visit ou� we� site at http://www.holtek.co�.tw.

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