Analog Integrated Circuits and Signal Processing, 11, 81-82 (1996)

Foreword: Special Section on Analog Technologies in Submicron Era

The rapid progress of integrated circuit technologies has brought us into the submicron era, where huge and highly functional systems are integrated on a single chip. Since the progress in digital technologies such as memories, microprocessors and DSP's is so eminent that the importance of analog technologies is some- times seemed to be overlooked. But analog circuits are always playing important roles in LSI's because they finally have to interface to the real world--analog world.

On the advent of the submicron era, the analog tech- nologies are being challenged to change; low voltage, low power, high frequency operation and high integrity of analog and digital function must be developed. With this situation in mined we have put together this special section on Analog Technologies in Submicron Era.

This special issue includes an .invited paper, eight contributed papers and a letter. The invited paper by Professor A. Iwata proposes a new analog-digital merged circuit architecture which utilizes the pulse modulation signals. The contributed papers covers im- portant key issues under submicron technologies such as low voltage operation, current mode operation and improvement of operation accuracy that are applied to ope-amps, filters, transconductance circuits, A/D con- verters and D/A converters in both MOS and bipolar circuits.

The guest editor would like to express his apprecia- tion to all the authors for their contribution and to all the reviewer for their critical reading. He also thanks for the following editorial committee members for their assistance in preparing this special issue.

Editorial Committee Members: Keitaro Sekine (Science University of Tokyo), Takahiro Inoue (Ku- mamoto University), Yukio Akazawa (NTT LSI Labo- ratory), Akira Matsuzawa (Matsushita Electric Indus- trial Co., Ltd.), Hiroshi Tanimoto (Toshiba Corpora- tion), Hidetoshi Onodera (Kyoto University), Shige- taka Takagi (Tokyo Institute of Technology), Futao Yamaguchi (Sony Corporation), Takahiro Miki (Mit-

Copyright, 1996, mICE, reprinted with permission from IEICE

subishi Electric Corporation), Daijiro Inami (NEC Cor- poration)

Secretary: Masao Hotta (Hitachi Ltd.), Yasuhiro Sugimoto (Chuo University)

Minoru Nagata, Guest Editor

Minoru Nagata (Member) was born in Tokyo, in 1933, received B.S. and Ph.D. degrees in electrical en- gineering from the University of Tokyo in 1956 and 1966, respectively. In 1956 he joined Central Research Laboratory, Hitachi Ltd., where he was engaged in the research of analog computers, dc amplifiers, and MOS- FET. He was one of the first Japanese who suggested MOS-FET structure in 1962. From 1964 to 1965 he was a Research Associate at Stanford Electronics Lab- oratory, Stanford University. In 1965 he returned to Hitachi CRL where he worked on operational ampli- tiers. From 1968 to 1972, he supervised a group work- ing on MOS LSIs and CAD of integrated circuits. He developed p-channel MOS LSI for desk-top calcula- tors and high speed n-channel MOS integrated circuits with depletion load device. In 1972 he was appointed a department head of the integrated circuit laboratory at Hitachi. Some of the research items he initiated include n-channel dynamic memory, power MOS-FETs, ana- log compatible IIL-technology and a two-dimensional device simulation. They are now recognized as the im- portant contributions from Hitachi. Since 1985, he has been a Director & Senior Chief Engineer, Corporate Technology, of Hitachi. Dr. Nagata was the chairman of the 1983/1984 ISSCC Far East Program Committee. He is one of the co-founders of VLSI Circuit Sympo-

82 Minoru Nagata

sium and served as the program chairman in 1987, the conference chairman in 1989. He received the National Medal of Honor from the Emperor of Japan in 1993,

received the IEEE Frederik Philips Award in 1994. He has been a member of The Engineering Academy of Japan since 1991.