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FPGA Fabrics

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Page 1: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

FPGA Fabrics

Page 2: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Reference

• Wayne Wolf, ‘FPGA-Based System Design’ Pearson

Education, 2004

Page 3: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

CPLD / FPGA

Page 4: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

CPLD

Interconnection of several PLD blocks with

Programmable interconnect on a single chip

Logic blocks executes sum-of-product expressions

and stores the results in micro-cell registers

Programmable interconnects route signals to and from

logic blocks

Page 5: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

CPLD

Logic

Block

Logic

Block

Logic

Block

Logic

Block

I/OI/O

Pro

gra

mm

able

Inte

rconnect

Page 6: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Major CPLD Resources

Number of macro-cells per logic block

Number of inputs from programmable interconnect to

logic block

Number of product terms in logic block

Page 7: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

FPGA

Programmable Logic Blocks

Implement combinational &

sequential logic

Programmable Interconnect

Wires to connect inputs and

outputs to logic blocks

Programmable I/O blocks

Logic blocks at the periphery for

external connections

Page 8: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Structure of FPGA

Logic Block

I/O Block

Interconnect

Page 9: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

FPGA Fabric

CLB: combinational logic block = logic element (LE).

LUT: Lookup table = SRAM used for truth table.

I/O block (IOB): I/O pin + associated logic and electronics.

LE LE LE

LE LE LE

LE LE LE

interconnect

IOB IOB IOB …

Page 10: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

FPGA Fabric

Look-up table with N-inputs can be used to implement any

combinational function of N-inputs

LUT is programmed with truth table

Page 11: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

FPGA Fabric

Page 12: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

LUT

3-input LUT

Based on Multiplexers

LUT entries stored in configuration memory cells

Page 13: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

FPGA Fabric (contd)

LE LE LE

LE LE LE

LE LE LE

Page 14: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Organized into channels.

Many wires per channel.

Connections between wires made at programmable

interconnection points.

Must choose:

Channels from source to destination.

Wires within the channels.

D Q

Programmable interconnect

Page 15: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Choosing a Path

LE

LE

Page 16: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Routing Problems

Global routing:

Which combination of channels?

Local routing:

Which wire in each channel?

Routing metrics:

Net length.

Delay.

Page 17: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Segmented wiring Vs Offset wiring

Segments

Offset

Length 1

Length 2

Page 18: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

SRAM-based FPGA fabrics

Xilinx

Altera

Page 19: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

SRAM-based FPGAs

Program logic functions, interconnect using SRAM.

Advantages:

Re-programmable;

dynamically reconfigurable;

Fabricated with standard VLSI processes.

Disadvantages:

SRAM burns power.

Possible to steal, disrupt configuration bits.

Page 20: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Logic elements

Logic element includes combinational function +

register(s).

Use SRAM as lookup table LUT for combinational

function.

Page 21: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

LUT-based logic element

Lookup

table

configuration

bits

out

inputs

Can multiplex at output or address at input

n

12n

Page 22: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Example

1, 1, 1, 1, 1, 1, 1, 0

111

0, 1, 1, 0, 1, 0, 0, 1

111

0 1

Page 23: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Evaluation of SRAM-based LUT

N-input LUT can handle function of 2n inputs.

All logic functions take the same amount of space.

All functions have the same delay.

SRAM is larger than static gate equivalent of function.

Burns power at idle.

Want to selectively add register to LE:

Page 24: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Registers in logic elements

Register may be selected into the circuit:

LUTD Q

Configuration bit

LE out

Page 25: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Other LE features

Multiple logic functions in an LE are possible.

Specialized Addition logic:

carry chain.

Partitioned lookup tables.

Page 26: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Xilinx Spartan-II CLB

Each CLB has two identical slices.

Slice has two logic cells:

LUT.

Carry/control logic.

Registers.

Page 27: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Page 28: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II CLB details

Each lookup table can be used as a 16-bit

synchronous RAM or 16-bit shift register.

Arithmetic logic includes an XOR gate.

Each slice includes a mux to combine the results of

the two function generators in the slice.

Register can be configured as DFF or latch.

Page 29: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II CLB operation

Arithmetic:

Carry block includes XOR gate.

Use LUT for carry, XOR for sum.

Each slice uses F5 mux to combine results of

multiplexers.

F6 mux combines outputs of F5 muxes.

Registers can be FF/latch; clock and clock enable.

Includes three-state output for on-chip bus.

Page 30: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Altera APEX II logic element

Each logic array block (LAB) has 10 logic elements.

Each LE contains LUT, FF.

Logic elements share some logic – carry and control

signal generation

Page 31: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Page 32: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Apex II LE modes

Modes of operation:

Normal.

Arithmetic.

Counter.

Page 33: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

APEX-II LE normal mode

Page 34: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

APEX-II LE arithmetic mode

Page 35: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

APEX-II LE counter mode

Page 36: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

APEX-II LE control logic

Page 37: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Programmable interconnect

Uses SRAM to hold information used to program

interconnect

MOS switch controlled by configuration bit:

CMOS transistor – pass transistor

CMOS has good off state

D Q

Page 38: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Programmable vs. fixed interconnect

Switch adds delay.

Transistor off-state is worse in advanced technologies.

FPGA interconnect has extra length = added

capacitance.

Page 39: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Interconnect strategies

Some wires will not be utilized.

Congestion will not be same throughout chip.

Types of wires:

Short wires: local LE connections.

Global wires: long-distance, buffered communication.

Special wires: clocks, etc.

Page 40: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Paths in interconnect

Connection may be long, complex:

LE LE LE LE LE

LE LE LE LE LE

LE LE LE LE LE

Wiring channel

Wir

ing c

han

nel

Page 41: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Interconnect architecture

Connections from wiring channels to LEs.

Connections between wires in the wiring channels.

LE LE

Wiring channel

Page 42: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Interconnect richness

Within a channel:

How many wires.

Length of segments.

Connections from LE to channel.

Between channels:

Number of connections between channels.

Channel structure.

Page 43: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Segmented wiring

Length 1

Length 2

Page 44: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Offset segments

Page 45: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Switchbox

channel channel

chan

nel

chan

nel

Page 46: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II interconnect

Types of interconnect:

local;

general-purpose;

dedicated;

I/O pin

Global

Clock

Page 47: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II general-purpose network

Provides majority of routing resources:

General routing matrix (GRM) connects

horizontal/vertical channels and CLBs.

Interconnect between adjacent GRMs.

Hex lines connect GRM to GRMs six blocks away.

Hex lines provide longer interconnect.

12 longlines span the chip.

Page 48: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II routing

Relationship between

GRM, hex lines, and

local interconnect:

Page 49: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II three-state bus

Horizontal on-chip busses:

Page 50: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Spartan-II clock distribution

Page 51: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Altera APEX II interconnect

columnrow

Page 52: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Permanently programmed FPGAs

Antifuse

Page 53: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Antifuses

Permanently programmed.

Make a connection with electrical signal.

Resistance of about 100 W which is more than

standard via

Page 54: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Antifuse structure

substrate

Metal 1

Metal 2

antifuse

via

Page 55: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Flash-programmed FPGA

Flash is high quality programmable read only memory

Uses a floating gate structure where low leakage

capacitor holds a voltage that controls a transistor gate

Page 56: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Flash-programmed switch

Page 57: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Logic blocks

Program by making connections.

Based on multiplexing.

d0

d1

a

outa out

0 d0

1 d1

Truth table

Page 58: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Larger logic block

0 0 0 01 1 0 0

Page 59: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel 54SX logic element

Page 60: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel 54SX adder logic

Uses two C-cells in SuperCluster.

Adds bits A0 and A1.

Carry in FCI, carry out FCO.

Active when CFN is high.

Page 61: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel 54SX R cell

Page 62: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel 54SX LE

C/R cells organized into clusters.

Type 1 cluster: CRC.

Type 2 cluster: CRR.

Clusters grouped into superclusters.

Type 1: two type 1 clusters.

Type 2: one type 1, one type 2.

Page 63: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel ProASIC 500K logic gate

Uses switches to connect inputs, feedback, etc.

Page 64: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Actel 54SX interconnect

FastConnect provides horizontal connections between

logic modules.

Within a supercluster.

To supercluster below.

DirectConnect is within a supercluster:

connects C-cell to R-cell neighbor.

Generic global wiring in segmented channels.

Page 65: FPGA - eeeforumeeeforum.weebly.com/uploads/1/0/2/5/10254481/fpga2.pdf · FPGA Programmable ... Length 2. N Krishna Prakash, , Amrita School of Engineering SRAM-based FPGA fabrics

N Krishna Prakash, , Amrita School of Engineering

Antifuse programming

Need to be able to apply programming voltage to every antifuse.

Path from VDD to GND.

Programming can be performed slowly.

Don’t need a lot of parallelism.

Use the wiring network to gain access to the antifuses.

Access transistors control path to antifuse.

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N Krishna Prakash, , Amrita School of Engineering

Antifuse programming access transistors

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N Krishna Prakash, , Amrita School of Engineering

I/O pins

Need programmable pins:

Input or output.

Three-state.

Other features:

Registers.

Slew rate.

Voltage levels.

Double-data rate (DDR) support.

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N Krishna Prakash, , Amrita School of Engineering

Actel APEX II I/O

Supports SDRAM and double-data rate (DDR)

memory.

Six registers and latch.

Bidirectional buffers.

Two inputs and two outputs.

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APEX II I/O

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N Krishna Prakash, , Amrita School of Engineering

Circuit design for FPGAs:

Logic elements.

Interconnect.

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N Krishna Prakash, , Amrita School of Engineering

Multiplexers as logic elements

1

1

0

A

A

1

B

0

(AB)’

1

0

0

A

A

1

B

0

A^B

Q

0

D

CLR

CLR

0

0

CLK

latch

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N Krishna Prakash, , Amrita School of Engineering

Using antifuses

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N Krishna Prakash, , Amrita School of Engineering

Static CMOS gate vs. LUT

Number of transistors:

NAND/NOR gate has 2n transistors.

4-input LUT has 128 transistors in SRAM, 96 in multiplexer.

Delay:

4-input NAND gate has 9t delay.

SRAM decoding has 21t delay.

Power:

Static gate’s power depends on activity.

SRAM always burns power.

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Lookup table circuitry

Demultiplexer or multiplexer?

LUTadrs

LUT

adrs

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Traditional RAM/ROM

Cell drives long bit line:

Bit line

adrs

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Lookup memory

Multiplexer presents smaller load to memory cells.

Allows smaller memory cells.

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Multiplexer styles

static gatespass transistors

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N Krishna Prakash, , Amrita School of Engineering

Multiplexer design

Pass transistor multiplexer uses fewer transistors than

fully complementary gates.

Pass transistor is somewhat faster than

complementary switch:

Equal-strength p-type is 2.5X n-type width.

Total resistance is 0.5X, total capacitance is 3.5X.

RC delay is 0.5 x 3.5 = 1.75 times n-type switch.

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N Krishna Prakash, , Amrita School of Engineering

Static gate four-input mux

Delay through n-input NAND is (n+2)/3.

Lg b + 1 inputs at first level, so delay is (lg b + 3)/3.

Delay at second level is (b+2)/3.

Delay grows as b lg b.

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Pass-transistor-based four-input mux

Must include decode logic in

total delay.

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Tree-based four-input mux

Delay proportional to square

of path length.

Delay grows as lg b2.

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N Krishna Prakash, , Amrita School of Engineering

LE output drivers

Must drive load:

Wire;

Destination LE.

Different types of wiring present different loads.

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N Krishna Prakash, , Amrita School of Engineering

Avoiding programming hazards

Want to disable connections to routing channel before

programming.

From LE

Routing channel

config

progb

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N Krishna Prakash, , Amrita School of Engineering

Interconnect circuits

Why so many types of

interconnect?

Provide a choice of delay

alternatives.

Sources of delay:

Wires.

Programming points.

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N Krishna Prakash, , Amrita School of Engineering

Styles of programmable interconnection

point

pass transistor Three-state

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N Krishna Prakash, , Amrita School of Engineering

Pass transistor programmable interconnect

point

Small area.

Resistive switch.

Delay grows as the square of

the number of switches.

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N Krishna Prakash, , Amrita School of Engineering

Clock drivers

Clock driver tree:

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N Krishna Prakash, , Amrita School of Engineering

Clock nets

Must drive all LEs.

Design parameters:

number of fanouts;

load per fanout;

wiring tree capacitance.

Determine optimal buffer sizes.