FSEZ1317A - Regulation PWM With Power MOSFET

8/13/2019 FSEZ1317A - Regulation PWM With Power MOSFET

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September 2012

2012 Fairchild Semiconductor Corporation www.fairchildsemi.comFSEZ1317A Rev. 1.0.4

FSEZ1317A

Primary-Side-RegulationPWMwithPOWERMOSFETIntegrated

FSEZ1317APrimary-Side-Regulation PWM with POWER MOSFETIntegrated

Features

Low Standby Power Under 30mW

High-Voltage Startup

Fewest External Component Counts

Constant-Voltage (CV) and Constant-Current (CC)Control without Secondary-Feedback Circuitry

Green-Mode: Linearly Decreasing PWM Frequency Fixed PWM Frequency at 50kHz with Frequency

Hopping to Solve EMI Problem

Cable Compensation in CV Mode

Peak-Current-Mode Control in CV Mode

Cycle-by-Cycle Current Limiting

VDDOver-Voltage Protection with Auto Restart

VDDUnder-Voltage Lockout (UVLO)

Gate Output Maximum Voltage Clamped at 15V

Fixed Over-Temperature Protection withAuto Restart

Available in the 7-Lead SOP Package

Applications

Battery chargers for cellular phones, cordlessphones,PDA, digital cameras, power tools, etc.

Replaces linear transformers and RCC SMPS

Related Resources

Evaluation Board: FEBFSEZ1317A_CH310v3

Fairchild Power Supply WebDesigner FlybackDesign & Simulation - In Minutes at No Expense

Description

This third-generation Primary-Side-Regulation (PSR)and highly integrated PWM controller provides severalfeatures to enhance the performance of low-powerflyback converters. The proprietary topology,TRUECURRENT

, of FSEZ1317A enables precise CC

regulation and simplified circuit design for battery-charger applications. A low-cost, smaller, and lightercharger results, as compared to a conventional designor a linear transformer.

To minimize standby power consumption, theproprietary green mode provides off-time modulation tolinearly decrease PWM frequency under light-loadconditions. Green mode assists the power supply inmeeting power conservation requirements.

By using the FSEZ1317A, a charger can beimplemented with few external components andminimized cost. A typical output CV/CC characteristicenvelope is shown in Figure 1.

Figure 1. Typical Output V-I Characteristic

Ordering Information

Part NumberOperating

Temperature RangePackage

PackingMethod

FSEZ1317AMY_F116 -40C to +105C 7-Lead, Small Outline Package (SOP-7) Tape & Reel
http://www.fairchildsemi.com/products/evaluationboards/http://www.fairchildsemi.com/products/evaluationboards/http://www.fairchildsemi.com/design_tools/power-supply-webdesigner/http://www.fairchildsemi.com/design_tools/power-supply-webdesigner/http://www.fairchildsemi.com/design_tools/power-supply-webdesigner/http://www.fairchildsemi.com/design_tools/power-supply-webdesigner/http://www.fairchildsemi.com/products/evaluationboards/


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2012 Fairchild Semiconductor Corporation www.fairchildsemi.comFSEZ1317A Rev. 1.0.4 2

FSEZ1317A

Primary-Side-RegulationPWMwithPOWERMOSFET

Integrated

Application Diagram

D1

D3

D4

D2

C1

Rsn2 Csn

Dsn

DF

CO1

AC

Input

RF

DCOutput

L1

C2

Rsn1

5

8

1

4

VS

DRAIN

CS

COMR

VDD

HV

GND

2

7

3

T1

DFaCVDD R1

R2

CVS

RSENSE

CCR

Csn2Rsn

CO2 Rd

Figure 2. Typical Application

Internal Block Diagram

OSC

VRESET

Pattern

Generator

VRESETMax.

Duty

SoftDriver

PWM

Figure 3. Functional Block Diagram


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FSEZ1317A


Integrated

Marking Information

Figure 4. Top Mark

Pin Configuration

Figure 5. Pin Configuration

Pin Definitions

Pin # Name Description

1 CSCurrent Sense. This pin connects a current-sense resistor, to detect the MOSFET current forpeak-current-mode control in CV mode, and provides the output-current regulation in CC mode.

2 VDDPower Supply. IC operating current and MOSFET driving current are supplied using this pin.This pin is connected to an external VDDcapacitor of typically 10F. The threshold voltages forstartup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA.

3 GND Ground

4 COMRCable Compensation. This pin connects a 1F capacitor between the COMR and GND pinsfor compensation voltage drop due to output cable loss in CV mode.

5 VSVoltage Sense. This pin detects the output voltage information and discharge time based onvoltage of auxiliary winding.

7 HV High Voltage. This pin connects to bulk capacitor for high-voltage startup.

8 DRAIN Driver Output.Power MOSFET drain. This pin is the high-voltage power MOSFET drain.

F: Fairchild LogoZ: Plant CodeX: 1-Digit Year CodeY: 1-Digit Week Code

TT: 2-Digit Die Run CodeT: Package Type (M=SOP)P: Y=Green Package

M: Manufacture Flow Code


4/16


FSEZ1317A


Integrated

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended.In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Units

VHV HV Pin Input Voltage 500 V

VVDD DC Supply Voltage(1,2)

30 V

VVS VS Pin Input Voltage -0.3 7.0 V

VCS CS Pin Input Voltage -0.3 7.0 V

VCOMV Voltage Error Amplifier Output Voltage -0.3 7.0 V

VCOMI Current Error Amplifier Output Voltage -0.3 7.0 V

VDS Drain-Source Voltage 700 V

ID Continuous Drain CurrentTA=25C 1 A

TA=100C 0.6 A

IDM Pulsed Drain Current 4 A

EAS Single Pulse Avalanche Energy 50 mJ

IAR Avalanche Current 1 A

PD Power Dissipation (TA50C) 660 mW

JA Thermal Resistance (Junction-to-Air) 150 C/W

JT Thermal Resistance (Junction-to-Case) 39 C/W

TJ Operating Junction Temperature -40 +150 C

TSTG Storage Temperature Range -55 +150 C

TL Lead Temperature (Wave soldering or IR, 10 seconds) +260 C

ESDElectrostaticDischarge Capability

(Except HV Pin)

Human Body Model, JEDEC-JESD22_A114 5000V

Charged Device Model, JEDEC-JESD22_C101 2000Notes:1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.2. All voltage values, except differential voltages, are given with respect to the GND pin.3. ESD ratings including HV pin: HBM=500V, CDM=1250V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommendedoperating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Units

TA Operating Ambient Temperature -40 +105 C


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FSEZ1317A


Integrated

Electrical Characteristics

Unless otherwise specified, VDD=15V and TA=25.

Symbol Parameter Conditions Min. Typ. Max. Units

VDDSection

VOP Continuously Operating Voltage 23 V

VDD-ON Turn-On Threshold Voltage 15 16 17 V

VDD-OFF Turn-Off Threshold Voltage 4.5 5.0 5.5 V

IDD-OP Operating Current 2.5 5.0 mA

IDD-GREEN Green-Mode Operating Supply Current 0.95 1.45 mA

VDD-OVP VDDOver-Voltage-Protection Level (OVP) 24 V

VDD-OVP-HYS Hysteresis Voltage for VDDOVP 1.5 2.0 2.5 V

tD-VDDOVP VDDOver-Voltage-Protection Debounce Time 50 200 300 s

HV Startup Current Source Section

VHV-MIN Minimum Startup Voltage on HV Pin 50 V

IHV Supply Current Drawn from HV Pin VDC=100V 1.5 3.0 mA

IHV-LC Leakage Current after StartupHV=500V,VDD= VDD-OFF+1V

0.96 3.00 A

Oscillator Section

fOSC FrequencyCenter Frequency 47 50 53

kHzFrequency Hopping Range 3.5

fOSC-N-MIN Minimum Frequency at No-Load 370 Hz

fOSC-CM-MIN Minimum Frequency at CCM 13 kHz

fDV Frequency Variation vs. VDDDeviation VDD=10~25V, 1 2 %

fDT Frequency Variation vs. Temperature DeviationTA=-40C to105C

15 %

Voltage-Sense Section

Itc IC Bias Current 10 A

VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV RVS=20k 1.4 V

Current-Sense Section

tPD Propagation Delay to GATE Output 90 200 ns

tMIN-N Minimum On Time at No-Load 590 795 1000 ns

VTH Threshold Voltage for Current Limit 0.8 V

Voltage-Error-Amplifier Section

VVR Reference Voltage 2.475 2.500 2.525 V

VN Green-Mode Starting Voltage on EA_V fOSC-5kHz 2.2 V

VG Green-Mode Ending Voltage on EA_V fOSC=1kHz 0.4 V

Current-Error-Amplifier Section

VIR Reference Voltage 2.475 2.500 2.525 V

Cable Compensation Section

VCOMR COMR Pin for Cable Compensation 0.85 V

Continued on the following page


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FSEZ1317A


Integrated

Electrical Characteristics (Continued)

Unless otherwise specified, VDD=15V and TA=25.

Symbol Parameter Conditions Min. Typ. Max. Units

Internal MOSFET Section(4)

DCYMAX Maximum Duty Cycle 52 65 78 %

BVDSS Drain-Source Breakdown VoltageID=250A,

VGS=0V700 V

BVDSS/TJ Breakdown Voltage Temperature Coefficient

ID=250A,

Referenced to

TA=25C

0.53 V/C

RDS(ON) Static Drain-Source On-Resistance ID=0.5A,VGS=10V

13 16

ISMaximum Continuous Drain-Source Diode Forward

Current1 A

IDSS Drain-Source Leakage Current

VDS=700V,

TA=25C10 A

VDS=560V,

TA=100C100 A

tD-ON Turn-On Delay TimeVDS=350V,

ID=1A,

RG=25(5)

10 30 ns

tD-OFF Turn-Off Delay Time 20 50 ns

CISS Input Capacitance

VGS=0V,

VDS=25V,

fS=1MHz

175 200 pF

COSS Output Capacitance 23 25 pF

Over-Temperature-Protection Section

TOTP Threshold Temperature for OTP(6)

+140 CNotes:4. These parameters, although guaranteed, are not 100% tested in production.

5. Pulse test: pulsewidth300s, duty cycle2%.

6. When the Over-temperature protection is activated, the power system enter auto-restart mode and output isdisabled.


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FSEZ1317A


Integrated

Typical Performance Characteristics

15

15.4

15.8

16.2

16.6

17

-40 -30 -15 0 25 50 75 85 100 125

VDD_O

N

(V)

Temperature (C)

4.5

4.7

4.9

5.1

5.3

5.5

-40 -30 -15 0 25 50 75 85 100 125

VDD_O

FF

(V)

Temperature (C)

Figure 6. Turn-On Threshold Voltage (VDD-ON)vs. Temperature

Figure 7. Turn-Off Threshold Voltage (VDD-OFF)vs. Temperature

1

1.8

2.6

3.4

4.2

5

-40 -30 -15 0 25 50 75 85 100 125

IDD_

OP

(mA)

Temperature (C)

42

45

48

51

54

-40 -30 -15 0 25 50 75 85 100 125

Fosc

(KHz)

Temperature (C)

Figure 8. Operating Current (IDD-OP) vs. Temperature Figure 9. Center Frequency (fOSC) vs. Temperature

2.465

2.475

2.485

2.495

2.505

2.515

2.525

-40 -30 -15 0 25 50 75 85 100 125

VVR

(V)

Temperature (C)

0.8

0.84

0.88

0.92

0.96

1

-40 -30 -15 0 25 50 75 85 100 125

IDD_

Green

(mA)

Temperature (C)

Figure 10. Reference Voltage (VVR) vs. Temperature Figure 11. Green Mode Operating Supply Current(IDD-GREEN) vs. Temperature


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FSEZ1317A


Integrated

Typical Performance Characteristics(Continued)

330

350

370

390

410

430

450

-40 -30 -15 0 25 50 75 85 100 125

Fosc_

Green

(Hz)

Temperature (C)

10

11

12

13

14

15

16

-40 -30 -15 0 25 50 75 85 100 125

Fosc_

CM_

MIN

(KHz)

Temperature (C)

Figure 12. Minimum Frequency at No Load(fOSC-N-MIN) vs. Temperature

Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN)vs. Temperature

0

0.5

1

1.5

2

2.5

3

-40 -30 -15 0 25 50 75 85 100 125

IHV

(V)

Temperature (C)

400

500

600

700

800

900

1000

-40 -30 -15 0 25 50 75 85 100 125

TMIN_

N

(V)

Temperature (C)

Figure 14. Supply Current Drawn from HV Pin (IHV)vs. Temperature

Figure 15. Minimum On Time at No Load (tMIN-N)vs. Temperature

2.3

2.335

2.37

2.405

2.44

2.475

-40 -30 -15 0 25 50 75 85 100 125

Vn

(V)

Temperature (C)

0.3

0.317

0.334

0.351

0.368

0.385

-40 -30 -15 0 25 50 75 85 100 125

Vg

(V)

Temperature (C)

Figure 16. Green Mode Starting Voltage on EA_V(VN) vs. Temperature

Figure 17. Green Mode Ending Voltage on EA_V (VG)vs. Temperature


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FSEZ1317A


Integrated

Typical Performance Characteristics(Continued)

8.6

8.8

9

9.2

9.4

9.6

9.8

-40 -30 -15 0 25 50 75 85 100 125

ITC

(uA)

Temperature (C)

1

1.1

1.2

1.3

1.4

1.5

1.6

-40 -30 -15 0 25 50 75 85 100 125

VBIAS_

COM

V

(V)

Temperature (C)

Figure 18. IC Bias Current (Itc) vs. Temperature Figure 19. Adaptive Bias Voltage Dominated by VCOMV(VBIAS-COMV) vs. Temperature

0.78

0.79

0.8

0.81

0.82

0.83

0.84

-40 -30 -15 0 25 50 75 85 100 125

VTH_

vs0.6

V

(ns)

Temperature (C)

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-40 -30 -15 0 25 50 75 85 100 125

IHV_

LC

(mA)

Temperature (C)

Figure 20. Threshold Voltage for Current Limit (VTH)vs. Temperature

Figure 21. Leakage Current after Startup (IHV-LC)vs. Temperature

0.79

0.81

0.83

0.85

0.87

0.89

0.91

-40 -30 -15 0 25 50 75 85 100 125

VCOMR

(V)

Temperature (C)

64

66

68

70

72

74

76

-40 -30 -15 0 25 50 75 85 100 125

DCYMax

(%)

Temperature (C)

Figure 22. Variation Test Voltage on COMR Pin forCable Compensation (VCOMR) vs. Temperature

Figure 23. Maximum Duty Cycle (DCYMAX)vs. Temperature


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FSEZ1317A


Integrated

Functional Description

Figure 24 shows the basic circuit diagram of primary-side regulated flyback converter, with typical waveformsshown in Figure 25. Generally, discontinuousconduction mode (DCM) operation is preferred forprimary-side regulation because it allows better outputregulation. The operation principles of DCM flyback

converter are as follows:

During the MOSFET on time (tON), input voltage (VDL) isapplied across the primary-side inductor (Lm). ThenMOSFET current (Ids) increases linearly from zero to thepeak value (Ipk). During this time, the energy is drawnfrom the input and stored in the inductor.

When the MOSFET is turned off, the energy stored inthe inductor forces the rectifier diode (D) to be turnedon. While the diode is conducting, the output voltage(Vo), together with diode forward-voltage drop (VF), is

applied across the secondary-side inductor (LmNs2/

Np2) and the diode current (ID) decreases linearly from

the peak value (IpkNp/Ns) to zero. At the end of inductor

current discharge time (tDIS), all the energy stored in theinductor has been delivered to the output.

When the diode current reaches zero, the transformerauxiliary winding voltage (Vw) begins to oscillate by theresonance between the primary-side inductor (Lm) andthe effective capacitor loaded across the MOSFET.

During the inductor current discharge time, the sum ofoutput voltage and diode forward-voltage drop is

reflected to the auxiliary winding side as (VO+VF) Na/Ns. Since the diode forward-voltage drop decreasesas current decreases, the auxiliary winding voltagereflects the output voltage best at the end of diodeconduction time where the diode current diminishes tozero. Thus, by sampling the winding voltage at the end

of the diode conduction time, the output voltageinformation can be obtained. The internal error amplifierfor output voltage regulation (EA_V) compares thesampled voltage with internal precise reference togenerate error voltage (VCOMV), which determines theduty cycle of the MOSFET in CV mode.

Meanwhile, the output current can be estimated usingthe peak drain current and inductor current dischargetime because output current is same as the average ofthe diode current in steady state.

The output current estimator picks up the peak value ofthe drain current with a peak detection circuit andcalculates the output current using the inductordischarge time (tDIS) and switching period (ts). Thisoutput information is compared with internal precisereference to generate error voltage (VCOMI), whichdetermines the duty cycle of the MOSFET in CC mode.With Fairchilds innovative technique TRUECURRENT

,

constant current (CC) output can be precisely controlled.

Among the two error voltages, VCOMV and VCOMI, thesmaller one determines the duty cycle. Therefore, duringconstant voltage regulation mode, VCOMVdetermines theduty cycle while VCOMI is saturated to HIGH. Duringconstant current regulation mode, VCOMI determines theduty cycle while VCOMVis saturated to HIGH.

+

VDL

-

Lm

+

VO

-

Np

: Ns

Ids

ID

D

P r i m a r y -S i d e R e g u l a t i o n

C o n t r o l l e r

+

Vw

-

VDD

VS

CS

+ VF-

NA

L

O

AD

IO

IOEstimator

VOEstimator

tDIS

DetectorPWM

Control

RCS

VA C

Ref

RefEA_V

EA_I

VCOMV

VCOMI

RS1

RS2

Figure 24. Simplified PSR Flyback Converter Circuit

Ppk

S

NI

pkI

.D avg oI I=

AF

S

V

AO

S

VN

Figure 25. Key Waveforms of DCM FlybackConverter


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FSEZ1317A


Integrated

Cable Voltage Drop Compensation

In cellular phone charger applications, the battery islocated at the end of cable, which typically causes severalpercentage of voltage drop on the battery voltage.FSEZ1317A has a built-in cable voltage dropcompensation that provides a constant output voltage atthe end of the cable over the entire load range in CV

mode. As load increases, the voltage drop across thecable is compensated by increasing the reference voltageof the voltage regulation error amplifier.

Operating Current

Operating current as small as 2.5mA results in higherefficiency and reduces the VDD hold-up capacitancerequirement. Once enters deep Green Mode, theoperating current is reduced to 0.95mA, which helps thepower supply meet power conservation requirements

Green-Mode Operation

The FSEZ1317A uses voltage regulation error amplifier

output (VCOMV) as an indicator of the output load andmodulates the PWM frequency as shown in Figure 26.The switching frequency decreases as the loaddecreases. In heavy load conditions, the switchingfrequency is fixed at 50kHz. Once VCOMV decreasesbelow 2.5V, the PWM frequency linearly decreases from50kHz. When FSEZ1317A enters deep green mode, thePWM frequency is reduced to a minimum frequency of370Hz, thus gaining power saving to meet internationalpower conservation requirements.

Figure 26. Switching Frequency in Green Mode

Frequency Hopping

EMI reduction is accomplished by frequency hopping,which spreads the energy over a wider frequency rangethan the bandwidth measured by the EMI testequipment. FSEZ1317A has an internal frequencyhopping circuit that changes the switching frequencybetween 46kHz and 54kHz over the period shown inFigure 27.

Figure 27. Frequency Hopping

High-Voltage Startup

Figure 28 shows the HV-startup circuit for FSEZ1317Aapplications. The HV pin is connected to the line input orbulk capacitor through a resistor, RSTART (100krecommended). During startup status, the internalstartup circuit is enabled. Meanwhile, line input suppliesthe current, ISTARTUP, to charge the hold-up capacitor,CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blockingISTARTUPfrom flowing into the HV pin. Once the IC turns

on, CDD is the only energy source to supply the ICconsumption current before the PWM starts to switch.Thus, CDD must be large enough to prevent VDD fromdropping down to VDD-OFF before the power can bedelivered from the auxiliary winding.

Figure 28. HV Startup Circuit


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FSEZ1317A


Integrated

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at16V and 5V, respectively. During startup, the hold-upcapacitor must be charged to 16V through the startupresistor to enable the FSEZ1317A. The hold-upcapacitor continues to supply VDD until power can be

delivered from the auxiliary winding of the maintransformer. VDDis not allowed to drop below 5V duringthis startup process. This UVLO hysteresis windowensures that hold-up capacitor properly supplies VDDduring startup.

Protections

The FSEZ1317A has several self-protection functions,such as Over-Voltage Protection (OVP), Over-Temperature Protection (OTP), and pulse-by-pulsecurrent limit. All the protections are implemented asauto-restart mode. Once the abnormal condition occurs,the switching is terminated and the MOSFET remainsoff, causing VDD to drop. When VDD drops to the VDDturn-off voltage of 5V, internal startup circuit is enabledagain and the supply current drawn from the HV pincharges the hold-up capacitor. When VDD reaches theturn-on voltage of 16V, normal operation resumes. Inthis manner, the auto-restart alternately enables anddisables the switching of the MOSFET until theabnormal condition is eliminated(see Figure 29).

Figure 29. Auto-Restart Operation

VDDOver-Voltage Protection (OVP)VDDover-voltage protection prevents damage from over-voltage conditions. If the VDD voltage exceeds 24V atopen-loop feedback condition, OVP is triggered and thePWM switching is disabled. The OVP has a debouncetime (typically 200s) to prevent false triggering due toswitching noises.

Over-Temperature Protection (OTP)The built-in temperature-sensing circuit shuts downPWM output if the junction temperature exceeds 140C.

Pulse-by-pulse Current LimitWhen the sensing voltage across the current-senseresistor exceeds the internal threshold of 0.8V, the

MOSFET is turned off for the remainder of switchingcycle. In normal operation, the pulse-by-pulse currentlimit is not triggered since the peak current is limited bythe control loop.

Leading-Edge Blanking (LEB)Each time the power MOSFET switches on, a turn-onspike occurs at the sense resistor. To avoid prematuretermination of the switching pulse, a leading-edgeblanking time is built in. During this blanking period,the current-limit comparator is disabled and cannotswitch off the gate driver. As a result conventional RCfiltering can be omitted.

Gate Output

The FSEZ1317A output stage is a fast totem-pole gatedriver. Cross conduction has been avoided to minimizeheat dissipation, increase efficiency, and enhancereliability. The output driver is clamped by an internal15V Zener diode to protect the power MOSFETtransistors against undesired over-voltage gate signals.

Built-In Slope Compensation

The sensed voltage across the current-sense resistor isused for current mode control and pulse-by-pulsecurrent limiting. Built-in slope compensation improvesstability and prevents sub-harmonic oscillations due topeak-current mode control. The FSEZ1317A has asynchronized, positive-slope ramp built-in at each

switching cycle.

Noise Immunity

Noise from the current sense or the control signal cancause significant pulsewidth jitter, particularly incontinuous-conduction mode. While slopecompensation helps alleviate these problems, furtherprecautions should still be taken. Good placement andlayout practices should be followed. Avoiding long PCBtraces and component leads, locating compensationand filter components near the FSEZ1317A, andincreasing the power MOS gate resistance are advised.


13/16


FSEZ1317A

Primary-Side-RegulationP

WMwithPOWERMOSFET

Integrated

Typical Application Circuit (Primary-Side Regulated Flyback Charger)

Application Fairchild Devices Input Voltage Range Output Output DC cable

Cell Phone Charger FSEZ1317AMY_F116 90~265VAC 5V/0.7A (3.5W) AWG26, 1.8 Meter

Features

High efficiency (>65.5% at full load) meeting EPS 2.0 regulation with enough margin Low standby (Pin


14/16


FSEZ1317APrimary-Side-RegulationPWMwithPOWERMOSFET

Integrated

Typical Application Circuit (Continued)

Transformer Specification

Core: EE16 Bobbin: EE16

Figure 33. Transformer Specification

Notes:7. When W4Rs winding is reversed winding, it must wind one layer.8. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer.

No.Terminal

Wire tsInsulation Barrier Tape

S F ts Primary Seconds

W1 4 5 2UEW 0.23*2 15 2

W2 3 1 2UEW 0.17*1

41 1

39 0

37 2

W3 1 COPPER SHIELD 1.2 3

W4 7 9 TEX-E 0.55*1 9 3

CORE ROUNDING TAPE 3

Pin Specification Remark

Primary-Side Inductance 13 2.25mH 7% 100kHz, 1V

Primary-Side Effective Leakage 13 80H 5% Short One of the Secondary Windings

54

BOBBIN

3

1

1

97

Auxiliary

Winding

Primary

Winding

1st Shield

Secondary

Winding


15/16



Integrated

Physical Dimensions

FRONT VIEW

80

SEE DETAIL A

SEATING PLANE

GAGE PLANE

x 45

DETAIL ASCALE: 2:1

0.250.19

0.36

0.500.25

R0.10

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

NOTES:

A) THIS PACKAGE DOES NOT FULLY CONFORMS TO JEDEC MS-012 VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS.

D) DRAWING FILENAME : M07Brev3

LAND PATTERN RECOMMENDATION

C

4

7

1

B5

A

0.65TYP

1.75TYP

1.27

6.205.80

3.81

4.003.80

5.004.80

(0.33)1.27

0.510.33

0.25

0.10

1.75 MAX

6

2 3

0.25 C B APIN #1

TOP VIEW

3.85 7.35

3.81

0.10 C

Figure 34. 7-Lead, Small Outline Package (SOP-7)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannerwithout notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orobtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions, specifically thewarranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:http://www.fairchildsemi.com/packaging/.


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FSEZ1317A - Regulation PWM With Power MOSFET