General Info Purpose/ Applications Interrupt Priority/ IVT Controlling Interrupts Maskable interrupts Non-maskable interrupts Example Conclusion 1 Interrupts

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• General Info

• Purpose/ Applications

• Interrupt Priority/ IVT

• Controlling Interrupts

• Maskable interrupts

• Non-maskable interrupts

• Example

• Conclusion

Interrupts

Nurudeen Olayiwola

Thomas Gutierrez

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Question??• When you are at home sitting on your

lazy boy, how do you know when someone wants to talk to you on the phone?

– Do you periodically get up and pick up the phone to see if someone is there?

– Or do you wait till the phone rings to answer it?

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Answer?• The first scenario shows a person

doing what is known as polling.

• The second case illustrates an interrupt-driven person.

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Polling

• AKA “busy waiting”; looping program

• Continues checking status register until a particular state exists

• “Are we there yet? Are we there yet? Are we there yet?”

• What happens if something occurs at other devices while the processor is busy waiting??

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Interrupt

• Device sends a special signal to CPU when data arrives.

• “Wake me up when we get there.”

• Responds to hardware interrupt signal by interrupting current processing.

• Now CPU can perform tasks before and after interrupt instead of just polling!! Good!

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General Interrupt Flow1. Completes current instruction

2. Saves current state to status registers

3. Identify source

4. Jump to and activate Interrupt Service Routing (ISR)

5. Return to original program (RTI) and restore state

Register

Interrupt drivenCPU

I/Odevice

I/Odevice

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Interrupts: Flow Chart

SOFTWARE

INTERRUPT

STACK MPU REGISTER CONTENTS

SET APPROPRIATE

BIT IN CCR

LOAD INTERRUPT VECTOR INTO

PROGRAM COUNTER

VECTOR TABLE

HARDWARE

INTERRUPT

MASK SET?

N

Y

EXECUTE INTERRUPT SERVICE ROUTINE

$FFC0

$FFFF

CONTINUE MAIN PROGRAM

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Brief Background

• Univac 1103/1103A (1953-56) – first recognized CPU with interrupts. Current instruction was stored in memory and program counter loaded with a fixed address.

• Other notables:– IBM (1954) – first to use interrupt

masking– NBS DYSEAC (1954) – first with I/O

interrupts

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Purpose/Applications• To modify or do additional instructions based on

internal requests and/or external devices.

• Provide a means for suspending current instructions for more important tasks.

• Hardware (called Interrupts or Resets)– Reset– User-defined interrupt– Timer operations– CPU operations monitor failure

• Software– Illegal instruction– SWI

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Purpose/Applications (cont.)• Coordinating I/O operations

• Notifies the CPU that an input is ready or an output can be changed

• Timing• Periodic (clock-driven) interrupts remind

the CPU of the passage of time• Multi-tasking• Updating counters• Timing during interactive programs

• Errors• Interrupts can notify of error situations

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Purpose/Applications (cont.)

• Practical uses/examples

• Change direction of a motor.

• Auto wiper speed increased or decreased.

• Pressing a pause button on a VCR

• HC11 controlled transmission system

• Etc.

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Types of interrupts

• Ignorable interrupts (or Maskable)– Most often used– Good for using when computer needs to

do something more important– When the interrupt mask is set, interrupts

are hidden and therefore are ignored.

• Non-ignorable interrupts (Non-maskable)• NMI’s take precedence and interrupt any

task

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Interrupt Vector Table

• When an interrupt occurs, control of the program moves to the interrupt handling routine– Event similar to subroutine– How do we know where the handler routine is

though??

• The address of the handler is provided by the interrupt vector table– IVT has one entry for each type of interrupt– Each entry is indexed by interrupt type, and

includes a pointer to the handler

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Interrupt Vector TableMaskable when the I-bit of CCR is set

Unmaskable

lowest priority

highest priority

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Maskable/Unmaskable

• 6 Non-Maskable– always interrupt the program

execution• 15 Maskable

– can enable or disable by mask bits– HOW?

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Stacking orderWhen an interrupt occurs:

2. HC11 pushes on stack: PC, accumulators and registers, CCR

3. HC11 sets the I-bit Masks interrupts - can’t interrupt an interrupt

4. Looks up vector of highest-priority interrupt

5. Branches to interrupt service routine Executes until RTI is encountered

6. Restores accumulators and registers, CCR from stack (note: this includes restoring the I-bit of CCR)

7. Returns to instruction after the one that was interrupted (note: other interrupts may be pending now)

1. Finish execution of the current instruction Note: Non-maskable interrupts and resets happen immediately

SP-9

SP-8

SP-7

SP-6

SP-4

SP-5

SP-3

SP-1

SP-2

SP-0

CCR

ACCB

ACCA

IXH

IXL

IYH

IYL

PCH

PCL

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Controlling Interrupts: The I-bit

• Exists as bit 4 in the Condition Code Register (CCR)– When set (I=1), interrupts will be inhibited and

placed as pending– When cleared (I=0), interrupt servicing will be

allowed when asked

• The I bit is always set while servicing an interrupt; Interrupts can’t nest

• Set during RESET to allow minimum system initialization

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Controlling Interrupts: The I-bit

• Can also be set by software to prevent execution of maskable interrupts– SEI (SEt Interrupt Mask)

• Can be cleared by software instructions– CLI (CLear Interrupt Mask)

• Automatically cleared by RTI instruction

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Maskable Interrupt: HPRIO

• Can elevate the priority of one of the maskable interrupts.

• Uses bits 0-3 of HPRIO (Highest PRIOrity Interrupt Register)

• Default is IRQ.

• Can be set at anytime during program as long as I bit is set.

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Maskable Interrupt: IRQ

• Highest priority maskable interrupt• IRQ pin provides additional external

interrupting source• Other additional MCU pins can be used as

interrupt inputs:– Example:

• XIRQ input• Main-Timer Capture Pins• Pulse Accumulator Pin

• IRQE Bit in the OPTION control used to specify IRQ pin configuration– IRQE = 0 -> Low level sensitive– IRQE = 1 -> Low-going edge sensitive (single

source only)

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Maskable Interrupt: IRQ

• Controlled by a pin on the HC11

• A low signal will initiate interrupt sequence

OPTION $10397 6 5 4 3 2 1 0

ADPU CSEL IRQE DLY CME CR1 CR0

0

1

IRQE = IRQ Select Edge Sensitive Only (Time Protected)

0 = IRQ configured for low LEVEL (default)1 = IRQ configured for falling EDGEs

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Non-maskable Interrupt: XIRQ

• Enabled by TAP instruction by clearing X-bit upon system initialization

• After being cleared, software cannot set the X-bit, thus XIRQ is non-maskable.

• Higher priority than any source maskable by the I-bit.

• Both the X and I bits are automatically set by hardware after stacking the CCR.

• RTI restores X and I bit to pre-interrupt states

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Non-maskable Interrupt: SWI

• Software instruction, thus cannot be interrupted until completed

• Uninhibited by global mask bits in the CCR

• Similar to other interrupts, sets the I-bit upon servicing

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Example - IRQ handler

IRQHANDLE ORG $3000ldaa count ; A <-- current count

inca ; increment countstaa count ; write back countldx #msg ; print out msgjsr OUTSTRGldx #count ; print out countjsr OUT1BYTrti ; all done – returnorg $2000 ; data section

msg fcc “Number of times button pressed:”fcb $04

count fcb 0 ; button counterorg $00eeJMP IRQHANDLE

org $2200 ; main programcli ; enable interrupts

loop bra loop ; endless loop

1. Write the IRQ handler routine

IRQ vector at $FFF2

3. Do-nothing program!

2. Write the initialization and main routine

>>Whenever button is pushed, update a counter and print out the current count

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The SIX untouchables: NONMASKABLE

• RESET

• CLOCK MONITOR

• COP Watchdog

• Illegal Opcode

• XIRQ

• SWI

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Advantages and Disadvantages

• Advantage

1. Efficient, better than polling

2. Multitasking

• Disadvantage

1. They can occur randomly

2. Requires additional hardware, sometimes

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Questions??

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References

http://courses.cs.tamu.edu/cpsc462/ walker/Slides/Exceptions_Interrupts_1.ppt

http://oa-003.spu.edu/bolding/ee3280/nosound/16-Exceptions.ppt

Previous semester presentations…

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General Info Purpose/ Applications Interrupt Priority/ IVT Controlling Interrupts Maskable interrupts Non-maskable interrupts Example Conclusion 1 Interrupts