Since most FPGAs are bundled in surface-mountpackages, it isn’t very practical to try and breadboardone to experiment with. There are several good

FPGA training boards available from Digilent; go towww.digilentinc.com to see what they have available inFPGA trainers.

This two-part series FPGAs will deal withthe Digilent Basys2 FPGA board which costsfrom $49 up to $79 depending on whetheryou are a student or not (see Photo 1). TheBasys2 FPGA board comes with a XilinxXC3S100E 100K gate FPGA or, for another$20 you can upgrade the board to a

XC3S250E 250K gate FPGA. This article will only deal withthe basic 100K FPGA.

You will probably want to purchase four of the 6” six-pin expansion cables for $2.50 each if you want to expandyour design out to an external bread-board, which will be

You’ve probably heard about FPGAs (field programmable gate arrays) recently if you’re involved in the electronics field. FPGAs are some of the latest ICs to befound in electronics products such as: digital flat screen televisions, digitalcameras, and multi-function printers. Anyone involved in the field of digitalelectronics should be interested in learning more about FPGAs because of theirgrowing influence in the field of electronics.

GettingStarted With

FPGAs —Part 1

by David Ward

PHOTO 1.

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PHOTO 2.

56 SERVO 09.2011

demonstrated later on (see Photo 2). The Basys2 FPGAboard comes equipped with eight slide switches, fourpushbuttons, eight LEDs, four seven-segment displays, aVGA connector, a PS2 connector, and a USB connector. It ispowered by your PC’s USB connection or from an external3.5V to 5.5V DC source.

FPGAs are volatile devices. That is, their configurationbit file — the file that tells them how to make their internalconnections to perform the functions that you desire — islost each time the FPGA is powered down. Therefore,FPGAs must have an external non-volatile memory device tohold this configuration bit file. The Basys2 FPGA board hasa 2M bit Xilinx XCF02 non-volatile platform Flash PROM(programmable read only memory) chip on-board for thispurpose. However, it is possible to download aconfiguration bit file from your PC directly into the FPGAand have it run as long as power is connected to the board.If you want your configuration bit file to operate afterpowering the board down, you will need to load that fileinto the PROM instead.

Let’s look at the internal structure of the XilinxXC3S100E FPGA. At the most fundamental level in theFPGA is the LUT (look-up table). Each LUT in the FPGA hasfour inputs and one output, and any four variable Booleanlogic operations can be implemented into one LUT. If moreinputs are needed, the LUTs are cascaded together. Thereare “G” LUTs and “F” LUTs; see Figure 1.

Two LUTs, one G LUT, and one F LUT are combinedtogether to make what is called a SLICEL, asshown in Figure 2. When two LUTs arecombined together with a 16-bit RAMregister, it is called a SLICEM; see Figure 3.There are a total of 1,920 LUTs in the FPGA:960 G LUTs and 960 F LUTs. Since SLICEMshave a 16-bit RAM register, they make up atotal of 15,360 RAM bits; 960 x 16 =15,360. This is what is referred to asdistributed RAM in the FPGA. These 16-bitSLICEM registers can also be used as shiftregisters.

Four slices, two SLICELs, and twoSLICEMs are interconnected to make a CLB(configurable logic block). There are 240CLBs in this FPGA. CLBs are placed in rowsand columns; 22 rows by 16 columns for atotal of 240 as shown in Figure 4. Notice

FIGURE 1.

FIGURE 4.

FIGURE 3.

FIGURE 2.

that 22 x 16 = 352, not 240.This is because some of theCLBs are not there to makeroom for other structureswhich will be discussed in thenext paragraph.

Also located in the FPGAare IOBs (input/output blocks).There are four IOB banks in theFPGA (see Figure 5). The IOBblock takes care of the physicalinterconnections from the internal logic to the FPGA pinsthemselves. The IOBs can be configured to over 20 I/Ostandards and drive from 2 mA up to 16 mA. For thecircuits that will be demonstrated in these articles, we willuse the LVTTL (low voltage TTL) I/O standard where 3.3V isa logic “1.” We can also set the drive at 16 mA to directlydrive LEDs. The slew rate can be configured from slow tofast to match the appropriate devices the FPGA may bedriving.

There are 72K bits of block RAM in the FPGA. Thereare also four 18-bit dedicated multipliers. There are twoDCMs (digital clock managers) as shown in Figure 6. The

block RAM, multipliers, and DCMs take up some of the CLBspace; that is why there are only 240 CLBs instead of 352.

The XC3S100E on the Basys2 board is in a 132-pinpackage which allows for a total of 83 user I/O pins,although the PCB only makes 16 of these available at thefour six-pin expansion connectors.

In order to generate the configuration bit files, Xilinxprovides their ISE Design Suite webPACK as a freedownload; go to www.xilinx.com. The ISE Design Suitehas a program called Impact which can be used to programCPLDs, FPGAs, and PROM chips, but it will notcommunicate with the Basys2 board. Digilent has a

SERVO 09.2011 57

FIGURE 8.

FIGURE 7.

FIGURE 6.

FIGURE 5.

58 SERVO 09.2011

FIGURE 13.

FIGURE 14.

FIGURE 11.

FIGURE 12.

FIGURE 9.

FIGURE 10.

program available that can be used to take the bit filecompiled in the ISE Design Suite and program it into eitherthe Basys2 FPGA or its PROM. Go to www.digilentinc.comand search for “digilent adept,” then download and installthe appropriate program for your computer. With both ofthese programs installed, you are now ready to build yourfirst FPGA digital design.

Let’s start out very simple and make a basic two-inputAND gate using two of the Basys2 slide switches as inputs,and use one of their on-board LEDs as an indicator of theAND gate’s output. This will be done in VHDL or very highspeed integrated circuit hardware description language.Open the Design Suite and start a new project as shown inFigure 7. From the Create New Project window, type in aname and location for your project (see Figure 8). From theProject Settings window, select a Spartan3E, XC3S100E,CP132, -4 as shown in Figure 9. Figure 10 shows theProject Summary window; click Finish to continue. SelectProject and New Source as shown in Figure 11.

In the next window, click on VHDL Module and type ina file name and location for your source file (see Figure12). Figure 13 allows you to enter port names and

directions; this can be done later but since this is a verysimple circuit, it’s easy to do it now. Figure 14 is anotherSummary window; select Finish to continue on. Figure 15shows you the VHDL template that the ISE program createdfor you with your inputs (A and B) and your output (Y).

Most of the template is made up of comments; thegreen text preceded by two dashes (—) can be ignored ordeleted. All we need to do is enter how we want theseinputs and outputs to operate logically. Line 42 in Figure16 shows how to enter a two-input AND gate with A and B

SERVO 09.2011 59

FIGURE 15.

FIGURE 16.

FIGURE 17.

FIGURE 18.

FIGURE 19.

as inputs and Y as the output. After line 42 is typed in, theVHDL listing could be compiled and fitted into the FPGA.However, since the Basys2 board has already connectedcertain FPGA pins to the slide switches and LEDs, we needto tell the program how we want these signals routed. Thisis done with a .UCF file or user constraint file.

To add a user constraint file, select Project New Sourceas shown in Figure 17. From the next window, click onImplementation Constraints File and type in a file name asshown in Figure 18. It’s not a bad idea to add the lettersUCF into the file name so it is easier to identify. Click Finishfrom the next Summary window as shown in Figure 19.You will now have a blank screen to enter your userconstraint information.

All that is needed is to locate or “LOC” the appropriatenet or port name with the desired FPGA pin number (seeFigure 20). These FPGA pin numbers are printed on theBasys2 PCB next to each switch and LED. The information isalso available in the Basys2 user guide which can bedownloaded from the Digilent website. Now if theImplement Top Module icon is clicked on, it looks like agreen RUN arrow. The project will compile and match yourport names with the desired FPGA pins as described in theUCF file (see Figure 21). You may see the next window inFigure 22 asking you to save these files; click on OK tocontinue.

If your original VHDL source file is okay (not missingsemi-colons, etc.) and your UCF file is good as well, theprogram will work away for a few seconds. If there are anyerrors, you will see messages in the console window at the

60 SERVO 09.2011

FIGURE 20.

FIGURE 21.

FIGURE 22.

FIGURE 23.

FIGURE 24.

bottom of the screen explaining what the problems are. Ifall goes well, you can now generate the necessary bit filethat can be downloaded into the FPGA or PROM chip. Clickon Generate Programming File and then Run, as shown inFigure 23. We now need to leave the Xilinx ISE DesignSuite to get this bit file into the FPGA.

With your Basys2 unit plugged into a USB port andturned on, open the Digilent Adept program. The programshould automatically recognize your Basys2 unit. At thispoint, it should be noted that there is a demonstrationprogram already loaded into thePROM chip of the Basys2 boardwhen you get it. It allows you tomove the slide switches, turn onLEDs, and press the pushbuttons toturn off the seven-segment displayswhile they count up. If you load yourAND gate into the PROM, you willoverwrite this demonstrationprogram and lose it. The program isavailable from the Basys2 web pageif you want to download anothercopy; look forBasys2_100userdemocclk.bit.

If you load your AND gate bitfile into the FPGA itself, it will run,but on powering down and up againthe demo program will be loadedback into the FPGA. Click on theBrowse button to the right of theFPGA drop down window (seeFigure 24). Select the bit file thatwas generated previously from theXilinx program as shown in Figure25. Now you can click on theProgram button. You’ll probably geta clock error message a couple oftimes as shown in Figure 26. SelectYes; it works fine anyway. Now youcan move slide switches SW0 andSW1 to their high positions and

LED0 should come on following the AND logic function thatwas placed into the FPGA.

We really haven’t taken any time to explain VHDLduring this article. If you want a good concise VHDL tutorialsearch for The Low-Carb VHDL Tutorial by Bryan Mealy onthe Internet.

Next TimeThe next article will demonstrate how to use the

Basys2 FPGA system to control an 8 x 8 LED matrix to scrolla message across it. This will require an externalbreadboard and the 6” expansion cables. The VHDL codelisting will also be explained in greater detail. Hopefully, thisarticle has given you enough information to at least get youstarted experimenting with FPGAs. There are also severalexample programs for the Basys2 FPGA trainer available onthe Digilent website. SV

SERVO 09.2011 61

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FIGURE 25.

FIGURE 26.

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Inspiration and goals... HandsOn Technology provides a multimedia and interactive platform for everyone interested in electronics. From beginner to diehard, from student to lecturer... Information, education, inspiration and entertainment. Analog and digital; practical and theoretical; software and hardware... HandsOn Technology provides Designs, ideas and solutions for today's engineers and electronics hobbyists.

Creativity for tomorrow's better living... HandsOn Technology believes everyone should have the tools, hardware, and resources to play with cool electronic gadgetry. HandsOn Technology's goal is to get our "hands On" current technology and information and pass it on to you! We set out to make finding the parts and information you need easier, more intuitive, and affordable so you can create your awesome projects. By getting technology in your hands, we think everyone is better offWe here at HandsOn like to think that we exist in the same group as our customers >> curious students, engineers, prototypers, and hobbyists who love to create and share. We are snowboarders and rock-climbers, painters and musicians, engineers and writers - but we all have one thing in common...we love electronics! We want to use electronics to make art projects, gadgets, and robots. We live, eat, and breathe this stuff!!If you have more questions, go ahead and poke around the website, or send an email to sales@handsontec.com. And as always, feel free to let your geek shine - around here, we encourage it...

62 SERVO 10.2011

In this second and final article, we will demonstrate amore complex and useful digital design that will usethe Basys2 FPGA trainer to control a scrolling message

on an 8 x 8 LED matrix display; see Photo 1. You will needto use four of the Digilent expansion cables and all of the16 available FPGA expansion pins to make this circuitoperate. The 8 x 8 LED matrix that is used is a Kingbright

part number TC15-11SRWA 1.5” dot matrix display fromwww.kingbrightusa.com for $4.76. When you look upthe Kingbright matrix, you’ll notice that the top surface isnot red like in Photo 1. If you cover the surface with redtail light repair tape, your letters appear brighter.

A complete schematic diagram is shown in Figure 1.The cathodes of the LEDs in the matrix are connected tothe column pins which are then taken to ground througheight 2N7000 FETs. Notice that no resistors are requiredwhen using these FETs in the manner shown here. Thegates of the FETs are connected to the eight columnoutputs from the Basys2 expansion connectors. Only one ofthese FETs will ever be on at one time because a ringcounter will be used to sequentially scan through them oneat a time over and over again at a fast rate, giving theillusion that all of the LED columns are lit at the same time.In reality, a maximum of eight LEDs will ever be on at thesame time. Each FET will conduct (at the most) 80 mA atone time; eight LEDs x 10 mA each = 80 mA. According tothe datasheets they are capable of conducting 200 mA.

The anodes of the LEDs are connected to the row pinson the matrix. The rows will be driven by eight FPGA pinsfrom the Basys2 expansion connectors in series with eight150 ohm resistors. These eight resistors are necessary tolimit the current from each FPGA row pin to 10 mA. TheLEDs drop 1.8V when conducting 10 mA. Therefore, 3.3V(a LVTTL logic “1”) – 1.8V = 1.5V and 1.5V / 10 mA = 150ohms of resistance. The FPGA pins can be configured in theUCF file to drive 16 mA. There will not be any problemsdriving the 64 LEDs in the matrix with the FPGA unless you

In the first article about FPGAs, the reader was introduced to the Digilent Basys2FPGA trainer and the Xilinx XC3S100E 100K gate FPGA in a 132-pin surface-mount package. The reader was shown how to enter a simple two input ANDgate in VHDL, compile the listing, generate a configuration bit file, anddownload that bit file into the FPGA and test it.

GettingStarted WithFPGAs —Part 2by David Ward

PHOTO 1

attempt to energize more than one column at a time. Now, let’s step through the VHDL and UCF listings line

by line and explain what is occurring; see Listings 1 and 2.By the way, this code displays the message “A,” “B,” “C,”and a blank as it scrolls from the right side of the matrixover to the left. The code has been commented here andthere to help the reader see what is being done. Commentsin VHDL are made by typing in two dashes (“—“) and thenyour comments. Comments are not compiled; they areignored by the Xilinx compiler. So, it won’t be necessary toelaborate on the comment lines such as lines 1 through 3.

Lines 5 through 9 are the “Entity” section of the VHDLcode listing. This is where ports or actual input and outputsignals are defined. Line 6 defines an input line named “clk”which is a single bit. The UCF file will direct this to pin B8of the FPGA where the Basys2 is connected to a 50 MHzclock signal; see line 1 of the UCF file in Listing 2. Line 7

defines an eight-bit output port named DISPLAY_C<0>through DISPLAY_C<7>. These are the eight bits that willgo out to the columns of the LED matrix. Their locations aredefined in lines 3 through 10 of the UCF listing. Line 8defines an eight-bit output port named DISPLAY_R<0>through DISPLAY_R<7>. These are the eight bits that will goout to the rows of the LED matrix. Their locations aredefined on lines 12 through 19 of the UCF listing. Line 9marks the end of the Entity section.

Lines 12 through line 56 are the “Architecture” sectionof the VHDL code listing. This is where the logical behaviorof the circuit is defined. Lines 14 though 16 set up a signalnamed ABC that is 256 bits wide. It is initialized with theones and zeros to display A, B, and C with a final blank screen.Line 17 sets up a signal called low_clk. This signal will be alower frequency signal derived from the higher 50 MHzsignal coming into the clk pin. Line 18 sets up a signal called

FIGURE 1

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64 SERVO 10.2011

ringcounter which is eight bits wide and is initialized to“00000001.” This signal will be constantly rotated left by onebit to drive the column scanning. Line 20 marks the beginningof the Architecture section after the signals have been defined.

Line 23 is the label for a process named “clk.” Aprocess operates sequentially in the FPGA instead of in aparallel manner. Line 24 defines two integer variables to beused in the process: inc and inc_2. They are both initializedto a value of zero. The first one, inc, will be incremented onevery positive going transition of the 50 MHz clock. Thesecond one, inc_2, will be incremented off of the low_clksignal to control the scrolling of the letters across thematrix. Line 25 marks the beginning of the clk process.

Lines 26 through 39 are four nested IF, THEN, ELSEstatements. Line 26 will increment inc by one on everypositive going transition (PGT) of the 50 MHz clock; this willoccur every 20 nS. Lines 27 and 28 determine that if inchas gotten up to 25,000 or that 500 μS have elapsed, thentoggle the low_clk signal. That is, if low_clk was previouslya 1, then make it a 0. If it was a 0, then make it a 1. Line29 increments inc_2 by one every time low_clk is toggled.

Line 30 determines that if inc_2 has gotten up to 125,

then reset inc_2 back to zero. Then, on line 31, rotate the256-bit signal ABC left by eight places. Line 32 determinesif inc_2 has not reached 125 yet, then don’t rotate ABC lefteight places; leave it as it was.

Line 33 is the END IF for line 30. Line 34 is the Else forline 28 for toggling the low_clk signal. Line 35 rotates theringcounter left by one place; this is for scanning thecolumns. Line 36 is the END IF for line 28. Line 37 resetsthe inc counter back to zero. Line 38 is the END IF for line27. Line 39 is the END IF for line 26.

Line 41 is where the signal ringcounter is actually sentout to the eight pins of DISPLAY_C<0> through DISPLAY_C<7>which is where the matrix column scanning takes place.

Lines 43 through 53 are a CASE structure. The CASEstructure will only find one of the lines from line 44through 51 true at a time. Since the CASE structure iscomparing to ringcounter to determine which line toexecute, it will step sequentially through them from line 44then on to line 45, etc., until reaching line 51. Sinceringcounter is rotated every 1 mS, then the CASE structurewill step through its eight choices every 8 mS. When theCASE structure finds a match — such as in line 44 when

—Basys2_ABC by David A. Ward May 2011—Displays ABC, this uses 64 bits per letter data —and scrolls R to L—clk info: 50MHZ = 20nS period applied to FPGA —pin B8

entity Basys2_ABC isPORT (clk : IN bit;—50MHZ clock coming in to pin B8DISPLAY_C : OUT bit_vector (0 TO 7);—8 column outputs to ground cathodesDISPLAY_R : OUT bit_vector(0 TO 7));—8 row outputs to source LED anodes

end Basys2_ABC;

—display info is 64 bits from row1 col1 down, every —8 bits is one column of dataarchitecture Behavioral of Basys2_ABC is—256 bits, 64 bits per full display, 4 displays; —A, B, C, and a blank

SIGNAL ABC : bit_vector(255 DOWNTO 0) :=

“0000000001111110100100001001000010010000011111100000000000000000000000001111111010010010100100101001001001101100000000000000000000000000011111001000001010000010100000100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000”;

SIGNAL low_clk : bit;—reduced frequency clockSIGNAL ringcounter : bit_vector(7 DOWNTO 0) := “00000001”; —init ring counter

BEGIN

—clock divider portion to reduce the F of the 50MHZ —clock down

PROCESS (clk)VARIABLE inc, inc_2 : integer := 0; —counter variable initialized to 0BEGINIF(clk’EVENT AND clk = ‘1’) THEN inc:= inc + 1; —increment on PGTIF(inc = 25000) THEN —toggle the low_clk 25,000 X 20nS = 500uS

IF(low_clk = ‘1’) THEN low_clk <= ‘0’; —toggle reduced clock signal

inc_2 := inc_2 +1; —increment scroll counter

IF(inc_2 = 125) THEN inc_2 := 0; —reset counter

ABC <= ABC rol 8; —time to scroll, rotate data 8 bits leftELSE ABC <= ABC; —not time to scroll, use past data

END IF;ELSE low_clk <= ‘1’; ringcounter <= ringcounter rol 1;—rotate ring counter

END IF;inc := 0; —clear count

END IF;END IF;

DISPLAY_C <= ringcounter;—8 lines used to energize 8 FET’s

CASE ringcounter IS—output letter data depending on switch settings

WHEN “00000001” => DISPLAY_R <= ABC(255 DOWNTO 248); —column 1

WHEN “00000010” => DISPLAY_R <= ABC(247 DOWNTO 240);

WHEN “00000100” => DISPLAY_R <= ABC(239 DOWNTO 232 );

WHEN “00001000” => DISPLAY_R <= ABC(231 DOWNTO 224);

WHEN “00010000” => DISPLAY_R <= ABC(223 DOWNTO 216);

WHEN “00100000” => DISPLAY_R <= ABC(215 DOWNTO 208);

WHEN “01000000” => DISPLAY_R <= ABC(207 DOWNTO 200);

WHEN “10000000” => DISPLAY_R <= ABC(199 DOWNTO 192); —column 8

WHEN OTHERS => DISPLAY_R <= “00000000”;END CASE;

END PROCESS;end Behavioral;

LISTING 1

ringcounter = “00000001” —then it will send out theupper eight bits of ABC toDISPLAY_R<0> throughDISPLAY_R<7>. This is wherethe eight LEDs on the eightrows are energized at theanodes and the FET fromcolumn 1 is turned on toground all of the cathodesfrom column 1. So, the CASEstructure is where the dataactually gets out to thematrix. As the CASE structurecycles through the eightringcounter values, it will display an entire 8 x 8 image.

This happens so rapidly that the human eye cannot seeit is actually scanning across the matrix and only lighting amaximum of eight LEDs at any one time. If the 256-bitsignal ABC is rotated left by eight bits or one column everyso often, then you can see the letters slowly scroll acrossthe matrix from right to left. Lines 54 and 56 mark the endof the process and the Architecture sections.

If you look at the UCF listing, you’ll see that it doesseveral other things than just locate or“LOC” signals from the VHDL listing withthe physical FPGA pins. The UCF also setsthe IOSTANDARD to LVTTL. There are over20 I/O standards available in this FPGA.The LVTTL stands for low voltage TTL,which means that a logic “1” is not 5.0Vbut 3.3V. The slew rate or the speed atwhich the signals transition from a 1 to a0 and vice versa are set to FAST. Theycan also be set to SLOW if the receivingdevices require it. Finally, the DRIVE is setto 16 mA. The drive can be set as low as2 mA and a maximum of 16 mA.

You will probably want to make upyour own messages since watching“ABC” slowly scrolling across isn’t veryexciting. By the way, entering all 256 ofyour 1s and 0s for your message isn’ttoo convenient, but it makes the VHDLlisting shorter and easier to follow.Figure 2 shows you how the data isgenerated for the letters so you candevelop your own messages. A blankform is included in the article downloads.

An easier way to generate yourmessages is to develop them column bycolumn in Notepad and then cut and pastethem into your code; see Listing 3. If youwant a longer message, the only thingthat needs to be changed is to paste yourextra letters into the end of the data at line16 and then increase the number (XXX)

in line 14 by 64 for each additional character, SIGNAL ABC:BIT_VECTOR (XXX DOWNTO 0). Of course, if you don’t changethe numbers in the CASE section (lines 43 through 53), themessage will start somewhere in the middle during the firstpass through, but it will appear correct after one pass.

Hopefully, you’ve enjoyed these articles on FPGAs and ithas given you a starting point to learn more about them andVHDL. Again, a good tutorial for VHDL is “The Low-CarbVHDL Tutorial” by Bryan Mealy available on the Internet. SV

8 X8 LED MATRIX FOR LETTER "A"

Co

lum

n 1

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D1

D0

Row 1 * Row 1 data 0 0 0 0 0 0 0 0

Row 2 * * Row 2 data 0 0 1 1 1 1 1 0

Row 3 * * Row 3 data 0 1 0 1 0 0 0 0

Row 4 * * * * * Row 4 data 1 0 0 1 0 0 0 0

Row 5 * * Row 5 data 0 1 0 1 0 0 0 0

Row 6 * * Row 6 data 0 0 1 1 1 1 1 0

Row 7 * * Row 7 data 0 0 0 0 0 0 0 0

Row 8 Row 8 data 0 0 0 0 0 0 0 0

"B"

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Row 1 * * * * Row 1 data 0 0 0 0 0 0 0 0

Row 2 * * Row 2 data 1 1 1 1 1 1 1 0

Row 3 * * Row 3 data 1 0 0 1 0 0 1 0

Row 4 * * * * * Row 4 data 1 0 0 1 0 0 1 0

Row 5 * * Row 5 data 1 0 0 1 0 0 1 0

Row 6 * * Row 6 data 0 1 1 1 1 1 0 0

Row 7 * * * * Row 7 data 0 0 0 0 0 0 0 0

Row 8 Row 8 data 0 0 0 0 0 0 0 0

"C"

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Row 1 * * * Row 1 data 0 0 0 0 0 0 0 0

Row 2 * * Row 2 data 0 1 1 1 1 1 0 0

Row 3 * Row 3 data 1 0 0 0 0 0 1 0

Row 4 * Row 4 data 1 0 0 0 0 0 1 0

Row 5 * Row 5 data 1 0 0 0 0 0 1 0

Row 6 * * Row 6 data 0 1 0 0 0 1 0 0

Row 7 * * * Row 7 data 0 0 0 0 0 0 0 0

Row 8 Row 8 data 0 0 0 0 0 0 0 0

FIGURE 2

NET “clk” LOC = B8;

NET “DISPLAY_C<0>” LOC = B7 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<1>” LOC = C5 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<2>” LOC = B6 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<3>” LOC = C6 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<4>” LOC = B5 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<5>” LOC = J3 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<6>” LOC = A3 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_C<7>” LOC = B2 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;

NET “DISPLAY_R<0>” LOC = A9 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<1>” LOC = A10 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<2>” LOC = D12 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<3>” LOC = B9 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<4>” LOC = C9 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<5>” LOC = C13 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<6>” LOC = C12 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;NET “DISPLAY_R<7>” LOC = A13 | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 16;

LISTING 2

A000000000111111010010000100100001001000001111110

0000000000000000

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LISTING 3

SERVO 10.2011 65

HandsOn Technology

http://www.handsontec.com

Low Cost 8051C Starter Kit/ Development Board HT-MC-02 HT-MC-02 is an ideal platform for small to medium scale embedded systems development and quick 8051 embedded design prototyping. HT-MC-02 can be used as stand-alone 8051C Flash programmer or as a development, prototyping and educational platform

Main Features:

8051 Central Processing Unit. On-chip Flash Program Memory with In-System Programming (ISP) and In Application

Programming (IAP) capability. Boot ROM contains low level Flash programming routines for downloading code via the RS232. Flash memory reliably stores program code even after 10,000 erase and program cycles. 10-year minimum data retention. Programmable security for the code in the Flash. The security feature protects against software

piracy and prevents the contents of the Flash from being read. 4 level priority interrupt & 7 interrupt sources. 32 general purpose I/O pins connected to 10pins header connectors for easy I/O pins access. Full-duplex enhanced UART – Framing error detection Automatic address recognition. Programmable Counter Array (PCA) & Pulse Width Modulation (PWM). Three 16-bits timer/event counters. AC/DC (9~12V) power supply – easily available from wall socket power adapter. On board stabilized +5Vdc for other external interface circuit power supply. Included 8x LEDs and pushbuttons test board (free with HT-MC-02 while stock last) for fast

simple code testing. Industrial popular window Keil C compiler and assembler included (Eval. version). Free Flash Magic Windows software for easy program code down loading.

PLEASE READ HT-MC-02 GETTING STARTED MANUAL BEFORE OPERATE THIS BOARD

INSTALL ACROBAT READER (AcrobatReader705 Application) TO OPEN AND PRINT ALL DOCUMENTS

High power, high quality discrete Class D amplifier

http://www.handsontec.com

The Universal Class D (UcD) version 1.00 demonstrator board implements a 200 W true RMS (into a 4 W load) high quality audio power amplifier on a very compact printed-circuit board. The amplifier is built-up of discrete components only.

The Class D concept allows efficient and cost-effective high output power audio amplifiers to be created. The Universal Class D (UcD) principle enables PWM amplifiersto perform at an excellent sonic level while making use of a relatively simple closed-loop topology.

For detail technical specifications of this discrete design, please visit: http://www.handsontec.com