Global Trigger Global Muon Trigger

Claudia-Elisabeth WulzAnton TaurokInstitute for High Energy Physics, Vienna

Hannes SakulinCERN

Annual ReviewCERN, 24 Sep. 2001

Global TriggerGlobal Muon Trigger

Claudia-Elisabeth Wulz 2 Annual Review, 24 Sept. 2001

URL’s

This talk may be found at:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTrigger/trans/wulz_AnnRev_sep01.ppt

More detailed transparencies prepared by H. Sakulin about the Global Muon Trigger may be found at:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GMT-IntReview24Sep2001.pdf

More detailed transparencies about the Global Trigger prepared by A. Taurok and presented at the Trigger Meeting on Tuesday, 25 Sep. 2001, may be found at:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger/trans/GT_GTM_status_Sept01.ppt

General information about the Global Trigger and the Global Muon Trigger is available at:http://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalTriggerhttp://wwwhephy.oeaw.ac.at/p3w/cms/trigger/globalMuonTrigger


Global Trigger Environment


Board Layout of the Global Trigger Processor

PSB (Pipeline Synchronizing Buffer) Input synchronizationGTL (Global Trigger Logic) Logic calculationFDL (Final Decision Logic) L1A decisionTCS (Trigger Control System Module) Trigger ControlNEW: L1A (Level-1 Accept Module) Delivery of L1ATIM (Timing Board) TimingGTFE (Global Trigger Frontend) Readout

FromDetector

To EVM

To TTC

Backplane andReadout links

PSB GTL FDL TCS L1A

ToDAQ

GTFE

FromTTC

TIM

FromPartitions


Global Trigger 9U Crate (old)

READOUT _ links

8 RPC muons4 DT muons

4 CSC muons

4TAU4 fwdJet4 Calo*

4 Calo* =total-ET, missing-ETNr_ jetsA, Nr_ jetsB

GTMU

GTMU

PSB12

GTL32

GTL32

PSB12

PSB12

PSB12

PSB12

PSB12

24

24 ch ISO and MIP

bits

6

4 centrJET4EG4IEG

4

TIM FDL GTL32

PSB12

32xL1A, COMMANDS

to TTCvi

TTCfibre

12

GT crate VME 9U

4 MUONS parallel

FAST SIGNALS:Warning, Inhibit,... ...from Subsystems

CLOCK, BCR, ...

6

12ISO+MIP

Global Muon Trigger

PSB12

int.conn.

GT-part of

TriggerControl

GT Receiver Crate 6U

Parallel toChannel Link

conversion

DAQfibre

GTFE

4 free4 unusable

EVMfibre

3 standard

VMEslots

Backplane

TCS

Global Trigger

8


Global Trigger 9U Crate


Global Trigger Rack


Global Trigger Progress and MilestonesMilestone March 2002: System Test

This includes the backplane, the PSB-6U, GTL-6U, FDL-9U and TIM-9U. The GTFE and the GMT are not included. Backplane-6U: Prototype availablePSB-6U: available. Channel Link receivers used.

• GTL-6U: Automatic chip design and setup procedure developed. Layout for a 20 channel GTL (4 , 4 isol. e/, 4 central jets, 4 fwd jets, ET, ET

miss, 8 jet multiplicities; other quadruplets can be connected alternatively for tests) is currently being finished. 1020-pin Altera FPGA 20k400E included for evaluation. The layout of a conversion board to be used later in final 9U-crate is ready. It contains also memories in FPGA’s to send simulated test data to the GTL-6U board.

• FDL-9U: Design with 8 final OR’s in progress.

• TIM-9U: The design of the board is nearly finished. The board contains a TTCrx chip and provides all timing signals for the GT crate. It will be used also in the Drift Tube Track Finder crates. An FPGA provides all necessary test functions to run the crate without the central TTC clock. It simulates also L1A requests for monitoring or to test the readout chain.


Global Trigger Progress and Milestones

Milestone July 2002: TCS-9U ready

• TCS-9U: The main functions are defined but the design is still open for additional requests (calibration logic etc.)Trigger Partitions: The maximum number of subsystems is fixed (32).A preliminary agreement about the output to the DAQ Event Manager is has been reached.The input format of Fast Signals should be fixed soon. 5 coded bits per subsystem, sent as parallel data, are proposed.The TCS board provides data for the standard TTCvi as well as for a ”CMS-TTCvi”, but different interface boards are required. L1A driver module to be used with CMS-TTCvi has been conceived.


Global Trigger Progress and Milestones

Milestone October 2002: 9U backplane readyThe design with the GTLp 80 MHz and Channel Links is in progress.

Milestone June 2003: Complete GT prototype availableIntegration tests possible from this date.•GTFE-9U: Conceptual design of readout board done.

Milestone July 2004: 12-channel PSB-9U available• PSB-9U: Conceptual design done. Will have memories inside FPGA’s.

Milestone Nov. 2004: Complete GT availableIncludes GTL-9U module with all 32 input channels (4 , 4 isol. e/, 4 non-isol. e/ , 4 central jets, 4 forward jets, 4 -jets, ET, ET

miss, 8 jet multiplicities). The Global Muon Trigger will have been completed by Nov. 2003.


Global Muon Trigger

RPCCaloTrigger DTBX CSC

PACTPattern

Comparator

TRACOTrack Correlator

Trigger Server

DTBarrel

Track Finder

Wirecards

Stripcards

Motherboard

CSCEndcap

Track Finder

DTSorter

CSCSorter

RPCSorter

CALReadout

Regional CALOTrigger

GLOBAL MUON TRIGGER

GLOBAL L1 TRIGGER

GLOBAL CALORIMETER

TRIGGER

4+4 4 4

4

MIP &quiet bits

(2x 252)

HEPHY Vienna

HEPHY Vienna

HEPHYVienna

Bologna Rice

Florida

BariBristol

BTIBunch & Time ID

WarsawWisconsin

L1 Accept ………… max. 100 kHz

Pipe-lined

40 MHz


Tasks and Location of the Global Muon Trigger

Receive Muon Candidates from DT, CSC and RPCTriggersFind the best 4 muons in the detector

Make use of the complementarity of the muon triggersystems (DT/RPC barrel, CSC/RPC endcap)

increase efficiency reduce ghosts reduce trigger rate by improving pT assignment

Add MIP and Quiet bits from the calorimeter triggerForward best 4 muons to the Global L1 TriggerGMT is located in the GT crate. It consists of 3 input boards (PSB) for the calorimeter information and 1 logic board. 3 additional slots used due to connectors.


Principle of the Global Muon Trigger•Inputs:8 bit , 6 bit , 5 bit pT, 1 bit charge, 3 bit quality

•Output:8 bit , 6 bit , 5 bit pT, 1 bit charge, 3 bit quality, 1 bit MIP, 1 bit Isolation

•Further Inputs:MIP and Quiet Bits of252 calorimeter regions

Responsible: H. Sakulin, A. Taurok, C.-E. Wulz

3 programmable merging modes:winner/loserparameter selectionparameter mixing


Global Muon Trigger Schedule

Milestones / Plans:2001 Logic design, ORCA + VHDL SimulationDec 2001 Logic design finished2002 VHDL Simulation, Design of FPGA chipsDec 2002 FPGA design finished2003 Production of VME 9U Boards2004/05 Integration tests, production of spare boards


Progress towards GMT milestones

Dec 2001: Logic design finished Progress in detailed logic design

• Chip Models selected (mostly Virtex II), interconnections defined• Design compacted (external RAMs moved into big FPGAs)

Improvement of functionality• DT/CSC cancel-out unit (improved performance in barrel/endcap overlap

region)

in parallel: • ORCA simulation extended and improved• Continuous studies to optimize GMT design parameters and performance

– CMS Note 2001/003 published: H. Sakulin, M. Fierro, “Studies of the Global Muon Trigger Performance”

Detailed GMT design document in preparationVHDL behavioral level simulation has started

Dec 2002: FPGA design finished FPGA models have been selectedSynthesis tools are being evaluated


New: GMT solution with 1 logic board


Simulation - muon 2001 production

ÿ Monte Carlo production (Pythia 6.152, CMSIM 121) new normalization (now Pythia default)

lower pT-cut (p-cut) in forward region(now p > 3.5 GeV/c, was pT>1.5 GeV/c)

increased - range in CMSIM( 5.5, 2.5)now was

- muons in pile up vetoed LHC luminosity=2 10L x 33cm-2s-1

ÿ 1 ( 5.1.2)L Trigger simulation ORCA new CSC Trigger primitives updated CSC Trigger updated Global Muon Trigger

• / MIP ISO bit assignment implemented• / - new DT CSC cancel out unit• matching windows and charge assignment improved

: RPC without noise and neutral background simulation

Sample Lint/nb-1 Eventsinluminosity

mu_MB1mu_pt1 0.0173 162kmu_MB1mu_pt4 0.2052 54kmu_MB1mu_pt10 2.81 41kW_1mu 2856. 43kZ_1mu 2336. 50kmu_MB2mu 0.0989 11kbackgroundsamples–2001muonproduction


Simulation - muon 2001 production

GMT optimized as in ORCA 5.1.2 rate at 20 GeV/c: 3.1 kHz

L1 efficiency(*): 96.6 %

re-tuned GMT selection:Only three-station CSC tracks used

without RPC confirmation

rate at 20 GeV/c: 1.4 kHz

L1 efficiency(*): 96.3 %

(*)efficiency to find muon of any pT in flat pT

sample

Rate from unconfirmed 2-station CSC tracks

GM

T s

ing

le m

uo

n t

rig

ger

rat

es (

pT >

16

GeV

/c) ORCA 5.1.2

re-tuned GMT


L1 efficiency with retuned GMT

GMT efficiency to find any muon in a flat pT sample as in ORCA 5.1.2 w/o RPC noise

ORCA 5.1.2 eff= 96.6%re-tuned eff= 96.3 %

Efficiency contribution from CSC Q2 muons

(lost with re-tuning)

Eff

icie

ncy

/%


Single muon rates

Trigger rate at 20 GeV/c (re-tuned GMT) 1.4 kHz (last year: 2.9 kHz)

Generated rate at 20 GeV/c ~120 Hz (last year: ~200 Hz)


Dimuon rates


Single muon and dimuon trigger rates


GT and GMT Manpower

System Engineer:

A. Taurok

CERN Doctoral Student:

H. Sakulin (Logic and Hardware Design of GMT)

Technicians: (shared with DTTF and other activities)

H. Bergauer, M. Padrta, K. Kastner (in Vienna)

Ch. Deldicque (at CERN)

Physicists:

M. Fierro, A. Jeitler, C.-E. Wulz (mainly working on GT/GMT)

N. Neumeister, P. Porth, H. Rohringer, L. Rurua (partly working on other activities)

L. Boldizsar (GT simulation, about 4 months per year in 2001 and 2002)


Conclusions

Progress in hardware design as planned

Global Trigger:

Layout of GTL-6U almost ready

Timing module designed

Other modules also on track

Design of TCS system updated

Global Muon Trigger:

FPGA chips selected

Design compacted

New solution with one logic board

VHDL simulation has started


Conclusions

New simulation results with muon 2001 production for Global Muon Trigger

pT-cut was lower than in last year’s production

improved CSC trigger & GMT can cope with higher background rate

trigger rates with improved trigger are lower despite higher background (even after taking into account the changed sample normalization)

Documents

Global Trigger Global Muon Trigger