External Use

TM

Hands-On Workshop: Kinetis L

Series MCUs Using Processor Expert

with IAR Embedded Workbench

FTF-SDS-F0067

A P R . 2 0 1 4

Michael Steffen | Sr. Field Applications Engineer

TM

External Use 1

Session Introduction

This is a hands-on class using Processor Expert Driver Suite together with

the IAR Embedded Workbench for ARM®. The Project Connection feature

is used to connect the tools and create projects from scratch to run on the

FRDM-KL25Z Freescale Freedom development platform. This class will

introduce the technical advantages Kinetis L series MCUs offer. Additional

topics will include an enablement overview with a focus on the Freescale

Freedom development platform, Processor Expert, and MQX Lite, which

give designers a jump start in learning the architecture and developing

applications for Kinetis L series devices. Hands-on labs will be performed to

introduce the attendees to Processor Expert and the method of configuring

device drivers for peripherals including timers and GPIO. The lab projects

will be extended to add the MQX Lite operating system. The class will use

the Freescale Freedom development platforms based on Kinetis MCUs,

which each attendee can take home.

TM

External Use 2

Session Objectives

Class attendees should leave with a solid understanding of the following concepts: 1. OpenSDA Architecture and the MSD and Debugger use models

2. Processor Expert (PEx): What it is and is not!

3. How to integrate PEx with a third-party tool

4. How to use PEx to add logical device drivers

5. How to create and extend an MQX-Lite application

6. Understand the Freescale Community and mbed.org and how to use them to benefit all

Class attendees will leave with: 1. A FRDM-KL25Z Freescale Freedom development platform

2. Step-by-step lab guides and all project files

3. Relevant FRDM-KL25Z, Kinetis KL25 device, and OpenSDA documentation and files

4. Pointers to web resources for related topics and tools

TM

External Use 3

Sample Learning Objectives

• By completing this training, you will be able to:

− Choose the appropriate Kinetis L series device based on your application

− Understand the low power features of Kinetis L series MCUs

− Use Processor Expert together with IAR to create and debug an

application

TM

External Use 4

Agenda

Kinetis L Series MCU Family Overview

Lab 1: OpenSDA Basics

This lab will cover OpenSDA, IAR and build/debug steps.

Lab 2: Create Basic Project using PEx and IAR

This lab will introduce PEx and how to tie in with IAR.

Lab 3: Create MQX-Lite Project

This lab will create an MQX-Lite project from scratch and add some components.

Lab 4: Add Serial Console, GPIO and Timer Components

This lab will add some simple and useful PEx components.

TM

External Use 5

Microcontroller Applications

Today

TM

External Use 6

Application Implications for Entry-Level MCUs

+ -

× ÷

sin log n √ ∫

x

n

Scalable, reusable platforms with

modern software techniques/$

Unique platforms,

MCU dependent/$$$

Broad MCU portfolios,

multi-source

Limited choice,

single-source

32-bit MCU 8-/16-bit MCU

Maximum

energy-efficiency

(CoreMark/mW)

Ultra low sleep/

power-down

currents

Connectivity

User Interface

Power

Consumption

Computation

Software/Cost

of Ownership

Scalability

TM

External Use 7

Kinetis L Series

MCUs The evolution of the

entry-level MCU

Energy-efficiency

Class-leading CoreMark/mA

Scalability & Integration Migration between Kinetis L & K series MCUs

Enablement

ARM® ecosystem

Low-power

Low STOP/RUN Idd, rapid wake-up

Low-cost

From <$0.50

Ease-of-use

Processor Expert

Kinetis L Series MCUs – The Best of Both Worlds

TM

External Use 8

Freescale Kinetis L Series

Microcontrollers

TM

External Use 9

Kinetis K Series MCUs Kinetis L Series MCUs

ARM® Cortex ® -M0+ ARM® Cortex ® -M4

( with optional SPFPU ) Processor

Typical ~50uA/MHz

( VLPR Mode )

Typical ~200uA/MHz

( VLPR Mode ) Ultra Low Power

8kB – 256kB Flash

1kB – 32kB SRAM

32kB – 1MB Flash

8kB – 128kB SRAM Memory

16 – 121 Pin 32 – 256 Pin Pin-Count

Baseline / Mixed-Signal

and optional

Segment LCD,

USB

Baseline / Mixed-Signal

and optional

FlexMemory, USB,

Segment LCD, CAN, Ethernet,

Graphic LCD, DRAM-CTRL,

NAND-Flash-CTRL, Crypto, Anti-

Tamper

Features

From $0.49

( MKL02x, 8KB, 16QFN )

From $0.99

( MK10x, 32KB, 32QFN ) Price

Up to

48MHz

Up to

50 / 72 / 100 / 120 / 150MHz Performance

www.freescale.com/FREEDOM

www.freescale.com/TOWER Demo Board

www.freescale.com/KINETIS

TM

External Use 10

Kinetis MCU Portfolio Scalability F

ea

ture

In

teg

rati

on

<=24pin 32pin 48pin 64pin 80pin 100pin 121pin 144pin 256pin

Kinetis K10 Family 50-120MHz, 32KB-1MB, Low Power, Mixed Signal

Kinetis K20 Family 50-120MHz, 32KB-1MB, USB OTG (FS/HS)

Kinetis K30 Family 72-100MHz , 64-512KB, Segment LCD

Kinetis K40 Family 72-100MHz, 64-512KB, USB OTG (FS), SLCD

Kinetis K50 Family 72-100MHz, 28-512KB,

Analogue, USB OTG (FS), E’net, SLCD, Encryption

Kinetis K60 Family 100-150MHz, 256KB-1MB,

Ethernet, USB OTG (FS/HS), Encryption, Tamper Detect, DRAM

Kinetis K70 Family 120/150MHz,

512KB-1MB, Graphics LCD, Ethernet,

USB (FS/HS) Encryption, Tamper, DRAM

Kinetis K Series MCUs ARM Cortex M4 50-150MHz

Kinetis KL0 Family 8-bit S08P compatible

Kinetis KL1 Family General Purpose

Kinetis KL2 Family USB OTG (FS)

Kinetis KL3 Family SLCD

Kinetis KL4 Family USB OTG (FS), SLCD

Kinetis L Series MCUs ARM Cortex M0+ 48MHz

Pin Count

TM

External Use 11

Migration between Kinetis K and L Series MCUs

KL25

48-pin

Cortex-M0+

1

12

13 24 2

5

36

37 48

AD

C

GP

IO e

tc

Digital

Power

ADC DP

Ch

GPIO etc.

Analog

Power

USB

HS

CM

P

AD

C

TS

I

GP

IO e

tc

Dig

ital

Pow

er

DA

C/A

DC

HS

CM

P

GP

IO e

tc.

SW

D

ADC/TSI

GPIO etc.

Clock

GPIO etc

Reset

GPIO LLW

U

GP

IO

K20

48-pin

Cortex-M4

1

12

13 24

25

3

6

37 48

AD

C

GP

IO e

tc

Digital

Power

ADC DP

Ch

Analog

Power

USB

HS

CM

P

AD

C

VR

EF

OU

T

TS

I

GP

IO e

tc

Dig

ital

Pow

er

Clo

ck (

32K

)

Vbat

SW

D

JT

AG

ADC/TSI

GPIO etc.

Clock

(3~32M)

GPIO etc

Reset

GPIO

LLW

U

GP

IO

Follow Same

Pin Assignment Rule

Fully Hardware Compatible

Same Peripheral Register

Setting for common features

Software Compatible,

C-Code Reusable

Check Hardware difference

Power Pin (Vbat)

External Clock Input

(32KHz/3~32MHz)

Analog interface (DAC,

Vref_Out)

Debug Interface (JTAG)

GPIO pinmux

Step 1

Check Software difference

DMA configuration

Watchdog Service Routine

Low Power usecase (New

features added on L-Series)

BME (new on L-Series)

MTB (new on L-Series)

GPIO Map (More on L-Series)

Flexmemory (K-Series only)

Step 2

Optimize the Design

Adopt new head file and

reuse the C code by modifying

the difference

Add new features support

in design that specific to L-

Series or K-Series

Step 3

Take 3 Steps for easy Migration:

* Detail technical migration guide will be available on Freescale website

TM

External Use 12

Kinetis L Series MCUs – Family Overview

USB + Seg. LCD

KL3x

KL1x KL1x

KL1x KL1x

KL2x KL2x KL2x

KL2x

KL2x KL2x KL2x

KL2x KL2x

KL4x

KL3x

KL4x

KL4x

KL3x

KL4x

KL2x

KL1x

KL2x

KL1x

KL1x

KL1x

KL2x

KL1x KL1x KL1x

KL3x

KL2x

KL3x

KL2x

KL2x

KL1x

KL2x

KL1x

KL1x

Segment LCD

USB

General Purpose

Entry Level

Flash

Memory

128KB

64KB

32KB

16KB

8KB

256KB

KL0x

KL0x

KL0x

KL0x

KL0x

100 LQFP /

121 MBGA 80 LQFP 64 LQFP 48 LQFP

/QFN

32 LQFP

/ QFN 24 QFN 35

WLCSP

KL2x

KL1x

KL0x

KL0x

KL0x

16 QFN

KL0x

KL0x

KL0x

Small Footprint Package

KL3x

20 WLCSP

KL0x

Package

TM

External Use 13

Analog Interfaces

System

Peripheral Bus

Energy Management

Power On

Reset

Low Voltage

Detector

Voltage Regulator

Clock Management

FLL

LS Osc

(32KHz,

2%)

Timers

2ch

32bit

PIT

SRTC w/

temperature

compensation

I/O Ports Connectivity

I2C x 2 12-bit

DAC HSCMP

Debug

(SWD)

COP

RST

Unique ID

DMA

4-ch

TSI x

16ch

Up to 84 GPIO

(4 High Dive)

w/ 25 interrupt

LPO

(1KHz)

RST/

Input

ULP Osc

(4MHz,

5%)

LPTMR

Crystal

Oscillator

(low&high

range)

16b LPTPM

6ch x1, 2ch x 2

SPI x 2

4chDP+ 8chSE 16-bit

/ 16chSE 12bit

SAR ADC /w DMA

Run Operation in: Wait VLLS

1

VLLS

0 Stop/

VLPS

VLLS

3

USB OTG

FS/LS

Transceiver

USB Regulator

USB Controller

Display

SLCD

51x8/55x4

PLL

Audio

I2S

ARM Cortex-M0+ Ultra-low power

48MHz bus freq.

Flash

32-256K RAM 4-32K

LPSCI

x 1

SCI

x2

Block Diagram – Kinetis L Series MCU Family Superset

TM

External Use 14

MCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest

power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational.

MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking

option. LVD protection is off and flash programming is disallowed.

Allows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option.

Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option.

MCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature

that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU.

Lowest power mode with option to keep PLL active.

MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-

up source for CPU.

MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and

select pin interrupts. Fast <4.3us wake-up.

MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states

held. LLWU controls wake-up source for CPU similar to LLS mode.

Similar to VLLS3 with no RAM or register file retention.

Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention.

Optional POR brown-out detection circuitry.

Ultra-Low Power Modes

Run

Wait

VLL Stop 1 (VLLS1)

VLL Stop 0 (VLLS0)

Stop

VLL Stop 3 (VLLS3)

VLP Run (VLPR)

VLP Wait (VLPW)

VLP Stop (VLPS)

LL Stop (LLS)

RU

N

SL

EE

P

DE

EP

SL

EE

P

Expands beyond typical run, sleep and deep sleep modes with power options

designed to maximize battery life in varying applications

TM

External Use 15

Energy Efficiency: Energy = Power x Time

RUN @3V, 48 MHz 84 uA/MHz

VLPR @3V, 4 MHz 47 uA/MHz

VLLS0 Deep Sleep @3V 176 nA

LLS Deep Sleep @3V 1.9 uA

CoreMark/MHz 1.77

LLS Wake-up Time 4.3 us

Time

Very Low Active and Standby

Power Consumption Energy Saving Peripherals Reduced Processing Time

Po

we

r

Initialization Control Compute

Deep Sleep Mode E

NE

RG

Y S

AV

ING

S

Ultra-low

Standby

Current

Ultra-low

Active

Current

TM

External Use 16

Kinetis MCU

Power Modes Recovery Time

Kinetis KL25 MCU Typical

Idd @ 3V and 25C

Leading Dynamic Power - 4.1 mA*/ 6.4 mA***

Innovative low power process technology (C90TFS) - 188 uA*/ 980 uA***

Low Power focused Platform Design 15 cycles** 2.9mA @ 24MHz

Next Generation Cortex M0+ core 15 cycles** 135uA @ 4MHz

Asynchronous DMA Wake-up (ADMA) 2us+15 cycles 345uA

Energy-saving peripherals are operational with ADMA

feature that can wake-up DMA to perform transfer and

return to current mode when complete 2us+15 cycles 4.4uA

Low Leakage Wake-up Unit 2us+58 cycles 1.9uA

Enables complete shut-down of core logic, including AWIC,

further reducing leakage currents in all low power modes 42us 1.4uA

Supports 8 external input pins and 8 internal modules as

wakeup sources; extends the low power wake-up

capability of some internal peripherals to all power modes. 93us 700nA

Wake-up inputs are activated in LLS or VLLS modes 95us 176nA****/381nA****

Breakthrough Power Efficiency

RUN

VLPR

WAIT

VLPW

STOP

VLPS

LLS

VLLS3

VLLS1

VLLS0

*Compute Operation enabled: 4.1mA @ 48MHz core / 24MHz bus)

** Compute Operation enabled: 188uA @ 4MHz core / 800kHz bus)

*** Running Coremark algorithm, KEIL 4.54 optimized for speed

****with and without POR enabled

TM

External Use 17

Kinetis L Series MCUs – AWIC and LLWU Wake-up source Description

Available system resets RESET pin when LPO is its clock source

Low-voltage detect Power management controller - functional in Stop mode

Low-voltage warning Power management controller - functional in Stop mode

Pin interrupts Port control module - any enabled pin

ADC The ADC is functional when using internal clock source

CMP0 Interrupt in normal or trigger mode

I2C Address match wakeup

UART0 Any interrupt provided clock remains enabled

UART1 and UART2 Active edge on RXD

RTC Alarm or seconds interrupt

TSI Any interrupt

NMI NMI pin

TPMx Any interrupt provided clock remains enabled

LPTMR Any interrupt provided clock remains enabled

SPI Slave mode interrupt

Asynchronous

Wake-up

Interrupt

Controller

Multiple

wake-

sources

selectable

TM

External Use 18

Kinetis L Series MCUs – AWIC and LLWU

Wake-up source

PTB0

PTC1

PTC3

PTC4

PTC5

PTC6

PTD4

PTD6

LPTMR0

CMP0

TSI0

RTC Alarm

RTC Seconds

The LLWU

implements

optional 3-

cycle glitch

filters, based

on the LPO

clock.

Low

Leakage

Wake-up

Unit

TM

External Use 19

ARM® Cortex® -M0+ Processor

TM

External Use 20

ARM® Cortex®-M Processor Series

TM

External Use 21

Fully upward compatible Architecture Family

ARM® Cortex®-M Series Instruction Sets

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (SP)

r14 (LR)

r15 (PC)

PSR

32-bits

TM

External Use 22

ARM® Cortex®-M0+ Processor

Single-Cycle I/O Port • 50% higher GPIO toggling

frequency than standard

I/O

• Improves reaction time to

external events allowing

bit-banding and software

protocol emulation

• Save precious cycles, e.g.

set faster peripherals for

low-power access

• Access GPIO/peripherals

while processor fetches

the next instruction

Energy-Efficiency • 2-stage pipeline – reduced

cycles per instruction (CPI)

enabling faster branch

instruction and ISR entry

• Program memory access on

alternate cycles

Micro Trace Buffer • Powerful, lightweight trace

solution enabling fast

debug

• Non-intrusive – trace

information stored in small

area of MCU SRAM (size

defined by programmer)

• Trace read over Serial

Wire /JTAG (CPU stopped)

Processing • Only 56 Instructions,

mostly coded on 16-bit.

Option for fast MUL 32x32

bit in 1 cycle

• Cortex-M0/3/4 compatible

• 1.77CM/MHz

• Best-in-class code density

vs. 8/16-bit architectures –

reduced cost, power

consumption and pin-count

TM

External Use 23

Higher efficiency on branch

• In pipelined processors, subsequent instructions are fetched while executing current instructions

• In 2-stage pipeline: − Branch shadow is reduced and energy is saved!

− Branch turn-around is 1 cycle faster!

3-stage

pipeline

2-stage

pipeline

Instructions fetched/decoded

but not used

TM

External Use 24

Minimizing Power at System Level

• Program memory access (e.g. Flash) generally on alternate cycles:

• Load 2x16-bit instructions every two cycles

• Cortex-M0+ powers only half the bus on unaligned access to save energy

NSEQ

a4

IDLE NSEQ

a6

IDLE

i4 i5 i6 i7

i4 i5 i6i3

i4 i5i2 i3

AHB

access

CPU

pipeline

HTRANS

HADDR

HRDATA

Fetch

Execute

TM

External Use 25

• Optimizing consumption

− Gate count optimized, starting 12kGate

− Reduced accesses to the program memory

• Save precious runtime cycle:

− 32-bit processing capability

− Shorter 2-stage pipeline: faster non-sequential accesses

• Dynamic Power scales well with process

− But beware of static consumption

− 90 nm is a good trade-off

0

10

20

30

40

50

60

40nm 90nm

180nm

3

11

52

42

1 0

uW for

minimal

configuration Static Dynamic

ARM® Cortex® -M0+: Energy Efficient By Design

TM

External Use 26

Enablement

TM

External Use 27

Freescale’s Microcontroller Enablement Bundle

Hardware System

Open source hardware

platform for prototyping

application development

+ Freescale MQX

Comprehensive solution for

embedded control

and connectivity

Create, configure, optimize,

migrate, and deliver

software components

+ Processor Expert + IAR IDE

Reliable, Powerful,

and Easy to use IDE

to accelerate

development time

Freescale MQX Lite

RTOS • Free, light-weight MQX kernel

customised for small resource

MCUs

• Packaged as a Processor Expert

component

• Upwards compatible with MQX

RTOS

TM

External Use 28

Evaluation Platforms and

OpenSDA

TM

External Use 29

Freescale Freedom Development Platform

FRDM-KL25Z $12.95SRP

www.freescale.com/FRDM-KL25Z

• Ultra low cost development platform

• Quick and simple with easy access to MCU I/O

• New, sophisticated OpenSDA Debug interface: mass storage device flash programming interface, P&E Multilink interface for run-control debugging, open-source Data Logging application

• Loaded with software: Processor Expert: stand-alone or IDE integrated, MQX Lite RTOS (via Processor Expert) and ecosystem partner support from IAR, Keil, Code Red, Atollic, Rowley, Free GNU command-line tools with GDB server

Freescale Tower System Platform

TWR-KL25Z48M $99.00 SRP

• www.freescale.com/TWR-KL25Z48M

• Modular, open-source development platform with reusable peripheral modules offering connectivity, analog, graphics LCD and motor control functionality

Kinetis L Series MCUs Hardware Enablement

TM

External Use 30

KL25Z

80 LQFP

IO Headers*

Cap Touch

Slider RGB LED

Serial

Flash*

MMA8451Q

Accelerometer

OpenSDA

Debug*

OpenSDA

Reset

USB

Device

KL25Z

Debug*

Power Supply

Shunts*

FRDM-KL25Z Callouts

* Not Installed

Arduino Form Factor

TM

External Use 31

OpenSDA Overview

• Embedded Serial Debug Adapter − New standard for embedded debug

circuit supporting SWD and JTAG

− Open hardware platform with proprietary and open-source software

− Built on K20DX128 50MHz CM4

− Provides serial channel and debug interface to the target MCU

• Mass-storage bootloader used to load new applications into the OpenSDA

• A mix of proprietary and open-source OpenSDA Applications will be available free-of-charge from Freescale − Customers and partners can

develop their own Applications as well.

MSD Bootloader

OpenSDA MCU K20DX128Vxx5

OpenSDA

Application

UART TX/RX UART RX/TX

OpenSDA

SPI, GPIO SWD / JTAG

GPIO / Interrupt RESET

to Target MCU

TM

External Use 32

OpenSDA Applications Overview

MSD Bootloader

OpenSDA MCU K20DX128Vxx5

OpenSDA

Application

UART TX/RX UART RX/TX

OpenSDA

SPI, GPIO SWD / JTAG

GPIO / Interrupt RESET

Open Debug

Standard

Cloud

Computing

Interface

Mass Storage

Programmer P&E Multilink

Customer / Partner

Application

Proprietary

Proprietary

Open or Proprietary

Open

Proprietary, Default

to Target MCU

Data Logging

Open

TM

External Use 33

Freescale Processor Expert and

IAR Embedded Workbench

TM

External Use 34

Overview of IAR Embedded Workbench

IAR Embedded Workbench IDE

IDE tools

Editor

Project manager

Library builder

Librarian

Build tools

IAR C/C++ Compiler

Assembler

Linker

IAR C-SPY Debugger

Simulator driver

Hardware system drivers

Power debugging

RTOS plug-ins

•Custom plug-ins - Editors, source code

control systems including

Subversion, etc.

•ARM EABI compliant

object code and CMSIS

included - Ability to link in object

code from other EABI

compliant tool chains

•Plug-in to Eclipse IDE - Compiler and build tools,

as well as a full integration

of the IAR C-SPY

Debugger.

•I-jet

•JTAGjet

•3rd party probes incl.

J-Link and P&E

•IAR visualSTATE

-State machine debug

integration

•Integrated RTOS

partners - Express Logic, CMX,

eForce, Freescale MQX,

FreeRTOS, Micrium,

Micro Digital, Sciopta,

SEGGER, Quadros,

Wittenstein

“The powerful optimizations provided by IAR Embedded Workbench

deliver outstanding performance for a Kinetis microcontroller,” says

Geoff Lees, senior vice president and general manager of Freescale’s

MCU business group. Press Release, Uppsala, Sweden—January 29, 2013

TM

External Use 35

Freescale MQX-Lite

TM

External Use 36

MQX Lite – Overview

• Very light MQX kernel for resource-limited MCUs

− Targeted at the Kinetis L series MCU family initially

− Packaged as a Processor Expert component

• I/O capability provided by Processor Expert

− USB via FSL bare-metal stack, also a Processor Expert component

− No POSIX-like drivers or file access

• Programming model allows upward code migration

− It is a true subset of the full MQX RTOS

− Code built with MQX Lite will move to full MQX RTOS easily

TM

External Use 37

MQX Lite – Main Features

• Scheduler

− Priority pre-emptive schedule

− Support for lightweight semaphore, and mutex (with polling)

• Task management does not support dynamic task creation

− All task resources allocated at compile time

− Dynamic memory management not allowed

No Task Termination

No Round Robin

• Lightweight events and messaging only

• Lightweight timer included (one shot, and periodic notification)

TM

External Use 38

MQX Subsystems Removed in MQX Lite RTOS

TM

External Use 39

Configuring a Task

• Tasks are separate components

contained within the RTOS component

• Configure in the component inspector

− Set name of task function

− Priority

− Stack size

− All the parameters of an MQX task

template list

TM

External Use 40

How Small Is MQX Lite?

• Minimal App – Hello Task, Idle task, interrupt stack

− Code = 10.4K

− Data = 3.7K (including 1.5K for stacks)

• Typical App – 7 tasks + idle, lightweight events, queues

− Code = 27K

− Data = 10K (5K for stacks)

TM

External Use 41

MQX Lite and Processor Expert Integration

• MQX Lite is an RTOS adapter

− Interrupt mechanism in MQX is

unchanged

− Processor Expert LDDs work with the

RTOS

− Tasks are defined within PEx prior to

code generation

− MQX-Lite Services enabled within PEx

− Interrupts managed through PEx with

implementation in Events.c

TM

External Use 42

Summary

TM

External Use 43

Kinetis L Series MCUs:

Enabling Differentiation in Entry-Level Products

Energy-efficiency

Class-leading

Coremark/mW

Scalability &

Integration

Kinetis L to K Series

(Cortex M0+ to M4)

Enablement

Freescale bundle +

ARM ecosystem

Ultra Low Static

<1uA

Low cost

From <$0.50

Ease-of-use

Freedom Platform,

Processor Expert &

MCU Solution Advisor Kinetis L Series MCUs

The evolution of the entry-level MCU

32-bit 8-bit

TM

External Use 44

Onto the labs…

TM

© 2014 Freescale Semiconductor, Inc. | External Use

www.Freescale.com