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High Frequency Integrated DC/DC ConverterDigital Control
Andreia MendesInstituto Superior Tecnico
Abstract—This work focuses on the power managementof electronic circuits that operate with low load currents, inthe range of a few hundred mA, with voltage regulated by aDC/DC converter since efficiency requirements don’t allow toconsider the application of a linear regulator. Therefore, theuse of a buck converter, whose efficiency doesn’t decreasesignificantly with the decrease of the load current, wasstudied, as well as the use of high frequency in order toallow the reduction of buck’s filter elements.
After the DC/DC step down converter design was com-pleted, the power stage modular approach was studied. Thesolution consisted on including in each module a portionof the power transistors and their respective drivers, dy-namically enabling just the number of necessary modules,depending on the load current applied, so that the referencevoltage was reached. By doing this, the conduction andswitching losses are optimized as the load current decreasesand, the efficiency of the converter is maintained approxi-mately constant.
Index Terms—Buck Converter, CMOS, High FrequencyDC/DC, Modular Project
I. INTRODUCTION
Recently the use of portable devices, with many dif-ferent features and purposes, has increased substantially.In particular, we have seen a mass use of mobile phones,laptops and more recently of tablet devices. However, allof these devices have one thing in common, they requireboth autonomy and portability. And, although the size ofthe equipments have been reduced, the number of differentapplications that they have to perform has increased.
All these functionalities and applications involve a risein their energy consumption and a corresponding demandfor increasing their battery capacity, but it is intendedthat they remain portable and with high autonomy. So,we can say that portable device battery capacities hasn’tkept pace with their power consumption. To that end,since the size of the equipment and, consequently itsbattery has been decreasing, it is necessary that they havea high efficient power management. For this reason, thepower management circuits are critical blocks in portableequipment. These aim to reduce power consumption andimprove the efficiency of equipment taking into accounttheir different types of possible uses (for example, per-forming communications or being on standby). This, inaddition to increasing the battery life will also improvethe system performance.
The purpose of using high switching frequency in thiswork is to allow buck’s filter elements to be smaller andreach their full integration into System on Chip (SoC),or partially in a System in Package (SiP). However, theincreased frequency results in a raise of the switching
losses associated with the converter and, as such, canstrongly penalize its performance.
The frequency used in this project, 20MHz, is thereforea compromise between the analysis of the effects thathigh frequency will arouse in converter’s efficiency andthe partial integration of its filter in a SiP (concerning itsinductive element).
Another key aspect in the project is the current rangeused in the output. What is intended with this study is toexplore the feasibility of a DC/DC converter operating ina current range of a few hundred mA. That range is lowfor a DC/DC converter point of view but, sufficiently highto make unfeasible the use of a linear regulator (due to itslow efficiency). It should be taken into account that theefficiency of a linear regulator will be given by the ratiobetween its output and input voltages [1]. Consequently,in this case, we would have an efficiency of approximately30%.
Linear regulators are a simple alternative in order toobtain a regulated output voltage lower than the inputvoltage. However, they are always associated with a sig-nificant power dissipation and that is the main reason whythey are primarily used in applications that require lowoutput current (where the absolute value of the energyassociated with these losses is not critical). Nevertheless,with the increasing of load current, not only the powerlosses increase as well, as there’s a greater difficultyin dissipating the heat associated with such losses. Assuch, the DC/DC converters have been the primary choicewhen dealing with applications that require higher outputcurrent, due to its better efficiency (over 90%) and lowerpower dissipation [1].
However, the DC/DC converters have the disadvantage,compared to linear regulators, of requiring an externalfilter that can be minimized by increasing the switchingfrequency. Yet, when considering the use of a higherfrequency than the usual 1−5MHz in a DC/DC converter,one should pay special attention to their switching losses.These are increasingly significant and penalty in terms ofthe efficiency obtained, as lower the converter’s operatingfrequency is.
Thus, the output current to consider can be said tobe reduced when considering an application of a DC/DCconverter, where it will have a lower efficiency (comparedwith the efficiencies reached when operating at lowerfrequencies but with a bulkier filter), although it is highfrom the point of view of the application of a linearregulator. Nonetheless, even a lower efficiency (around80%) for a DC/DC converter remains higher than that
obtained by using a linear regulator (which would be 30%)
The organization of this paper is as follows.In section II the concept of the control method proposed
is introduced.The aim of section III is to detail the steps taken on
the initial design of the DC/DC converter. This primarilydesign will be used as a starting point towards the modu-larization of converter’s power stage.
On section IV is studied how to modularize the con-verter’s power stage. It contains the several steps thatallowed to define the power stage unitary modules, aswell as the analysis of the results obtained after theimplementation.
For last, section V presents the overall conclusionsabout the work made and the future steps that could bedone towards a final prototype.
II. PROPOSED CONTROL METHOD
As previous mentioned, the use of higher switchingfrequency will lead to an increase in the energy losses as-sociated with the switching of the transistors, making thesethe most relevant, compared to the transistor’s conductionlosses. Since it is intended that the switching losses are asminimal as possible, it is usual to consider more than onemode of operation for the converters. Usually the workloadin mobile equipments is variable over time, alternatingbetween long periods of inactivity (standby) and short timeintensive tasks. So the ideal is to have a different treatmentto each of the operating modes of the devices.
Typically, we can approach an ideal switched converter(i.e. get a high efficiency regardless of the load conditions)when using a hybrid mode, usually composed by PulseWidth Modulation (PWM) and Pulse Frequency Modula-tion (PFM). The mode of operation will thus be chosenaccording to the load conditions [2] [3] [4]. For a lowenergy mode, such as sleep, standby or power saving,the usual modulation considered is PFM. In cases wherethere’s an heavy load, is then frequently used PWM.Thereby providing an alternating way between a lowerswitching frequency with PFM and a higher switchingfrequency when changing to PWM.
The buck converter proposed in [5] uses a hybrid mode,using PWM for heavy loads and Switch-On-DemandModulation (SODM) when the converter’s load is lower.This SODM control method proposed in [5], consists inskipping cycles in which the converter should be on itson-state, thereby decreasing the switching frequency. Thiswill, according to the authors, allow the converter to passfrom its Discontinuous Conduction Mode (DCM) to theContinuous Conduction Mode (CCM) in a smooth andautomatic way, as the load current increases.
However, this work [5], was also used a techniqueof Switch Size Control (SSC), which consists in thechanging of the power transistors size according to theconditions prevailing in the converter’s load. Thus, theauthors divided the power stage into four segments, whereonly one of it is used when the converter has a low loadcurrent.
Thus, SSC technique used in [5] was the influence forthe control method developed in this work. Taking into
account the concept of dividing the power stage, but usingthe number of the connected segments as a control method(not only to decrease the power associated with the powertransistors and their drivers as in [5])
The control method implemented requires the modula-rization of the power stage, insofar as it consists of severalmodules containing a specific number of power transistorsand their drivers. This additional modules are added to thepower stage when the output voltage of the converter islower than the reference voltage and, otherwise removedas the output voltage decreases.
The number of modules present in the power stage willbe the only mean used for correcting the voltage at theconverter’s output, as its duty cycle is fixed. By settingthe time in which the converter is in its on-state, it is notnecessary to have a pulse modulation, as in PWM, whichimplies a significant current consumption.
The control method developed to set how the constituentmodules of the power stage are connected or disconnected,is done in a simple digital manner, based on the digitalword originated from the comparison between the outputvoltage sampled and the reference voltage.
The fact that the power stage is modular and its controldone digitally, allow it to be adapted or changed inthe future, depending on the needs or requirements thatmay be later identified. This adaptability is one of theadvantages of using digital control methods.
III. POWER STAGE PROJECT
A. Converter’s Components
The specifications for the buck converter set the fre-quency at 20MHz and the capacitor of its filter to be1µF . It was also specified that the typical value of theinput voltage was 3.3V and the reference voltage shouldbe 1V .
So, the duty cycle of the converter, in its CCM, isapproximately 0.3. Considering a voltage drop in theinductor of 2V and its current amplitude to be 300mA,the inductor was deduced to have 100nH .
B. Power Transistors Drivers
One of the key aspects on buck’s operation is theswitching of its power transistors. So, in order to enablethe converter to switch between its on-state and off-state,it is necessary that the power transistors are turned on oroff, according to the intended operating state.
Preventing the appearance of a shoot-through current,it was necessary to control both power transistors inter-calating their conduction with a non-overlap time. Thiswas implemented by placing a driver (that consisted ininverters) for each power transistor, which only allows itto be connected after the cutting off of the other transistor.
C. Converter Active Elements Sizing and Proportions
In choosing the size of transistors, it is necessary toconsider the compromise between their conduction lossesand the ones related with their switching.
Thus, by increasing power transistors channel width itis possible to decrease the resistance of their channel andminimize their conduction losses. However, increasing thetransistor width will also result in a raise of the parasitic
capacity associated with their terminals, including its gate,and so the switching losses are increased too.
Then, the dimensions of the power transistors need tobe varied in order to find the optimal solution leading toa higher efficiency. Also, taking into account the currentthat will flow through the power transistors, these willhave dimensions that prevent them of being composed bya single cell. As such, they have been implemented usingarrays of smaller transistors with 10 fingers and a widthof 30µm.
However, unlike what happens with the length (L),which will vary depending on the considered transistor(pMOS or nMOS, of power transistors or their drivers), thewidth (W) of the base transistor will always be constant.
The proportions used on the sizing of the transistors andtheir drivers were:(
W
L
)pMOS
= 3
(W
L
)nMOS(
W
L
)PwrTrans.
= 20
(W
L
)Driver
(1)
D. Driver’s Transistors Lenght (L)
The drivers transmit the control signal that will turn on,or off, the respective power transistor. The ideal wouldbe to have an instantaneous transition between the on andoff signal. As such, it is desired for driver’s transistors tobe as fast as possible so that the transition of their signalcould be closer to the ideal case.
Faster switching implies that the transistor has to havemore current flow between its terminals. So, that involvesdecreasing the transistor’s length, enhancing its speed.
As in the technology used the minimum length forpMOS and nMOS transistors is 300nm and 340nm,respectively, these were the lengths used for the driver’stransistors.
E. Power Transistors Lenght (L)
In order to analyze what will be the appropriate lengthfor the power transistors, it will be necessary to assignthem a width nearby the one they will have at the end oftheir sizing.
After their estimated sizing were then determined theirassociated leakage currents according to the differentlengths considered.
Estimated transistor’s width: To be able to vary thelength of the power transistors and determine its optimalvalue, it is initially necessary to provide a realistic widthof the power transistors.
So, it was decided to assign a length of 600nm to thepower transistors, consider an output current of 250mAand adjusting the duty cycle as necessary to maintainan output voltage of 1V . The iterations were made bychanging the number of the base transistors present inthe power transistor nMOS, being the other parameters(number of base transistors in the power transistor pMOSand the number of the transistors in the drivers) calculatedaccording to the proportions defined.
Based on the efficiencies obtained, the best conditionwas achieved with 260 power transistors nMOS, corre-sponding to an efficiency of 81.62%.
Power Transistor’s Leakage Current: With the approx-imate size of the power transistors defined, the leakagecurrents associated with the power transistors were simu-lated, according to their possible different lengths.
The length has been modified from the lowest valuepossible (300nm for the pMOS and 340nm for the nMOS)up to the 600nm, which had been used initially forestimating the size of the power transistors. To betterobserve the leakage current effects, the temperature of thesimulations was set to 125◦C.
In evaluating the results obtained it is necessary to takeinto account that the increasing of the channel lengthtranslates into lower losses due to leakage currents. Butalso results in increasing the gate capacitance, with higherswitching losses and, in a reduction of power transistorsswitching speed.
Thus, the analyses focused on the points at which anequal increase of the transistor’s length leaded to a furtherreduction in the leakage current. These being the pointswhere the leakage current curve had a higher slope.
The lengths that better suit this condition were thecombination of 340nm for the power transistor pMOSand, 380nm for the nMOS. But, despite considering thiscombination as a better compromise between the trade-offsidentified, other combinations were taken for comparison(in the next step for the evaluation of what should be thepower transistor’s length).
Effect of Power Transistor’s Length: After the identifi-cation of the leakage currents associated with the powertransistor’s different lengths, their impact was checked outchanging also the power transistor’s width. The outputcurrent specified for this simulation was approximately250mA and, the duty cycle adjusted so it could beachieved an output voltage of nearly 1V . In these sim-ulations, 12 different combinations were tested and thebest result achieved, taking in consideration the reductionof the leakage current, was composed by 698 pMOSpower transistors with a length of 340nm, 260 nMOSpower transistors with a length of 380nm (and, their driverimplemented by 31 pMOS and 12 nMOS), where theefficiency obtained was 86.65%.
This stage also allowed reducing the number of combi-nations that should be evaluated. Meaning that it shouldbe considered two different combinations (one of which isthat presented before) and the ones correspondent to theborder restraints (maximum and minimum lengths tested),in order to compare the results.
Selection of Power Transistor’s Length: To choosewhich final length should be assigned to the power transis-tors, was then done an analysis of the results obtained withthe four different combinations of lengths identified in theprevious step. But in this case, also changing the outputcurrent of the converter to: 200mA, 250mA, 300mA and,400mA.
The different efficiencies obtained allowed concludingthat the option with lengths 340nm (for pMOS) and
380nm (for nMOS) were the most regular and independentof the output current on the converter. Furthermore, inall the combinations simulated, the best efficiencies areobtained when the output current is close to 300mA,whose results could be seen in table I and figure 1.
TABLE IRESULTS OBTAINED WITH AN OUTPUT CURRENT OF 300mA, FOR
DIFFERENT COMBINATIONS OF POWER TRANSISTOR’S LENGTH.
Maximum Minimum Comb. P1 Comb. P2
780 688 698 67423.4 20.6 20.9 20.2260 260 260 2607.8 7.8 7.8 7.8600 300 340 380600 340 380 440600 300 340 380600 340 380 4400.29 3.56 1.71 1.031.54 2.55 2.13 1.80
Io [mA] 305.6 314.0 311.8 309.6Vo [V] 1.009 1.036 1.029 1.022η [%] 81.5 87.5 86.8 86.0≈
300
mA
L nMOS_Pwr [nm]
# pMOS_Drv# nMOS_Drv
iLeakP [uA] iLeakN [uA]
# pMOS_Pwr
W pMOS_Pwr [mm]
# nMOS_Pwr
W nMOS_Pwr [mm]
L pMOS_Pwr [nm]
86.8!
1.71!
2.13!
0.0!
0.5!
1.0!
1.5!
2.0!
2.5!
3.0!
3.5!
4.0!
79!
80!
81!
82!
83!
84!
85!
86!
87!
88!
Maximum ! Minimum! Comb. P1! Comb. P2!
!Po
wer
Tra
nsis
tors
Lea
kage
Cur
rent
[uA]!
Effic
ienc
y [%
]!!
Io->300mA! iLeak pMOS! iLeak nMOS!
Fig. 1. Comparison of results obtained with an output current of 300mA,for different combinations of power transistor’s length.
As it is possible to see in figure 1, while the efficiencyin ”Comb. P1” is slightly lower than the one obtained for”Minimum”, there is a significant decrease in the powertransistor’s leakage current. Being this the main reasonwhy the ”Comb. P1” was the one chosen for the powerstage initial sizing.
F. Power Stage Initial Design
The converter’s initial project included not only thedesign of its passive elements, but mostly its power stage.
In the case of power transistor’s drivers, the main featuretaken into account was their switching speed, which iswhy their active elements have been designed with theminimum length allowed by technology.
As regards the power transistors, compromises hadbeen made on its design between what would be theirconduction losses, those associated with its switching andtheir speed in state transitions.
After the study of several possible combinations for thepower transistor’s width and length, considering differentload currents, the design selected was the one that leadedto the best efficiency, balancing the different commitments
already indicated. In table II is described the configurationchosen and, the simulation results obtained.
TABLE IIRESULTS FOR THE POWER STAGE INTIAL SIZING.
# pMOS_Pot 698 Ton [ns] 15W pMOS_Pot [mm] 20.9 Iin [mA] 107L pMOS_Pot [nm] 340 Iin_ctr [mA] 5iLeakP [uA] 1.7 Io [mA] 312# nMOS_Pot 260 Vo [V] 1.029W nMOS_Pot [mm] 7.8 Pin [mW] 352L nMOS_Pot [nm] 380 Pin_ctr [mW] 18iLeakN [uA] 2.1 Po [mW] 321# pMOS_Drv 31 η [%] 86.8# nMOS_Drv 12
IV. MODULAR IMPLEMENTATIONOF THE DC/DC CONVERTER
A. Power Stage Modularization
After the power stage initial project it was studied thepossibility of its modularization. As it was perceptible, justby increasing or decreasing the number of basic transistorsin the power transistor’s arrays the output voltage obtainedvaried. However, in the power stage project the intentionwas to find the perfect design. So, besides changing thetransistor’s width and length, the duty cycle was also adjustto achieve the desired output voltage.
The goal in the power stage modularization is to setthe converter’s duty cycle and, achieve the desired outputvoltage by only dynamically setting the number of activepower transistors and their drivers.
The modular structure implemented is depicted in sim-plified form in figure 2.
Module 1Module 2
Module n
Power Stage
Fig. 2. Modular power stage representation.
As is present in the representation of the modular powerstage, the modules required for a particular converter’sconfiguration are connected in parallel. Thereby addingthe number of base transistors needed to each of its activeelements.
This modularization will involve compromises on thevariation levels of either output voltage and current, whenadding each module. Therefor, the less base transistorsof each active element that are present on each module,the greater will be the precision obtained on the outputvoltage. On the contrary, the more base transistors that arepresent in each module, the higher will be their impact onthe variation that they will produce in the output voltage.On the output current range achieved, the impact will besimilar. As there are more base transistors in each module,the reference voltage is obtained for less output currentvalues.
This granularity based on how many transistors mustbe present in each module has to be balanced due tothe identified commitments. The target is to increase themodularization of the power stage (which means to havethe most possible base transistors in each module) withoutlosing precision in both the output voltage obtained andthe current range supported.
In the following parts of this section are describedthe steps that were taken for the selection of granularity.Trying to increase the modularization of the power stagewithout prejudice its performance.
The contents of each module are shown in figure 3,also in simplified form. As can be seen, each module hasfour major components that contain a number of basictransistors corresponding to transistors: power PMOS,power nMOS, driver’s pMOS and driver’s nMOS.
Module
x Base Trans.
Pwr pMOS
y Base Trans.
Pwr nMOS
DriverpMOS
z Base Trans.pMOS Drv
w Base Trans.nMOS Drv
DrivernMOS
z Base Trans.pMOS Drv
w Base Trans.nMOS Drv
Fig. 3. Module representation.
B. Transistor’s Variation Analysis
As indicated before, there is a need to verify how manybase transistors could be allocated into a module, respect-ing the commitments already identified. After some initialsimulations, it was stipulated that it should be observedthe changes occurring when incrementing 20 nMOS basetransistors at each time. Since for a lower number, thechanges in the output voltage were too minimal, leadingto a very low granularity and, a numerous of modules inorder to allow the reference voltage to be reached.
For each level of output current (400mA, 300mA,200mA and, 180mA) was then tested the effect that thevariation indicated caused, both within the obtained outputvoltage and in the efficiency reached.
The starting point for the number of nMOS basetransistors to be used was 260, since it corresponds toinitial power stage project. The other transistors were thenadjusted according to the proportions that needed to berespected. For each different configuration tested was alsoobserved the variation that occurred in terms of the outputvoltage reached and the efficiency obtained. So, it waspossible to check how an addition of each these set ofbase transistor altered those parameters.
In terms of the output voltage variation was identifiedthat, as the output current decreases, it takes higher ab-solute values. For example, in conditions adjacent to the
condition chosen for 400mA, the variation in the outputvoltage was about 5mV . However, for the same situation,but applying 200mA or 180mA, the variation is alreadyapproaching 10mV .
When observing the efficiency variation, the condi-tions corresponding to an output voltage higher than thereference voltage, typically have lower absolute values,compared to the same conditions (same number of basetransistors nMOS varied) when the obtained voltage islower than the reference voltage.
The implemented granularity has proved to be a goodcompromise between the variation caused in the outputvoltage (in each output current level analyzed) and, thepossibility to achieve the desired reference voltage. Thus,associating to each module this number of base transistors,on converter’s the active elements, it is possible to achievethe desired output voltage. Estimating that the differencein the output voltage to increase, or decrease, a modulewill be approximately 5mV to 10mV .
In the table III, are presented the results for the con-figuration chosen in each output current level analyze(400mA, 300mA, 200mA and, 180mA). Also, are pre-sented the ”Minimum” configuration that corresponds tothe combination with the minimum base transistors withwhich the converter still operates in the CCM.
TABLE IIINUMBER OF BASE TRANSISTORS IN EACH CONVERTER’S ACTIVE
ELEMENT, FOR DIFERENT LEVELS OF OUTPUT CURRENTS.
400mA 300mA 200mA 180mA Minimum# pMOS_Pwr 966 752 483 429 322# nMOS_Pwr 360 280 180 160 120# pMOS_Drv 43 33 21 19 14# nMOS_Drv 16 13 8 7 5Vo [V] 1.000 1.005 1.004 1.004 0.985η [%] 86.1 86.3 86.6 86.4 85.0
Regarding the efficiency obtained, it should be notedthat between the maximum value obtained (86.3% for300mA) and its minimum (86.4% for 180mA) it justvaries 0.5%.
C. Unitary Module Proportions
The granularity estimated can be validated in the level ofthe output voltage variation achieved. However, it remainsto set how many base transistors should be assigned toeach module that will be a part of the modular powerstage.
The number of base transistors on the converter’s activeelements, were determined based on the most regularlyvariation that they suffer on the simulations done in theprevious part.
Thus, in table IV is indicated the design chosen for eachmodule, the unit component of the modular converter’sstructure.
However, when implementing the converter with thismodular structure, the number of base transistors that com-posed the converter’s active elements fail to fully respectthe proportions that were defined. This is a consequence,and a commitment, of modularize the power stage.
Another choice on this implementation was to separatethe modules into two different groups. The ”Base Mod-ules” which will always remain connected in the power
TABLE IVNUMBER OF BASE TRANSISTORS IN EACH MODULE.
# pMOS_Pwr 54# nMOS_Pwr 20# pMOS_Drv 2# nMOS_Drv 1
Module
stage and, that correspond to the minimum base transistorsestimated before to be necessary to maintain the converteron its CCM. And, the ”Additional Modules” that will beadded only when needed to reach the reference voltage.
D. Proposed Control
The implemented control aims to turn on, or off, thenumber of necessary ”Additional Modules” according tothe converter’s output voltage. When the output voltage islower than the reference voltage, it is necessary to connect”Additional Modules” until it is achieved. On the contrary,when the inverter output voltage exceeds the referencevoltage there are ”Additional modules” that need to bedisconnected.
In order to know if the output voltage is higher, orlower, than the reference voltage, it is necessary to usean Analog-to-Digital Converter (ADC). The ADC allowsto translate the analog output voltage to a digital wordrepresentative of its value. Since the implementation ofthe ADC is already outside the scope of this work, certaincharacteristics were assumed only from a conceptual pointof view, adjusted to the modularization of the power stageand not for an ADC in particular. Since it is intended tocontrol 12 ”Additional modules”, it was assumed that itwould be used an ADC with 24 bits, whose digital wordencoding is performed in thermometer code.
The digital word Sel < 0 : 23 > in thermometer codeprovided from the sampling and comparison done by theADC is then used by the control in order to turn on, or off,the number of ”Additional Modules” necessary. However,it was necessary to divide it into two other distinct arrays:bitH<1:12> and bitL<1:12>.
Module 1
Sel23 Sel22 (...) Sel14 Sel13 Sel12 Sel11 Sel10 Sel9 (...) Sel1 Sel0
bitL12 bitL11 (...) bitL3 bitL2 bitL1 bitH1 bitH2 bitH3 (...) bitH11 bitH12
Module 12
Fig. 4. Correspondence representation of the digital word and the”Aditional Modules”.
As it is represented in figure 4, the bits bitHx andbitLx allow controlling one ”Module x”. Thus, it is thecombination of these two bits which decides whether amodule should be turned on or off.
Before describing how the module’s control was imple-mented, using the arrays bitH < 1 : 12 > and bitL < 1 :12>, it is necessary to observe their correspondence withthe digital word (in thermometer code) obtained from theADC.
• [VO = Vref ] That means that bitL < 1 : 12 >= 1and bitH < 1 : 12 >= 0 once the reference voltagehas been reached. So it is intended that the modulesremain in the state they were in before. Therefore, thecombination of modules (connected or disconnected)which allowed reaching the reference voltage shouldremain unchanged.
• [VO < Vref ] In this case bitH < 1 : 12 >= 0 butnot all bits in the bitLx array are unitary. So, thereference voltage was not reached and the moduleswhich have bitLx = 0 need to be connected.
• [VO > Vref ] This situation is dual of the previousone. In this case bitL < 1 : 12>= 1 but not all thebitHx array is null. So, the output voltage is higherthan the reference voltage and the modules whichhave bitHx = 1 need to be disconnected.
With the three possible scenarios described and iden-tified their correspondence with the arrays bitHx andbitLx, it is showed on table V how the modules shouldbe controlled.
TABLE VANALYSIS OF ACTIONS TO TAKE FOR EACH COMBINATION bitHx
AND bitLx.
bitLx bitHx
0 0
0 1
1 0
1 1
Impossible
Enable Module x
Actions
Disable Module x
Hold
As it is perceptible by the condition where is necessaryto maintain the previous module state, the control methodhas to have memory. This way the module’s state assignedin a previous assessment of the output voltage sampledcan be maintained if necessary. To implement the control’smemory it was used a NAND latch.
In a state where is intended to increment a specificmodule, it corresponds to a latch set. Otherwise, whena module needs to be removed, that is accomplished bydoing a reset in the latch. However, the latch will be onhold either when it is intended to maintain the previousstate attributed to a module and, in the impossible caseto occur (given the representation of the digital word inthermometer code).
Regarding the control signals that should be given to thepower transistors, it is necessary to identify the situationswhere they should be enable.
In the case of the pMOS power transistor, it should onlybe active when the latch is on set state (identifying thata particular module should be connected) and when theconverter is in its on-state (that corresponds to the clock’sraising edge).
For the nMOS power transistor, it is also intended tobe switched on only when the latch is in set state, butsimultaneously with the falling edge of the clock, whichcorresponds to the converter’s off-mode.
After identifying when the power transistors may, ormay not, be connected, it is also necessary to ensure that
it will not occur an overlap on their conduction.Thus, it is intended that a power transistor only be
turned on after the other one is already turned off. Other-wise, there will be some periods in which both powertransistors would be simultaneously conducting in theseswitching stages (between the converter’s on-state and off-state).
The implemented control may be considered to bedivided into three different parts, being these representedin figure 5.
States Impulses Non-Overlap
Fig. 5. Control circuit representation.
The first part ”States” corresponds to the analysis of thearrays bitHx and bitLx and, the respective evaluation ofwhich state should be attributed to a ”Module x” (enableit, desable it or hold its previous state).
The second part ”Impulses” is where the control signalsfor the power transistor’s gates are defined.
And the last one ”Non-Overlap” guaranties that thecontrol signals will not cause any simultaneous conductionof the power transistors.
E. Effects of Including Control
After the unit module proportions are set and eachmodule’s control defined, it is necessary to check theimpact of control’ insertion on the converter’s efficiency.
As expected, the power associated with the converter’scontrol elements increased slightly, from about 1.6mWa 1.8mW . However, it was also observed that either thevoltage and the current on the converter’s output decreasedslightly, when the control proceeded to dictate the signalsfor the power transistor’s gates.
Regarding the efficiency obtained there is also a re-duction, but it doesn’t exceed 0.7%. Being even lesssignificant (only 0.1%) in the best case identified, i.e. fora current of approximately 300mA.
Due to the reductions in the voltage and current at theconverter’s output, it was decided to adjust the number ofbase modules present in the power stage.
Thus, the number of base modules was increased to7 and then observed the consequences that such increasecould imply in the number of additional modules used foreach output current level.
The results obtained allowed concluding that regardingthe output current the raise was minimum but, as far as theoutput voltage the value obtained is near to the referencevalue, as it was intended. Thus, it was also confirmed thatthere was no need to adjust the additional modules, foreach output current level, after the inclusion of one morebase module (this adjustment was sufficient to guaranteethat the reference voltage was achieved).
The results achieved after the control inclusion and, theadjustment of the base modules, are present in table VI
TABLE VIRESULTS OBTAINED AFTER CONTROL INCLUSION AND ADJUSTING
THE NUMBER OF BASE MODULES.
2 Modules 3 Modules 8 Modules 12 ModulesIin [mA] 59.2 66.0 100.1 138.0Iin_ctr [mA] 4.0 4.3 6.3 7.9Io [mA] 179 200 304 416Vo [V] 1.001 1.000 1.003 0.999Pin [mW] 195.2 217.8 330.3 455.5Pin_ctr [mW] 13.1 14.3 20.8 26.0Po [mW] 179.0 200.1 304.7 416.2η [%] 85.9 86.2 86.8 86.4
7 base modules
As the output voltage of this configuration (with 7base modules) is more close to the reference voltage thatit’s aimed to achieve in the converter’s output, withoutcompromising either the efficiency obtained or the outputcurrent levels achieved, this was the configuration chosenfor the power stage’s modular implementation.
F. Converter Analysis
Steady State Waveforms: Analyzing the converter’soutput current and voltage waveforms when the steadystate is reached, their amplitude were: ∆VO ' 2.24mV ,∆IO ' 0.68mA and, ∆IL ' 358mA.
So, the output voltage and current were consideredconstant when reached the steady state. Observing thevariation indicated, against the end value for which theystabilize, this approximation can be considered valid be-cause: ∆VO
VO' 0.22% and ∆IO
IO' 0.23%.
In both cases the variation is quite less than 1%, thenboth parameters can be considered continuous.
Fixed Output Current: Rather than check the efficiencyobtained for a certain fixed output current, it is intended toexamine the converter’s behavior to a change in its outputcurrent. Thus, it was used in the converter’s output anideal current source with two different current levels andobserved how the control corrected the output voltage tocompensate it and achieve the desired reference voltage.
Transient Response
0 5.0 1 0 1 5 2 0time (us)
3.02.52.01.51.0
.50
−.5
−1.0
I (A)
I (A)
5 00
400
300
200
100
0
−100
I (m
A)I (
mA)
1 .5
1.25
1.0
.75
.5
.25
0
−.25
V (V
)V
(V)
3 25
300
275
250
225
200
175
I (m
A)I (
mA)
/iIn/PLUS
/iCtr/PLUS
Vo
Io
time (us)
User: amendes Date: Sep 30, 2015 1:39:55 PM WEST DCDC_sim_am DCDC_PWRdv OpenLoop_12b : Sep 30 12:12:40 2015 25
Fig. 6. Output voltage and current waveforms when reached the steadystate.
In figure 6 it is possible to see the waveforms ofthe voltage and current at the converter’s output. Thistransition corresponds to a simulation of 20us where at10us the current output was changed from 200mA to300mA.
In the output voltage plot is signaled the reference volt-age to achieve (1V ). After the change in the output current(at 10us) it is possible to observe a slight oscillation,where the output voltage has decreased due to the raise
of the output current. That was promptly compensated byadding more 5 additional modules.
Fixed Output Voltage: Fixing the converter’s outputvoltage at the reference value will allow assessing the out-put current achieved when adding each additional module.
Thus, keeping the 7 base modules active and an idealvoltage source of 1V at the converter’s output, wereincluded additional modules one by one. The results foreach of these 13 conditions, from 0 to 12 additionalmodules, are present on a graphic presented in figure 7.
147!166!
185!205!
225!247!
268!290!
312!333!
355!377!
399!
84.36! 84.33! 84.26! 84.19! 84.20! 84.24! 84.28! 84.31! 84.32! 84.35! 84.36! 84.36! 84.39!
80.0!80.5!81.0!81.5!82.0!82.5!83.0!83.5!84.0!84.5!85.0!
100!
150!
200!
250!
300!
350!
400!
450!
0! 1! 2! 3! 4! 5! 6! 7! 8! 9! 10! 11! 12!
Effic
ienc
y [%
]!
Out
put C
urre
nt [m
A]!
Number of Active Modules (besides the Base Modules)!
Io [mA]! η [%]!
Fig. 7. Efficiency and output current obtained by adding each additionalmodule to the modular power stage, with a fixed output voltage.
Regarding the variation in the output current causedby adding each additional module, it is possible to verifythat its value is increasing as more additional modules areadded. However, this variation is located between 19mAand 22mA, representing an increase of approximately13.6% between the variation obtained initially (with theaddition of the first modules) and the variation obtainedwith the insertion of the last modules.
As can be seen the increase of the current is approxi-mately linear, which would be expected since the variationof the output current increases slightly, as the number ofconnected modules are also raised.
As to the efficiency obtained, it remains approximatelyconstant, considering that between the maximum andminimum values reached there is only a difference of0.19%
V. CONCLUSIONS AND FUTURE WORK
The main goal in the modular implementation of thepower stage is to use only the required number of tran-sistors in each active element of the converter (powertransistors and their drivers). Minimizing the number oftransistors present in each active element, reduces conduc-tion and switching losses as the conditions on converterload are changed; because they are optimized for eachcircumstance and not fixed regardless of the requirementsthat are imposed on its load.
With this approach it was possible to maintain anapproximately constant output with a variation of only0.19%, for a load current from 185mA to 399mA. Suchbehaviour runs counter to the downward trend of theconverter’s efficiency as its output current is decreased.
The best efficiency obtained was 86.8%, for an outputcurrent of 304mA. Although this is lower than the typi-cally efficiency obtained for converters that operate with
higher load currents (up to 90%), it is still much higherthan what could be achieved by using a linear regulator(about 30%).
The modular implementation also allows to proposea method for controlling the output voltage by partialactivate the power stage. Preliminary results show that fora significant current range, it is possible to maintain theduty cycle and make the output voltage regulation onlyby changing the number of active elements in the powerstage.
Regarding the ripple of the output voltage, the valueobtained was 2.3mV , much lower than what was specified(30mV ). More specifically, the ripple obtained comparedto the output voltage value reached was about 0.2%. So itcan be considered that the output voltage is regulated andconstant.
The next challenge in the design is clearly the integra-tion of a ADC that can provide a digital word to the controland test the solution in a closed loop. The ADC shouldhave 24 levels, so that each additional module has 2 bitsof the digital word associated to them.
Afterwords, solutions that enable a full integration ofconverter’s filter elements in a SiP should be studied, sothat a prototype could be manufactured.
REFERENCES
[1] H. J. Zhang, “Basic concepts of linear regulator and switching modepower supplies.” Linear Technology Application Note 140, October2013.
[2] W.-R. Liou, M.-L. Yeh, and Y. L. Kuo, “A high efficiency dual-modebuck converter IC for portable applications,” IEEE Transactions onPower Electronics, vol. 23, no. 2, pp. 667–677, Mar 2008.
[3] J.-C. Tsai, T.-Y. Huang, W.-W. Lai, and K.-H. Chen, “Dual modula-tion technique for high efficiency in high-switching buck convertersover a wide load range,” IEEE Transactions on Circuits and SystemsI: Regular Papers, vol. 58, no. 7, pp. 1671–1680, Jul 2011.
[4] L.-F. Shi and W.-G. Jia, “Mode-selectable high-efficiency low-quiescent-current synchronous buck dc-dc converter,” IEEE Transac-tions on Industrial Electronics, vol. 61, no. 5, pp. 2278–2285, May2014.
[5] B. Yuan, X.-Q. Lai, H.-Y. Wang, and L.-F. Shi, “High-efficient hybridbuck converter with switch-on-demand modulation and switch sizecontrol for wide-load low-ripple applications,” IEEE Transactions onMicrowave Theory and Techniques, vol. 61, no. 9, pp. 3329–3338,Sep 2013.
