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Tunable and Programmable Filter Array

Design Project ECE 262 Spring 2012

Rahil Jain Rajat Chadha

Department of Electrical and Computer Engineering, Duke University, Durham NC

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1. Introduction Active analog filters are widely used for audio filtering and conditioning, frequency and amplitude modulation and various signal processing applications. Most common active filter circuit configurations are Sallen and key, Butterworth and Chebyshew. Common transfer functions are: ● High-pass filter – attenuation of frequencies below their cut-off frequencies. ● Low-pass filter – attenuation of frequencies above their cut-off frequencies. ● Band-pass filter – attenuation of frequencies both above and below those they allow to

pass. ● Notch filter – attenuation of certain frequencies while allowing all others to pass.

The cutoff frequencies of these filters are mostly fixed and depends on RC network used to design the filter. Fixed cutoff frequency filters post hindrance in designing circuits that have dynamic inputs. The solution commonly used uses array of filters with different cutoff frequencies and a the required filter is chosen using a digital logic. We realized that to make a filter versatile, it is imperative that its cutoff frequency can be tuned, which became the core idea of this project. The idea of providing freedom to the user was further extended by allowing the user to choose a filter depending upon the application. Adding to the convenience of choosing the cutoff frequency of the filter from a given range, the user can also programmable select which filter to apply this cutoff to. This novel idea provides a high degree of flexibility to the end user. Switched capacitor networks are often used to provide tunability to RC networks. The idea was to replace the resistance in RC networks of active filters by an array of MOS transistors and capacitors. Switching the MOS transistors in a periodic fashion controls the charging and discharging of the capacitor, thus simulating a resistive network. This approach is promising as it provides a variable resistance by modulating the switching speeds of the MOS transistors. Additionally, this approach removes resistive networks from the circuit, making it more compatible to CMOS design methodologies. Since resistors are the most power and area consuming devices on-chip, considerable savings of real estate and power can be done by using switched capacitors networks. To provide selectability of filter, a complex digital logic needs to be used. Depending on the nature of application, the user can select the appropriate filter using the control lines (S) while tuning the cutoff frequency using the clock input lines (Phi1 and Phi2). Depending on user’s input, appropriate filtering will be performed and a valid output will be available on the corresponding output line. In our initial proposal, we had aimed to include low pass, high pass, band pass and notch filters based on Sallenkey configuration in the filter array. Although the final design includes only high pass and low pass filters, we are able to demonstrate the novel idea. We acknowledge that to grant complete flexibility it entails a single output pin should be provided. Given the time requirements of this project, we planned to design individual output

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lines for each filter. In this design, the user will have to poll for the valid output on the selected filter output pin. This work can be extended by providing a output filtering and conditioning unit that will take the valid output from the selected filter and provide it to the user. The block diagram of the design is depicted below and shows the building blocks of the design. Individual blocks are explained in more detail, along with schematic and layouts in the following section.

Figure 1: High level block diagram for tunable and programmable filter array 2. Module Desciption 2.1. Digital Unit The digital circuit provides the selectibility to the circuit. It allows the user to choose either the high pass or the low pass filter from the array. It consists of the following components: ● Single inverter unit ● Inverting Unit ● NAND Unit

Single Inverter Unit: The inverter unit inverts a signal ‘s’ to ‘sbar’. s is an input pin, it gives the selectibility to the filter array. If s is high, High pass filter gets selected and the low pass filter is fed with a null value. Inverting Unit: The inverting unit consistes of for CMOS inverters, which are fed with four different clock frequency signals, namely: ● sphi2lpf

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● sphi1lpf ● sphi2hpf ● sphi1hpf

The inverting unit facilitates the switch capacitor unit with transmission gate configuratin ,this provides better noise immunity to the circuit. The schematic of the inverting unit is as follows:

Figure 2: Schematic of inverting unit Note that the W/L of all the nmos transistors, as obtained by hspice simulation, were 3.7 and that of pmos transistors was double, i.e., 7.4 (this compensates for the low mobility of the pmos devices) NAND Unit: ● The NAND unit consists of four two-input NAND gates which are connected to whose

input and output pot names are as follows: s and phi1 => sphi2lpf s and phi2 => sphi1lpf s’ and phi1 => sphi2hpf

s’ and phi2 => sphi1hpf This unit provides two non-overlapping clock frequencies to the low-pass and the high-pass filters.

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Figure 3: NAND unit The NAND gate in turn has a 10 finger nmos with W/L =3, a nmos with W/L=2, and two pmos devices with W/L=1

Figure 4: Two input NAND gate unit

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Figure 5: NAND gate layout There was a choice between using NAND array or AND array circuitry to provide selectability to the design. NAND gate array was chosen as it uses less number of transistors, hence a faster response, also when NAND array was simulated using hspice it was seen that the input signal at the unselected filter was a sinusoidal wave with amplitude of a few nano volts. On the other hand, simulating the AND gate array showed that a dc component would be at the input of the unselected filter of the order of micro volts. The layout of the integrated digital unit is given below. It consists of all the components described above.

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Figure 6: NAND gate based selector circuit layout

2.2. Analog Unit The analog unit is designed to provide the filtering operation. Two analog filters, low pass and high pass filter are the two major components of this unit. Based on the user provided select input (S), the digital logic supplies the clock (phi1 and phi2) to the corresponding switched capacitor network. The switched capacitor network of the unselected filter provides a high impedence stage to the filter, thus negating any filtering operation. Care was taken to determine appropriate transistor dimensions to drive the switch capacitor and filter units. The analog filters

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can further be decomposed into two block, a low output impedence, high bandwidth, high linearity, low gain error unity gain amplifier (UGA) and the corresponding switched capacitor network. The UGA design was inspired from the work of Palmisano et. al (IEEE Trans on Circuits and Systems 1998) and customized to our application. An additional buffering unit was added at the input of this design to improve the drivability by the switched capacitor network. 2.2.1. Unity Gain Amplifier The requirement of a unity gain amplifier that provides low output impedence for high fanout, high bandwidth for operation in wideband applications, high linearity, low gain error for improved performance was fulfilled by the design depicted below. Along with these restrictions, the design should be compatible to CMOS process. Hspice simulation for transistor dimensions revealed highly varied widths for PMOS and NMOS. A engineered layout was planned and executed keeping in mind that the UGA needs to be integrated with switched capacitor network in following stage. The schematic of the UGA and hspice simulation results are shown below. A unity gain for a bandwidth of 10 MHz was observed. The phase margin, although low, can be compensated by increasing the load capacitances. Provision of adding load capacitances on bonding pads were also explored and executed in the final layout of the design.

Figure 7: Schematic for Unity Gain Amplifier

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Figure 8: Frequency response by AC analysis of the UGA

Figure 9: Layout of the Unity Gain Amplifier

2.2.2 Switched Capacitor Network A switched capacitor based circuit was employed to incorporate tunability to each of the filters in the design. It consists of four nmos-pmos transistor pairs (transmission gates) which adds to the noise immunity in the circuit. Each of the four switch capacitor transmission gates run on two complementary clock frequencies provided by the inverting unit. It can be seen again that the W/L ratio of pmos devices are kept twice as that of the nmos devices. Also, the capacitor is not

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included in the schematic as common centroiding of all the capacitors is necessary to ensure minimum effect of process variation during fabrication of the circuit.

Figure 10: Switched Capacitor circuit layout

Figure 11: Schematic for Switched Capacitor Unit 2.2.3 Low Pass Filter The low pass filter consists of the switched capacitor network to provide variable resistance, a capacitor for the filter circuit and a unity gain amplifier (UGA). The filter capacitor was 10pf. The schematic and the layout of the low pass filter are as follows:

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Figure 12: Schematic of Low Pass Filter

Figure 13: Layout for the LPF with switched Capacitor 2.2.4 High Pass Filter The high pass filter consists of the switched capacitor network to provide variable resistance, a capacitor for the filter circuit and a unity gain amplifier (UGA). The filter capacitor was 10pf. The schematic and the layout of the high pass filter are as follows:

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Figure 14: Schematic for High Pass filter

Figure 15: Layout of high pass filter with Switch Capacitor 3. Integrated System Design All the components discussed above were finally integrated to build the tunable and programmable analog filter array and the DRC and LVS tests gave a positive result (smiley face). The schematic and the layout of the full system is as follows:

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Figure 16: Schematic of the Integrated Design

Figure 17: Layout of LVS clean switch Capacitor

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4. Results System simulations were performed using MOSIS supplied transistor models in Hspice. A varying select input was provided to change the filter. Also filter tuning was demonstarted by changing the clock frequencies (Phi1 and Phi2). 4.1. High Pass Filter Selection

If the Select unit is kept low, high pass filter is functional. No clock is coupled to low pass filter switched capacitor, thus blocking filtering. In case of high frequency input (> Cutoff frequency, based on Phi1 and Phi2), the output waveform resembles the input. In case of low frequency input (<< Cutoff frequency), the ouput waveform is fairly diminshed as depicted in following figures. 4.2. Low Pass Filter Selection By making the Select line high, low pass filtering can be selected. Frequencies lower than cutoff are allowed to pass without attenuation, while the frequencies above cutoff are not passed as shown in following figure. 4.3. Cutoff frequency tuning Cutoff frquency can be varied by changing the clock frequencies (Phi1 and Phi2). Increasing the clock frequency increases the cutoff frequency and vice-

Figure 18: High Pass filter response for high frequency and low frequency input. Low pass filter response to high frequency input

Figure 188: High Pass filter response for high frequency and low frequency input. Low pass filter response to high frequency input

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cutoff frequency and vice-versa. Cutoff frequency variation for high pass filter is shown below. By decreasing the clock frequency, an input frequency that was intitally in pass band of the filter is shown to attenuate with decreasing clock frequency.

5. Specifications Optimization for instance size was done while designing the layout for each unit. After achieving DRC and LVS clean designs, the second phase of optimization was performed to realize a truly engineered design. Guard rings were addded to high pass filter block and the digital unit. Guard rings couldn’t be added to low pass filter unit because of practical considerations. Additonally, bond pads were added to the final 10 pin design to provide for global connection and electrostatic dischange protection. The bond pads available under the ECE 299 library were first cleaned of DRC errors and then customized according to the final design. The pin layout in detailed as:

Pin # Pin Name Description Specification 1 VDD Global VDD 5V 2 PHI1 Clock 1 Non-Overlapping

clocks 3 PHI2 Clock 2 4 IN Analog Signal Input 5 GND Global Ground 6 VSS Global VSS -5V 7 SEL Filter Selection 1 Bit Input 8 LPFOUT Output of LPF Filter 9 HPFOUT Output of HPF Filter 10 GND Global Ground

Figure 19: High Pass Filter Cutoff frequency tuning

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Figure 21: Integrated design with guard rings and I/O pads

Figure 190: Guard Rings around the Digital Unit (left) and High Pass filter (Top)