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[email protected] [email protected] The Leader in Memory Technology The Leader in Memory Technology High Speed DRAM Interface Changsik Yoo DRAM Design 3 Samsung Electronics

High Speed DRAM Interface - Hanyangiclab.hanyang.ac.kr/research/data/High-speed DRAM interface.pdf · High Speed DRAM Interface Changsik Yoo DRAM Design 3 Samsung Electronics. [email protected]@ieee.org

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[email protected]@ieee.org The Leader in Memory TechnologyThe Leader in Memory Technology

High Speed DRAM Interface

Changsik YooDRAM Design 3

Samsung Electronics

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Memory Channel

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NG(?)

EDOEDO PC66/100PC66/100FPFP

Toggle mode

BEDO

CDRAMVCRAM

FCRAM

SLDRAM

Mosys.DRAM

VRAM SG/SDRAM

DDR SG/SD

VRAM

3D RAM

WRAM

DRAM type

* Graphics

MainMain stream stream

* Specialty

‘94 ‘95 ‘96 ‘97 ‘98 ‘99 ‘00 ‘01 ‘02

DRAM Freq. & Perf.

25MHz( 200MB/S)

50MHz(400MB/S)

100MHz(800MB/S)

800MHz (1.6GB/S)

1.6GHz ?(3.2GB/S ?)

System HW & OS

386/486Win 3.1

Pentium Win 95

PIIWin 98

PIII/P7Win 2K

P7/P8Win ?

PC133PC133

RDRAMRDRAM

DDR SDRAMDDR SDRAM

DRAM Interface Trend

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SSTL Bus for DDR SDRAM

DRAM DRAM DRAMC/A

Buffer

DRAM DRAM DRAMC/A

Buffer

Vterm

Memory ControllerMemory Controller

Rterm

Rstub

Z0=50Ω

DQ & DQS

ClockDriverClockDriver

CLK

CLK

CLK

CLK

DQSDQ

Command & Address

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Clocking of DDR SDRAM

§ Source synchronous clocking using bi-directional data strobe (DQS)ü Write DQ ; center aligned to DQSü Read DQ ; edge aligned to DQS

§ System clock is not used for data transmission.ü System clock is to sample the command/address signals and define the time domain.

§ Signal quality of data strobe is inferior to a free-running clock.ü Then, why don’t we use a free-running clock instead of data strobe?

§ In DRAM and chipset, data sampled by DQS should be transferred to the systemclock domain for internal operation.

DQRCLK

tD

DRAM

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Data Strobe of DDR SDRAM

?

Data Strobe (DQS)

Data (DQ)

DIN buffer

Vref

Dout buffer

Con

trol

ler

x8 DQ

x1 DS

Vtt

Rtt

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Basic Timing of DDR SDRAM

tDQSS =0.75~1.25tCK

DQS-outtAC= 0.1 * tCK tAC = 0.1 * tCK

CK,/CK7.5 ns

DQ-out

DQ-in

tDQSCK = 0.1 * tCK

DQS-in

7.5

3 3

tDS0.5ns

tDH0.5ns

* tDQSQ = 0.5ns (Skew between DQS & DQs)

Write

Read tDQSCK = 0.1 * tCK

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RAMBUS Channel

DR

AM

DR

AM

DR

AM

DR

AM

MemoryControllerMemory

Controller

DQ

RQ

DR

AM

DR

AM

DR

AM

DR

AM

Vterm

ClockDriverClockDriver

CTM

CFM

CTMRead DQ

CFMWrite DQ

Z0=28Ω

CTM = Clock To MasterCFM = Clock From MasterRQ = Command/Address Packet

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Clocking of RAMBUS DRAM

§ Source synchronous clocking using free-running clocksü Write DQ ; center aligned to CFMü Read DQ ; center aligned to CTM

§ Depending on the physical location of DRAM, the phase difference between CTMand CFM changes.

ü The phase difference is denoted as tTR.ü In DRAM and chipset, some special circuitry is included to handle tTR.

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Future Memory Channel ; ?§ Point-to-point bus can give much higher data rate than a multi-drop bus.ü How to terminate the bus?

§ Graphic DDR SDRAM is now targeting ~1Gbps data rate.§ Then, why don’t we use point-to-point DRAM channel?

ü Limited memory capacity

§ Serial chain style busü Media RAM by MicroUnity (US Patent 5742840)

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Future Memory Channel ; ??§ Simultaneous bi-directional busü In multi-drop bus, it is difficult to extract the input data stream from a data stream onthe channel.ü Imagine when you want to write to module 1 while you read from module 2. DRAMs onthe module 1 do not have any information on the data pattern read from module 2.ü So, this technique can be used only for point-to-point bus.

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Future Memory Channel ; DDR-II§ In JEDEC, DDR-II targeting 667Mb/s/pin is being defined as an extension of DDR.§ Interface is defined at VDDQ=1.8V.§ SSTL bus structure has been modified for higher data rate.ü ODT (On Die Termination) is employed for better signal integrity.ü ODT gives smaller ISI and better voltage margin.

§ For detailed information on DDR-II, see JEDEC web-site.

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Future Memory Channel ; Yellow Stonehttp://www.rambus.com

For consumer and communications applications

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Future Memory Channel ; 4 PAM Signaling

J. Zerbe, et al., “1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus” JSSC, May, 2001

§ Timing burden relaxed but voltage margin reduced§ For high data rate multi-drop bus, attenuation is a serious problem and thusvoltage margin is a big issue.ü Current integrating input receiver is used to filter out the noise.

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Wider RAMBUS Channel ; 32 Bit Channelhttp://www.rambus.com/developer/downloads/RIMM3264_06.12.pdf

16 bit channel currently in use 32 bit channel

Number of module connector pins = Money

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Interface Circuits

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Timing and Voltage Specifications

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Timing Budget Calculation - An Example

625psHalf bit time

250pstQ of chipset

200pstSH of RDRAM

100pstCE ; Channel effect

50pstJ ; Clock jitter

25psMargin

§ For RAMBUS read case at 800Mbps operation§ tQ and tSH are from data books while the other numbers are arbitrarily chosen.

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Delay Locked Loop

DDR SDRAM RAMBUS DRAM

No YesWrite DLL

Yes YesRead DLL

No YesQuadrature clock

No YesDuty correction

< 200 cycles ~ µsLocking time

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DLL for DDR SDRAM

∆ ∆ ∆ ∆ ∆ ∆ ∆

MUX

MUX Inte

rpol

ater

Compensation delay

Data path16 16

Direct PD &Control logic

CLK(SSTL)

All digital control including DCC

ISSCC’01

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Digital Duty Cycle CorrectionISSCC’01

extCLK

intCLK

intCLKB_FB

tH

tCC-tH

tCC-2*tH

tCC/2-tH

tCC/2

intCLKB

§ For power saving, it is desirable to turn off DLL during standby (pre-charge) statein DDR SDRAM.§ For fast standby exit, all the locking information including DCC is stored as digitalcodes.ü If DCC is done by analog integrator as in RAMBUS DRAM, standby exit time would belimited by DCC re-locking.

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DLL for RAMBUS DRAM ; R-Loop

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DLL for RAMBUS DRAM ; T-Loop

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Input Receiver ; DDR SDRAM

§ Single-ended DQ inputü Different low and high transition delay

§ DQ is sampled by DQS after being buffered toCMOS level.ü Delay matching between DQ and DQS is critical.ü Delay mismatch directly affects tSH.

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• DIND : Input data after Din buffer• PE : Pulse generated by the rising edge of DQS• PO : Pulse generated by the falling edge of DQS• PCK : Internal Pulse generated by the rising edge of CLK

D Q D Q

D Q

DIN

DQS

CLK

DIND DINED DINEDD

DINOD

Latch&

WriteDriver(even)

Latch&

WriteDriver(odd)

PCKDELAYED

PULSE

PULSEGEN.

PO

PEBuffer

Vref

Vref

Vref

+

-

+

-

+

-

Data Input Sampling ; DDR SDRAM

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x8 DQ

x1 DS

Output Driver ; DDR SDRAM§ Voltage mode push-pull driver ; small rON§ Key issuesü Through current from VddQ to VssQü Tri-state control ; timing control not easyü Simultaneous switching noise ; tQ degradation

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Simultaneous Switching Noise

VDD

VSS

VDD

VSS

VDDQ

VSSQ

DOP

DON

to off-chip

VDDQ/VSSQVDD/VSS

VDD

VSS

VDD

VSS

DQ

VDDQ

VSSQ

DQ[0:7]

DQ[8:15]

DQ[0:14]

DQ[15]

VDDQ

VSSQ

VDDQ

VSSQ

DQ[0:14]

DQ[15]

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VDDQ

VSSQ

DQ[0:7]

DQ[8:15]

DQ[0:14]

DQ[15]

VDDQ

VSSQ

VDDQ

VSSQ

DQ[0:14]

DQ[15]

DON[0:14]

DOP[0:14]

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

VSSQ

DOP

DON

DQ

VDDQ/VSSQ

VDD

VSS

VDD

VSS

VDD/VSS

to off-chip

Simultaneous Switching Noise Reduction

ISSCC’01

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Slew Rate Control Method

Predriver Driver

DQ

Cload

Predriver Driver

DQ

Cload

§ Slew rate control should be independent of driver strength control.

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Input Receiver ; RAMBUS DRAM

Clk

IN Ref

Bias

Out

Outb

Clk

B. Lau, et al., “A 2.6-GByte/s Multipurpose Chip-to-Chip Interface” JSSC, NOV. 1998

Pre-amplifier• Role? • Gain?

Sense-amplifier RS-latch

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Input Related AC Specifications

Input setup and hold timetSH

Input receiver uncertainty windowDLL clock jitter

Clock centering errorClock duty cycle error

Input voltage marginViH / ViLtTR (RQ and DQ coupling effect)Input receiver kick-back noise

Pre-amplifier design

What is this?Spec. Determining factors

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Read Data Output Circuitry ; RAMBUS

status

trace line

enable

nMOS array

data_e

Leveldetection

Vterm

FSM & counter(level control)

P.V.detection

Data slewcontroldata_o

clkb

clk pin_en

initial

Rterm

pad &package

7

§ For good design, parasitics such as metal line resistance/capacitance and packageinductance/capacitance should be modeled as accurate as possible.§ Revision is money !!!

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Output Swing Level Detection ; RAMBUS

FSM &Counter

Vref

Vterm

Vterm 0

VOH

VOL

VM

Ctrl[5:0]

ini

ini

B. Lau, et al., “A 2.6-GByte/s Multipurpose Chip-to-Chip Interface” JSSC, NOV. 1998

The effect of these resistors should be compensated.

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Why Current Mode Driver in RAMBUS?

§ If it is voltage mode driver, the reflected wave from chipset is reflected once againat the driver and these reflections will persist for long, deteriorating the signalintegrity.

§ The RAMBUS output driver is specified to give larger than 150-Ohm outputresistance.

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Summary

§ Data rate of DRAM channel is continuously increasing.ü 800Mbps is in mass production.ü 1066Mbps looks feasible with minor changes.ü 1200Mbps, 1600Mbps … .. will be seen in near future.

§ In DRAM channel, peak data rate does not tell everything.ü It is only one of many factors determining the memory system performance.

§ In order to devise a high-performance DRAM channel, good understanding ofmemory system is required.