Homework #3 Solution (Summer 2000) - CAE Usershomepages.cae.wisc.edu/~ece352/summer00/homework/... · Homework 3, Summer 2000 Page 4 ECE/CS/352 6). (JK Flip-Flop Analysis) Book problem

Homework 3, Summer 2000 Page 1 ECE/CS/352

Department of Electrical and Computer Engineering University of Wisconsin - Madison

ECE/Comp Sci 352 Digital System Fundamentals

Homework #3 Solution (Summer 2000)

1). (Timing Characteristics) A logic family has the following characteristics:

Parameter Value (all times in nanoseconds)

Flip Flop Clock to output tpLH (min) = 2.0, tpLH (max) = 4.0 tpHL (min) = 1.0, tpHL (max) = 3.0

Flip-Flop Setup time tsu = 3.0 (min)

Flip-flop Hold time th = 0.0 (min)

Logic gate delay tpLH (min) = 1.0, tpLH (max) = 3.0 tpHL (min) = 0.5, tpHL (max) = 2.0

What is the maximum clock speed for the circuit when:

Answer:

(a). There are 4 levels of combinatorial logic delay between flip-flops?

F =1/period = 1/(4.0 + 4*3.0 + 3.0) = 1/(19 ns.) = 52.6 MHz. (b). There are 8 levels of combinatorial logic delay between flip-flops?

F = 1/period = 1/(4.0 + 8*3 + 3.0) = 1/(31 ns.) = 32.3 MHz.

Assuming that the implementing logic is NAND gates, does this affect the clock frequency calculation? How? (Hint: NAND gates invert.)

Yes it affects the logic delay since inverting pairs can use tpLH(max) and tpHL(max) for 2.0+3.0=5.0 ns rather than 2*3.0 = 6.0 ns.


2). (Characteristic tables) Book problem 4-10, page 240.

3). (D-type Flip Flop Analysis) Book problem 4-11.


4). (Serial Adder Sequential Circuit Analysis) Book problem 4-13.

5). (State Diagram Behavior) Book problem 4-15.


6). (JK Flip-Flop Analysis) Book problem 4-18.

7). (D Flip-Flop Sequential Circuit Design) Book problem 4-19.


8). (Set-Dominant SR Flip-Flop Characteristics) Book problem 4-26.

9). (JK Flip Flop Sequential Circuit Design) Book Problem 4-30.


10). (SR Flip Flop Sequential Circuit Design) Book Problem 4-35.

11). (T Flip-Flop Sequential Circuit Design. Book Problem 4-36


12). (Shift Register) It is desired to use a 4-bit wide, D-type, edge triggered Flip-Flop and multiplexers to build a four bit shift register. Design the circuit that will implement the following shift register commands:

Control Input S1 S0

Meaning

0 0 Hold (no shift)

0 1 Shift right -- MSB toward LSB.

1 0 Shift left -- shift data left (LSB toward MSB.

1 1 Load -- Pre-load the data from four separate input lines.

Using four of the 4-bit shift registers designed above, implement a 16 bit shift register.

4-Bit Shift Register 16 Bit Shift Register


13). (Ripple Counters) -- Book Problem 5-16.

14). (Synchronous Counters) -- Book Problem 5-17.

15). (Load/Count Counters) -- Book Problem 5-22.


16). (Other Count Sequences) -- Using two T Flip-Flops, design a counter that counts 0-1-3-2-0-1-3-2, etc.

T1 T2

T1 = X Y’ + X C’ + X’Y C T2 = X Y + Y C’ + X’Y’C

Present State Count Next State T1 T2X Y X(t+1) Y(t+1)

0 0 0 0 0 0 00 0 1 0 1 0 10 1 0 0 0 0 10 1 1 1 1 1 01 0 0 0 0 1 01 0 1 0 0 1 01 1 0 0 0 1 11 1 1 1 0 0 1

C C1 1 1

X 1 1 1 X 1 1 Y Y

Q

QSET

CLR

T

Q

QSET

CLR

T

X

Y

T1

T2

COUNT


17). (Other Count Sequences) -- Switch Tail Ring Counter/Johnson Counter -- Book Problem 5-12. What happens in either case if the state is initially "0101"? Draw a complete state transition diagram of the counters showing the sequence transitions for all possible initial states.

a). The shift register states are:

1000 to 0100 to 0010 to 0001 to 1000, etc. (Cycle repeats)

b) Switch Tail Ring (Johnson) states starting from 0000 are:

0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, etc. (Cycle repeats)

c). There are 2*n states for an n-bit switch-tail ring counter.

Here is the state transition tables for both counter types. You draw the diagrams.

Initial State Next State Switch Tail

Next State SR

0000 1000 0000 0001 0000 1000 0010 1001 0001 0011 0001 1001 0100 1010 0010 0101 0010 1010 0110 1011 0011 0111 0011 1011 1000 1100 0100 1001 0100 1100 1010 1101 0101 1011 0101 1101 1100 1110 0110 1101 0110 1110 1110 1111 0111 1111 0111 1111


18) (Asynchronous Design Concepts) -- Using a four-bit ripple counter (Figure 5-8 in the book) and a 3-input NOR gate connected to the Q0, Q1 and Q3 outputs to decode the states "0000", "0100", show how, and at what counts, short "glitches" can occur. Assume that the clock to output for the flip-flop is 20 ns. and the gate delay is 5 ns. Plot the waveform of one such "glitch" in detail.

Answer: Flip-flop outputs change interval of 20 ns. from the clock edge. The table below shows the output states attained after the clock: (NC = no change). The underlined entries represent temporary states which will be incorrectly decoded by the NOR gate, producing a "glitch" (delayed by 5 ns.).

Initial State Before CLK

CLK +20 CLK + 40

CLK + 60

CLK + 80

0000 0001 NC

0001 0000 0010 NC

0010 0011 NC

0011 0010 0000 0100 NC

0100 0101 NC

0101 0100 0110 NC

0110 0111 NC

0111 0110 0100 0000 1000

1000 1001 NC

1001 1000 1010 NC

1010 1011 NC

1011 1010 1000 1100 NC

1100 1101 NC

1101 1100 1110 NC

1110 1111 NC

1111 1110 1100 1000 0000


19). (Asynchronous Design Concepts) -- Using the circuit of Figure 3-6 in Supplement 3, eliminate gates to introduce a hazard and determine the input change required to cause the hazard. Using a 5 ns. gate delay, plot a simulation waveform for each case, showing the hazard. The cases to be simulated are:

a). Eliminate the NAND gate for the term (B•C)'.

b). Eliminate the NAND gate for the term (A•C)'.


20). (Ripple Counter) Study the circuit diagrams below and determine which counters:

a). count up, (note that "A" is the LSB and "B" is the MSB) b). count down, c). are synchronous, d). may be "paused" at any count using the control line "X".

Answer:

Feature 1 2 3 4

Count Up X X

Count Down X

Synchronous X X X

Paused by X X X

21). (RAM Organization) -- Book Problem 6-1.


CP

D Q

Q

AD Q

Q

B

BX

CP

T Q

Q

AT Q

Q

X

T Q

Q

AT Q

Q

BX

CP

D Q

Q

AT Q

Q

BX

B

Counter #1 Counter #3

Counter #2 Counter #4

CP



24). (ROM) -- Book Problem 6-14.

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Homework #3 Solution (Summer 2000) - CAE Usershomepages.cae.wisc.edu/~ece352/summer00/homework/... · Homework 3, Summer 2000 Page 4 ECE/CS/352 6). (JK Flip-Flop Analysis) Book problem